pinctrl-rk805.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494
  1. /*
  2. * Pinctrl driver for Rockchip RK805 PMIC
  3. *
  4. * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
  5. *
  6. * Author: Joseph Chen <chenjh@rock-chips.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * Based on the pinctrl-as3722 driver
  14. */
  15. #include <linux/gpio/driver.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/mfd/rk808.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/pinctrl/consumer.h>
  23. #include <linux/pinctrl/machine.h>
  24. #include <linux/pinctrl/pinctrl.h>
  25. #include <linux/pinctrl/pinconf-generic.h>
  26. #include <linux/pinctrl/pinconf.h>
  27. #include <linux/pinctrl/pinmux.h>
  28. #include <linux/pm.h>
  29. #include <linux/slab.h>
  30. #include "core.h"
  31. #include "pinconf.h"
  32. #include "pinctrl-utils.h"
  33. struct rk805_pin_function {
  34. const char *name;
  35. const char *const *groups;
  36. unsigned int ngroups;
  37. int mux_option;
  38. };
  39. struct rk805_pin_group {
  40. const char *name;
  41. const unsigned int pins[1];
  42. unsigned int npins;
  43. };
  44. /*
  45. * @reg: gpio setting register;
  46. * @fun_mask: functions select mask value, when set is gpio;
  47. * @dir_mask: input or output mask value, when set is output, otherwise input;
  48. * @val_mask: gpio set value, when set is level high, otherwise low;
  49. *
  50. * Different PMIC has different pin features, belowing 3 mask members are not
  51. * all necessary for every PMIC. For example, RK805 has 2 pins that can be used
  52. * as output only GPIOs, so func_mask and dir_mask are not needed. RK816 has 1
  53. * pin that can be used as TS/GPIO, so fun_mask, dir_mask and val_mask are all
  54. * necessary.
  55. */
  56. struct rk805_pin_config {
  57. u8 reg;
  58. u8 fun_msk;
  59. u8 dir_msk;
  60. u8 val_msk;
  61. };
  62. struct rk805_pctrl_info {
  63. struct rk808 *rk808;
  64. struct device *dev;
  65. struct pinctrl_dev *pctl;
  66. struct gpio_chip gpio_chip;
  67. struct pinctrl_desc pinctrl_desc;
  68. const struct rk805_pin_function *functions;
  69. unsigned int num_functions;
  70. const struct rk805_pin_group *groups;
  71. int num_pin_groups;
  72. const struct pinctrl_pin_desc *pins;
  73. unsigned int num_pins;
  74. struct rk805_pin_config *pin_cfg;
  75. };
  76. enum rk805_pinmux_option {
  77. RK805_PINMUX_GPIO,
  78. };
  79. enum {
  80. RK805_GPIO0,
  81. RK805_GPIO1,
  82. };
  83. static const char *const rk805_gpio_groups[] = {
  84. "gpio0",
  85. "gpio1",
  86. };
  87. /* RK805: 2 output only GPIOs */
  88. static const struct pinctrl_pin_desc rk805_pins_desc[] = {
  89. PINCTRL_PIN(RK805_GPIO0, "gpio0"),
  90. PINCTRL_PIN(RK805_GPIO1, "gpio1"),
  91. };
  92. static const struct rk805_pin_function rk805_pin_functions[] = {
  93. {
  94. .name = "gpio",
  95. .groups = rk805_gpio_groups,
  96. .ngroups = ARRAY_SIZE(rk805_gpio_groups),
  97. .mux_option = RK805_PINMUX_GPIO,
  98. },
  99. };
  100. static const struct rk805_pin_group rk805_pin_groups[] = {
  101. {
  102. .name = "gpio0",
  103. .pins = { RK805_GPIO0 },
  104. .npins = 1,
  105. },
  106. {
  107. .name = "gpio1",
  108. .pins = { RK805_GPIO1 },
  109. .npins = 1,
  110. },
  111. };
  112. #define RK805_GPIO0_VAL_MSK BIT(0)
  113. #define RK805_GPIO1_VAL_MSK BIT(1)
  114. static struct rk805_pin_config rk805_gpio_cfgs[] = {
  115. {
  116. .reg = RK805_OUT_REG,
  117. .val_msk = RK805_GPIO0_VAL_MSK,
  118. },
  119. {
  120. .reg = RK805_OUT_REG,
  121. .val_msk = RK805_GPIO1_VAL_MSK,
  122. },
  123. };
  124. /* generic gpio chip */
  125. static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
  126. {
  127. struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
  128. int ret, val;
  129. ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val);
  130. if (ret) {
  131. dev_err(pci->dev, "get gpio%d value failed\n", offset);
  132. return ret;
  133. }
  134. return !!(val & pci->pin_cfg[offset].val_msk);
  135. }
  136. static void rk805_gpio_set(struct gpio_chip *chip,
  137. unsigned int offset,
  138. int value)
  139. {
  140. struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
  141. int ret;
  142. ret = regmap_update_bits(pci->rk808->regmap,
  143. pci->pin_cfg[offset].reg,
  144. pci->pin_cfg[offset].val_msk,
  145. value ? pci->pin_cfg[offset].val_msk : 0);
  146. if (ret)
  147. dev_err(pci->dev, "set gpio%d value %d failed\n",
  148. offset, value);
  149. }
  150. static int rk805_gpio_direction_input(struct gpio_chip *chip,
  151. unsigned int offset)
  152. {
  153. return pinctrl_gpio_direction_input(chip->base + offset);
  154. }
  155. static int rk805_gpio_direction_output(struct gpio_chip *chip,
  156. unsigned int offset, int value)
  157. {
  158. rk805_gpio_set(chip, offset, value);
  159. return pinctrl_gpio_direction_output(chip->base + offset);
  160. }
  161. static int rk805_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  162. {
  163. struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
  164. unsigned int val;
  165. int ret;
  166. /* default output*/
  167. if (!pci->pin_cfg[offset].dir_msk)
  168. return 0;
  169. ret = regmap_read(pci->rk808->regmap,
  170. pci->pin_cfg[offset].reg,
  171. &val);
  172. if (ret) {
  173. dev_err(pci->dev, "get gpio%d direction failed\n", offset);
  174. return ret;
  175. }
  176. return !(val & pci->pin_cfg[offset].dir_msk);
  177. }
  178. static struct gpio_chip rk805_gpio_chip = {
  179. .label = "rk805-gpio",
  180. .request = gpiochip_generic_request,
  181. .free = gpiochip_generic_free,
  182. .get_direction = rk805_gpio_get_direction,
  183. .get = rk805_gpio_get,
  184. .set = rk805_gpio_set,
  185. .direction_input = rk805_gpio_direction_input,
  186. .direction_output = rk805_gpio_direction_output,
  187. .can_sleep = true,
  188. .base = -1,
  189. .owner = THIS_MODULE,
  190. };
  191. /* generic pinctrl */
  192. static int rk805_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  193. {
  194. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  195. return pci->num_pin_groups;
  196. }
  197. static const char *rk805_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  198. unsigned int group)
  199. {
  200. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  201. return pci->groups[group].name;
  202. }
  203. static int rk805_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  204. unsigned int group,
  205. const unsigned int **pins,
  206. unsigned int *num_pins)
  207. {
  208. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  209. *pins = pci->groups[group].pins;
  210. *num_pins = pci->groups[group].npins;
  211. return 0;
  212. }
  213. static const struct pinctrl_ops rk805_pinctrl_ops = {
  214. .get_groups_count = rk805_pinctrl_get_groups_count,
  215. .get_group_name = rk805_pinctrl_get_group_name,
  216. .get_group_pins = rk805_pinctrl_get_group_pins,
  217. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  218. .dt_free_map = pinctrl_utils_free_map,
  219. };
  220. static int rk805_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
  221. {
  222. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  223. return pci->num_functions;
  224. }
  225. static const char *rk805_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
  226. unsigned int function)
  227. {
  228. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  229. return pci->functions[function].name;
  230. }
  231. static int rk805_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
  232. unsigned int function,
  233. const char *const **groups,
  234. unsigned int *const num_groups)
  235. {
  236. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  237. *groups = pci->functions[function].groups;
  238. *num_groups = pci->functions[function].ngroups;
  239. return 0;
  240. }
  241. static int _rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev,
  242. unsigned int offset,
  243. int mux)
  244. {
  245. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  246. int ret;
  247. if (!pci->pin_cfg[offset].fun_msk)
  248. return 0;
  249. if (mux == RK805_PINMUX_GPIO) {
  250. ret = regmap_update_bits(pci->rk808->regmap,
  251. pci->pin_cfg[offset].reg,
  252. pci->pin_cfg[offset].fun_msk,
  253. pci->pin_cfg[offset].fun_msk);
  254. if (ret) {
  255. dev_err(pci->dev, "set gpio%d GPIO failed\n", offset);
  256. return ret;
  257. }
  258. } else {
  259. dev_err(pci->dev, "Couldn't find function mux %d\n", mux);
  260. return -EINVAL;
  261. }
  262. return 0;
  263. }
  264. static int rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev,
  265. unsigned int function,
  266. unsigned int group)
  267. {
  268. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  269. int mux = pci->functions[function].mux_option;
  270. int offset = group;
  271. return _rk805_pinctrl_set_mux(pctldev, offset, mux);
  272. }
  273. static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  274. struct pinctrl_gpio_range *range,
  275. unsigned int offset, bool input)
  276. {
  277. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  278. int ret;
  279. /* switch to gpio function */
  280. ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
  281. if (ret) {
  282. dev_err(pci->dev, "set gpio%d mux failed\n", offset);
  283. return ret;
  284. }
  285. /* set direction */
  286. if (!pci->pin_cfg[offset].dir_msk)
  287. return 0;
  288. ret = regmap_update_bits(pci->rk808->regmap,
  289. pci->pin_cfg[offset].reg,
  290. pci->pin_cfg[offset].dir_msk,
  291. input ? 0 : pci->pin_cfg[offset].dir_msk);
  292. if (ret) {
  293. dev_err(pci->dev, "set gpio%d direction failed\n", offset);
  294. return ret;
  295. }
  296. return ret;
  297. }
  298. static const struct pinmux_ops rk805_pinmux_ops = {
  299. .get_functions_count = rk805_pinctrl_get_funcs_count,
  300. .get_function_name = rk805_pinctrl_get_func_name,
  301. .get_function_groups = rk805_pinctrl_get_func_groups,
  302. .set_mux = rk805_pinctrl_set_mux,
  303. .gpio_set_direction = rk805_pmx_gpio_set_direction,
  304. };
  305. static int rk805_pinconf_get(struct pinctrl_dev *pctldev,
  306. unsigned int pin, unsigned long *config)
  307. {
  308. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  309. enum pin_config_param param = pinconf_to_config_param(*config);
  310. u32 arg = 0;
  311. switch (param) {
  312. case PIN_CONFIG_OUTPUT:
  313. arg = rk805_gpio_get(&pci->gpio_chip, pin);
  314. break;
  315. default:
  316. dev_err(pci->dev, "Properties not supported\n");
  317. return -ENOTSUPP;
  318. }
  319. *config = pinconf_to_config_packed(param, (u16)arg);
  320. return 0;
  321. }
  322. static int rk805_pinconf_set(struct pinctrl_dev *pctldev,
  323. unsigned int pin, unsigned long *configs,
  324. unsigned int num_configs)
  325. {
  326. struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
  327. enum pin_config_param param;
  328. u32 i, arg = 0;
  329. for (i = 0; i < num_configs; i++) {
  330. param = pinconf_to_config_param(configs[i]);
  331. arg = pinconf_to_config_argument(configs[i]);
  332. switch (param) {
  333. case PIN_CONFIG_OUTPUT:
  334. rk805_gpio_set(&pci->gpio_chip, pin, arg);
  335. rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
  336. break;
  337. default:
  338. dev_err(pci->dev, "Properties not supported\n");
  339. return -ENOTSUPP;
  340. }
  341. }
  342. return 0;
  343. }
  344. static const struct pinconf_ops rk805_pinconf_ops = {
  345. .pin_config_get = rk805_pinconf_get,
  346. .pin_config_set = rk805_pinconf_set,
  347. };
  348. static struct pinctrl_desc rk805_pinctrl_desc = {
  349. .name = "rk805-pinctrl",
  350. .pctlops = &rk805_pinctrl_ops,
  351. .pmxops = &rk805_pinmux_ops,
  352. .confops = &rk805_pinconf_ops,
  353. .owner = THIS_MODULE,
  354. };
  355. static int rk805_pinctrl_probe(struct platform_device *pdev)
  356. {
  357. struct rk805_pctrl_info *pci;
  358. int ret;
  359. pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
  360. if (!pci)
  361. return -ENOMEM;
  362. pci->dev = &pdev->dev;
  363. pci->dev->of_node = pdev->dev.parent->of_node;
  364. pci->rk808 = dev_get_drvdata(pdev->dev.parent);
  365. pci->pinctrl_desc = rk805_pinctrl_desc;
  366. pci->gpio_chip = rk805_gpio_chip;
  367. pci->gpio_chip.parent = &pdev->dev;
  368. pci->gpio_chip.of_node = pdev->dev.parent->of_node;
  369. platform_set_drvdata(pdev, pci);
  370. switch (pci->rk808->variant) {
  371. case RK805_ID:
  372. pci->pins = rk805_pins_desc;
  373. pci->num_pins = ARRAY_SIZE(rk805_pins_desc);
  374. pci->functions = rk805_pin_functions;
  375. pci->num_functions = ARRAY_SIZE(rk805_pin_functions);
  376. pci->groups = rk805_pin_groups;
  377. pci->num_pin_groups = ARRAY_SIZE(rk805_pin_groups);
  378. pci->pinctrl_desc.pins = rk805_pins_desc;
  379. pci->pinctrl_desc.npins = ARRAY_SIZE(rk805_pins_desc);
  380. pci->pin_cfg = rk805_gpio_cfgs;
  381. pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs);
  382. break;
  383. default:
  384. dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
  385. pci->rk808->variant);
  386. return -EINVAL;
  387. }
  388. /* Add gpio chip */
  389. ret = devm_gpiochip_add_data(&pdev->dev, &pci->gpio_chip, pci);
  390. if (ret < 0) {
  391. dev_err(&pdev->dev, "Couldn't add gpiochip\n");
  392. return ret;
  393. }
  394. /* Add pinctrl */
  395. pci->pctl = devm_pinctrl_register(&pdev->dev, &pci->pinctrl_desc, pci);
  396. if (IS_ERR(pci->pctl)) {
  397. dev_err(&pdev->dev, "Couldn't add pinctrl\n");
  398. return PTR_ERR(pci->pctl);
  399. }
  400. /* Add pin range */
  401. ret = gpiochip_add_pin_range(&pci->gpio_chip, dev_name(&pdev->dev),
  402. 0, 0, pci->gpio_chip.ngpio);
  403. if (ret < 0) {
  404. dev_err(&pdev->dev, "Couldn't add gpiochip pin range\n");
  405. return ret;
  406. }
  407. return 0;
  408. }
  409. static struct platform_driver rk805_pinctrl_driver = {
  410. .probe = rk805_pinctrl_probe,
  411. .driver = {
  412. .name = "rk805-pinctrl",
  413. },
  414. };
  415. module_platform_driver(rk805_pinctrl_driver);
  416. MODULE_DESCRIPTION("RK805 pin control and GPIO driver");
  417. MODULE_AUTHOR("Joseph Chen <chenjh@rock-chips.com>");
  418. MODULE_LICENSE("GPL v2");