pinctrl-paris.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
  4. * bindings for MediaTek SoC.
  5. *
  6. * Copyright (C) 2018 MediaTek Inc.
  7. * Author: Sean Wang <sean.wang@mediatek.com>
  8. * Zhiyong Tao <zhiyong.tao@mediatek.com>
  9. * Hongzhou.Yang <hongzhou.yang@mediatek.com>
  10. */
  11. #include <linux/of_address.h>
  12. #include <dt-bindings/pinctrl/mt65xx.h>
  13. #include "pinctrl-paris.h"
  14. #include "pinctrl-mtk-common-v2_debug.h"
  15. #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
  16. /* Custom pinconf parameters */
  17. #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
  18. #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
  19. #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
  20. #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
  21. #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
  22. static const struct pinconf_generic_params mtk_custom_bindings[] = {
  23. {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
  24. {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
  25. {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
  26. {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
  27. {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
  28. };
  29. #ifdef CONFIG_DEBUG_FS
  30. static const struct pin_config_item mtk_conf_items[] = {
  31. PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
  32. PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
  33. PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
  34. PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
  35. PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
  36. };
  37. #endif
  38. static const char * const mtk_gpio_functions[] = {
  39. "func0", "func1", "func2", "func3",
  40. "func4", "func5", "func6", "func7",
  41. "func8", "func9", "func10", "func11",
  42. "func12", "func13", "func14", "func15",
  43. };
  44. static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
  45. struct pinctrl_gpio_range *range,
  46. unsigned int pin)
  47. {
  48. int err;
  49. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  50. const struct mtk_pin_desc *desc;
  51. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  52. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
  53. hw->soc->gpio_m);
  54. if (err)
  55. return err;
  56. if (hw->soc->eh_pin_pinmux)
  57. mtk_eh_ctrl(hw, desc, hw->soc->gpio_m);
  58. return 0;
  59. }
  60. static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
  61. struct pinctrl_gpio_range *range,
  62. unsigned int pin, bool input)
  63. {
  64. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  65. const struct mtk_pin_desc *desc;
  66. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  67. /* hardware would take 0 as input direction */
  68. return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
  69. }
  70. static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
  71. unsigned int pin, unsigned long *config)
  72. {
  73. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  74. u32 param = pinconf_to_config_param(*config);
  75. int err, reg, ret = 1;
  76. int pullup;
  77. const struct mtk_pin_desc *desc;
  78. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  79. switch (param) {
  80. case PIN_CONFIG_BIAS_DISABLE:
  81. case PIN_CONFIG_BIAS_PULL_UP:
  82. case PIN_CONFIG_BIAS_PULL_DOWN:
  83. if (hw->soc->bias_get_combo) {
  84. err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
  85. if (err)
  86. goto out;
  87. if (param == PIN_CONFIG_BIAS_DISABLE) {
  88. if (ret == MTK_PUPD_SET_R1R0_00)
  89. ret = MTK_DISABLE;
  90. } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
  91. /* When desire to get pull-up value,
  92. * return error if current setting is pull-down
  93. */
  94. if (!pullup)
  95. err = -EINVAL;
  96. } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
  97. /* When desire to get pull-down value,
  98. * return error if current setting is pull-up
  99. */
  100. if (pullup)
  101. err = -EINVAL;
  102. }
  103. } else {
  104. err = -ENOTSUPP;
  105. }
  106. break;
  107. case PIN_CONFIG_SLEW_RATE:
  108. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
  109. break;
  110. case PIN_CONFIG_INPUT_ENABLE:
  111. case PIN_CONFIG_OUTPUT_ENABLE:
  112. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
  113. if (err)
  114. goto out;
  115. /* CONFIG Current direction return value
  116. * ------------- ----------------- ----------------------
  117. * OUTPUT_ENABLE output 1 (= HW value)
  118. * input 0 (= HW value)
  119. * INPUT_ENABLE output 0 (= reverse HW value)
  120. * input 1 (= reverse HW value)
  121. */
  122. if (param == PIN_CONFIG_INPUT_ENABLE)
  123. ret = !ret;
  124. break;
  125. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  126. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
  127. if (err)
  128. goto out;
  129. /* return error when in output mode
  130. * because schmitt trigger only work in input mode
  131. */
  132. if (ret) {
  133. err = -EINVAL;
  134. goto out;
  135. }
  136. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
  137. break;
  138. case PIN_CONFIG_DRIVE_STRENGTH:
  139. if (hw->soc->drive_get)
  140. err = hw->soc->drive_get(hw, desc, &ret);
  141. else
  142. err = -ENOTSUPP;
  143. break;
  144. case MTK_PIN_CONFIG_TDSEL:
  145. case MTK_PIN_CONFIG_RDSEL:
  146. reg = (param == MTK_PIN_CONFIG_TDSEL) ?
  147. PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
  148. err = mtk_hw_get_value(hw, desc, reg, &ret);
  149. break;
  150. case MTK_PIN_CONFIG_PU_ADV:
  151. case MTK_PIN_CONFIG_PD_ADV:
  152. if (hw->soc->adv_pull_get) {
  153. bool pullup;
  154. pullup = param == MTK_PIN_CONFIG_PU_ADV;
  155. err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
  156. } else {
  157. err = -ENOTSUPP;
  158. }
  159. break;
  160. case MTK_PIN_CONFIG_DRV_ADV:
  161. if (hw->soc->adv_drive_get) {
  162. err = hw->soc->adv_drive_get(hw, desc, &ret);
  163. if (err)
  164. return err;
  165. } else {
  166. return -ENOTSUPP;
  167. }
  168. break;
  169. default:
  170. err = -ENOTSUPP;
  171. }
  172. out:
  173. if (!err)
  174. *config = pinconf_to_config_packed(param, ret);
  175. return err;
  176. }
  177. static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  178. enum pin_config_param param,
  179. u32 arg)
  180. {
  181. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  182. const struct mtk_pin_desc *desc;
  183. int err = 0;
  184. u32 reg;
  185. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  186. switch ((u32)param) {
  187. case PIN_CONFIG_BIAS_DISABLE:
  188. if (hw->soc->bias_set_combo)
  189. err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
  190. else
  191. err = -ENOTSUPP;
  192. break;
  193. case PIN_CONFIG_BIAS_PULL_UP:
  194. if (hw->soc->bias_set_combo)
  195. err = hw->soc->bias_set_combo(hw, desc, 1, arg);
  196. else
  197. err = -ENOTSUPP;
  198. break;
  199. case PIN_CONFIG_BIAS_PULL_DOWN:
  200. if (hw->soc->bias_set_combo)
  201. err = hw->soc->bias_set_combo(hw, desc, 0, arg);
  202. else
  203. err = -ENOTSUPP;
  204. break;
  205. case PIN_CONFIG_OUTPUT_ENABLE:
  206. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
  207. MTK_DISABLE);
  208. if (err)
  209. goto err;
  210. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  211. MTK_OUTPUT);
  212. break;
  213. case PIN_CONFIG_INPUT_ENABLE:
  214. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
  215. MTK_ENABLE);
  216. if (err)
  217. goto err;
  218. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  219. MTK_INPUT);
  220. break;
  221. case PIN_CONFIG_SLEW_RATE:
  222. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, arg);
  223. break;
  224. case PIN_CONFIG_OUTPUT:
  225. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  226. MTK_OUTPUT);
  227. if (err)
  228. goto err;
  229. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, arg);
  230. break;
  231. case PIN_CONFIG_INPUT_SCHMITT:
  232. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  233. /* arg = 1: Input mode & SMT enable
  234. * arg = 0: Output mode & SMT disable
  235. */
  236. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
  237. if (err)
  238. goto err;
  239. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
  240. break;
  241. case PIN_CONFIG_DRIVE_STRENGTH:
  242. if (hw->soc->drive_set)
  243. err = hw->soc->drive_set(hw, desc, arg);
  244. else
  245. err = -ENOTSUPP;
  246. break;
  247. case MTK_PIN_CONFIG_TDSEL:
  248. case MTK_PIN_CONFIG_RDSEL:
  249. reg = (param == MTK_PIN_CONFIG_TDSEL) ?
  250. PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
  251. err = mtk_hw_set_value(hw, desc, reg, arg);
  252. break;
  253. case MTK_PIN_CONFIG_PU_ADV:
  254. case MTK_PIN_CONFIG_PD_ADV:
  255. if (hw->soc->adv_pull_set) {
  256. bool pullup;
  257. pullup = param == MTK_PIN_CONFIG_PU_ADV;
  258. err = hw->soc->adv_pull_set(hw, desc, pullup,
  259. arg);
  260. } else {
  261. err = -ENOTSUPP;
  262. }
  263. break;
  264. case MTK_PIN_CONFIG_DRV_ADV:
  265. if (hw->soc->adv_drive_set) {
  266. err = hw->soc->adv_drive_set(hw, desc, arg);
  267. if (err)
  268. return err;
  269. } else {
  270. return -ENOTSUPP;
  271. }
  272. break;
  273. default:
  274. err = -ENOTSUPP;
  275. }
  276. err:
  277. return err;
  278. }
  279. static struct mtk_pinctrl_group *
  280. mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
  281. {
  282. int i;
  283. for (i = 0; i < hw->soc->ngrps; i++) {
  284. struct mtk_pinctrl_group *grp = hw->groups + i;
  285. if (grp->pin == pin)
  286. return grp;
  287. }
  288. return NULL;
  289. }
  290. static const struct mtk_func_desc *
  291. mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
  292. {
  293. const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
  294. const struct mtk_func_desc *func = pin->funcs;
  295. while (func && func->name) {
  296. if (func->muxval == fnum)
  297. return func;
  298. func++;
  299. }
  300. return NULL;
  301. }
  302. static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
  303. u32 fnum)
  304. {
  305. int i;
  306. for (i = 0; i < hw->soc->npins; i++) {
  307. const struct mtk_pin_desc *pin = hw->soc->pins + i;
  308. if (pin->number == pin_num) {
  309. const struct mtk_func_desc *func = pin->funcs;
  310. while (func && func->name) {
  311. if (func->muxval == fnum)
  312. return true;
  313. func++;
  314. }
  315. break;
  316. }
  317. }
  318. return false;
  319. }
  320. static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
  321. u32 pin, u32 fnum,
  322. struct mtk_pinctrl_group *grp,
  323. struct pinctrl_map **map,
  324. unsigned int *reserved_maps,
  325. unsigned int *num_maps)
  326. {
  327. bool ret;
  328. if (*num_maps == *reserved_maps)
  329. return -ENOSPC;
  330. (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
  331. (*map)[*num_maps].data.mux.group = grp->name;
  332. ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
  333. if (!ret) {
  334. dev_err(pctl->dev, "invalid function %d on pin %d .\n",
  335. fnum, pin);
  336. return -EINVAL;
  337. }
  338. (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
  339. (*num_maps)++;
  340. return 0;
  341. }
  342. static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  343. struct device_node *node,
  344. struct pinctrl_map **map,
  345. unsigned int *reserved_maps,
  346. unsigned int *num_maps)
  347. {
  348. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  349. int num_pins, num_funcs, maps_per_pin, i, err;
  350. struct mtk_pinctrl_group *grp;
  351. unsigned int num_configs;
  352. bool has_config = false;
  353. unsigned long *configs;
  354. u32 pinfunc, pin, func;
  355. struct property *pins;
  356. unsigned int reserve = 0;
  357. pins = of_find_property(node, "pinmux", NULL);
  358. if (!pins) {
  359. dev_err(hw->dev, "missing pins property in node %pOFn .\n",
  360. node);
  361. return -EINVAL;
  362. }
  363. err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
  364. &num_configs);
  365. if (err)
  366. return err;
  367. if (num_configs)
  368. has_config = true;
  369. num_pins = pins->length / sizeof(u32);
  370. num_funcs = num_pins;
  371. maps_per_pin = 0;
  372. if (num_funcs)
  373. maps_per_pin++;
  374. if (has_config && num_pins >= 1)
  375. maps_per_pin++;
  376. if (!num_pins || !maps_per_pin) {
  377. err = -EINVAL;
  378. goto exit;
  379. }
  380. reserve = num_pins * maps_per_pin;
  381. err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
  382. (unsigned int)reserve);
  383. if (err < 0)
  384. goto exit;
  385. for (i = 0; i < num_pins; i++) {
  386. err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
  387. if (err)
  388. goto exit;
  389. pin = MTK_GET_PIN_NO(pinfunc);
  390. func = MTK_GET_PIN_FUNC(pinfunc);
  391. if (pin >= hw->soc->npins ||
  392. func >= ARRAY_SIZE(mtk_gpio_functions)) {
  393. dev_err(hw->dev, "invalid pins value.\n");
  394. err = -EINVAL;
  395. goto exit;
  396. }
  397. grp = mtk_pctrl_find_group_by_pin(hw, pin);
  398. if (!grp) {
  399. dev_err(hw->dev, "unable to match pin %d to group\n",
  400. pin);
  401. err = -EINVAL;
  402. goto exit;
  403. }
  404. err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
  405. reserved_maps, num_maps);
  406. if (err < 0)
  407. goto exit;
  408. if (has_config) {
  409. err = pinctrl_utils_add_map_configs(pctldev, map,
  410. reserved_maps,
  411. num_maps,
  412. grp->name,
  413. configs,
  414. num_configs,
  415. PIN_MAP_TYPE_CONFIGS_GROUP);
  416. if (err < 0)
  417. goto exit;
  418. }
  419. }
  420. err = 0;
  421. exit:
  422. kfree(configs);
  423. return err;
  424. }
  425. static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
  426. struct device_node *np_config,
  427. struct pinctrl_map **map,
  428. unsigned int *num_maps)
  429. {
  430. struct device_node *np;
  431. unsigned int reserved_maps;
  432. int ret;
  433. *map = NULL;
  434. *num_maps = 0;
  435. reserved_maps = 0;
  436. for_each_child_of_node(np_config, np) {
  437. ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
  438. &reserved_maps,
  439. num_maps);
  440. if (ret < 0) {
  441. pinctrl_utils_free_map(pctldev, *map, *num_maps);
  442. of_node_put(np);
  443. return ret;
  444. }
  445. }
  446. return 0;
  447. }
  448. static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  449. {
  450. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  451. return hw->soc->ngrps;
  452. }
  453. static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  454. unsigned int group)
  455. {
  456. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  457. return hw->groups[group].name;
  458. }
  459. static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  460. unsigned int group,
  461. const unsigned int **pins,
  462. unsigned int *num_pins)
  463. {
  464. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  465. *pins = (unsigned int *)&hw->groups[group].pin;
  466. *num_pins = 1;
  467. return 0;
  468. }
  469. int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
  470. {
  471. const struct mtk_pin_desc *desc;
  472. int value, err;
  473. if (gpio > hw->soc->npins)
  474. return -EINVAL;
  475. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  476. err = mtk_hw_get_value(hw, desc, field, &value);
  477. if (err)
  478. return err;
  479. return value;
  480. }
  481. ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
  482. unsigned int gpio, char *buf, unsigned int bufLen)
  483. {
  484. const struct mtk_pin_desc *desc;
  485. int pinmux, pullup = 0, pullen = 0, r1 = -1, r0 = -1, len = 0;
  486. if (gpio > hw->soc->npins)
  487. return -EINVAL;
  488. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  489. pinmux = mtk_pctrl_get_pinmux(hw, gpio);
  490. if (pinmux >= hw->soc->nfuncs)
  491. pinmux -= hw->soc->nfuncs;
  492. mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
  493. if (pullen == MTK_PUPD_SET_R1R0_00) {
  494. pullen = 0;
  495. r1 = 0;
  496. r0 = 0;
  497. } else if (pullen == MTK_PUPD_SET_R1R0_01) {
  498. pullen = 1;
  499. r1 = 0;
  500. r0 = 1;
  501. } else if (pullen == MTK_PUPD_SET_R1R0_10) {
  502. pullen = 1;
  503. r1 = 1;
  504. r0 = 0;
  505. } else if (pullen == MTK_PUPD_SET_R1R0_11) {
  506. pullen = 1;
  507. r1 = 1;
  508. r0 = 1;
  509. } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
  510. pullen = 0;
  511. }
  512. len += snprintf(buf + len, bufLen - len,
  513. "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
  514. gpio,
  515. pinmux,
  516. mtk_pctrl_get_direction(hw, gpio),
  517. mtk_pctrl_get_out(hw, gpio),
  518. mtk_pctrl_get_in(hw, gpio),
  519. mtk_pctrl_get_driving(hw, gpio),
  520. mtk_pctrl_get_smt(hw, gpio),
  521. mtk_pctrl_get_ies(hw, gpio),
  522. pullen,
  523. pullup);
  524. if (r1 != -1) {
  525. len += snprintf(buf + len, bufLen - len, " (%1d %1d)\n",
  526. r1, r0);
  527. } else {
  528. len += snprintf(buf + len, bufLen - len, "\n");
  529. }
  530. return len;
  531. }
  532. #define PIN_DBG_BUF_SZ 96
  533. static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  534. unsigned int gpio)
  535. {
  536. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  537. char buf[PIN_DBG_BUF_SZ];
  538. (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
  539. seq_printf(s, "%s", buf);
  540. }
  541. static const struct pinctrl_ops mtk_pctlops = {
  542. .dt_node_to_map = mtk_pctrl_dt_node_to_map,
  543. .dt_free_map = pinctrl_utils_free_map,
  544. .get_groups_count = mtk_pctrl_get_groups_count,
  545. .get_group_name = mtk_pctrl_get_group_name,
  546. .get_group_pins = mtk_pctrl_get_group_pins,
  547. .pin_dbg_show = mtk_pctrl_dbg_show,
  548. };
  549. static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
  550. {
  551. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  552. if (hw->soc->nfuncs)
  553. return (int)hw->soc->nfuncs;
  554. return ARRAY_SIZE(mtk_gpio_functions);
  555. }
  556. static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
  557. unsigned int selector)
  558. {
  559. return mtk_gpio_functions[selector];
  560. }
  561. static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
  562. unsigned int function,
  563. const char * const **groups,
  564. unsigned * const num_groups)
  565. {
  566. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  567. *groups = hw->grp_names;
  568. *num_groups = hw->soc->ngrps;
  569. return 0;
  570. }
  571. static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
  572. unsigned int function,
  573. unsigned int group)
  574. {
  575. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  576. struct mtk_pinctrl_group *grp = hw->groups + group;
  577. const struct mtk_func_desc *desc_func;
  578. const struct mtk_pin_desc *desc;
  579. bool ret;
  580. ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
  581. if (!ret) {
  582. dev_err(hw->dev, "invalid function %d on group %d .\n",
  583. function, group);
  584. return -EINVAL;
  585. }
  586. desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
  587. if (!desc_func)
  588. return -EINVAL;
  589. desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
  590. ret = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
  591. desc_func->muxval);
  592. if (ret)
  593. return ret;
  594. if (hw->soc->eh_pin_pinmux)
  595. mtk_eh_ctrl(hw, desc, desc_func->muxval);
  596. return 0;
  597. }
  598. static const struct pinmux_ops mtk_pmxops = {
  599. .get_functions_count = mtk_pmx_get_funcs_cnt,
  600. .get_function_name = mtk_pmx_get_func_name,
  601. .get_function_groups = mtk_pmx_get_func_groups,
  602. .set_mux = mtk_pmx_set_mux,
  603. .gpio_set_direction = mtk_pinmux_gpio_set_direction,
  604. .gpio_request_enable = mtk_pinmux_gpio_request_enable,
  605. };
  606. static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned int group,
  607. unsigned long *config)
  608. {
  609. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  610. *config = hw->groups[group].config;
  611. return 0;
  612. }
  613. static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int group,
  614. unsigned long *configs, unsigned int num_configs)
  615. {
  616. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  617. struct mtk_pinctrl_group *grp = &hw->groups[group];
  618. int i, ret;
  619. for (i = 0; i < num_configs; i++) {
  620. ret = mtk_pinconf_set(pctldev, grp->pin,
  621. pinconf_to_config_param(configs[i]),
  622. pinconf_to_config_argument(configs[i]));
  623. if (ret < 0)
  624. return ret;
  625. grp->config = configs[i];
  626. }
  627. return 0;
  628. }
  629. static const struct pinconf_ops mtk_confops = {
  630. .pin_config_get = mtk_pinconf_get,
  631. .pin_config_group_get = mtk_pconf_group_get,
  632. .pin_config_group_set = mtk_pconf_group_set,
  633. .is_generic = true,
  634. };
  635. static struct pinctrl_desc mtk_desc = {
  636. .name = PINCTRL_PINCTRL_DEV,
  637. .pctlops = &mtk_pctlops,
  638. .pmxops = &mtk_pmxops,
  639. .confops = &mtk_confops,
  640. .owner = THIS_MODULE,
  641. };
  642. static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
  643. {
  644. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  645. const struct mtk_pin_desc *desc;
  646. int value, err;
  647. if (gpio > hw->soc->npins)
  648. return -EINVAL;
  649. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  650. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
  651. if (err)
  652. return err;
  653. return !value;
  654. }
  655. static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
  656. {
  657. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  658. const struct mtk_pin_desc *desc;
  659. int value, err;
  660. if (gpio > hw->soc->npins)
  661. return -EINVAL;
  662. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  663. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
  664. if (err)
  665. return err;
  666. return !!value;
  667. }
  668. static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
  669. {
  670. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  671. const struct mtk_pin_desc *desc;
  672. if (gpio > hw->soc->npins)
  673. return;
  674. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  675. (void)mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
  676. }
  677. static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
  678. {
  679. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  680. if (gpio > hw->soc->npins)
  681. return -EINVAL;
  682. return pinctrl_gpio_direction_input(chip->base + gpio);
  683. }
  684. static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
  685. int value)
  686. {
  687. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  688. if (gpio > hw->soc->npins)
  689. return -EINVAL;
  690. mtk_gpio_set(chip, gpio, value);
  691. return pinctrl_gpio_direction_output(chip->base + gpio);
  692. }
  693. static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  694. {
  695. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  696. const struct mtk_pin_desc *desc;
  697. if (!hw->eint)
  698. return -ENOTSUPP;
  699. desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
  700. if (desc->eint.eint_n == EINT_NA)
  701. return -ENOTSUPP;
  702. return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
  703. }
  704. static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  705. unsigned long config)
  706. {
  707. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  708. const struct mtk_pin_desc *desc;
  709. u32 debounce;
  710. desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
  711. if (!hw->eint ||
  712. pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
  713. desc->eint.eint_n == EINT_NA)
  714. return -ENOTSUPP;
  715. debounce = pinconf_to_config_argument(config);
  716. return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
  717. }
  718. static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
  719. {
  720. struct gpio_chip *chip = &hw->chip;
  721. int ret;
  722. chip->label = PINCTRL_PINCTRL_DEV;
  723. chip->parent = hw->dev;
  724. chip->request = gpiochip_generic_request;
  725. chip->free = gpiochip_generic_free;
  726. chip->get_direction = mtk_gpio_get_direction;
  727. chip->direction_input = mtk_gpio_direction_input;
  728. chip->direction_output = mtk_gpio_direction_output;
  729. chip->get = mtk_gpio_get;
  730. chip->set = mtk_gpio_set;
  731. chip->to_irq = mtk_gpio_to_irq,
  732. chip->set_config = mtk_gpio_set_config,
  733. chip->base = -1;
  734. chip->ngpio = hw->soc->npins;
  735. chip->of_node = np;
  736. chip->of_gpio_n_cells = 2;
  737. ret = gpiochip_add_data(chip, hw);
  738. if (ret < 0)
  739. return ret;
  740. return 0;
  741. }
  742. static int mtk_pctrl_build_state(struct platform_device *pdev)
  743. {
  744. struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
  745. int i;
  746. /* Allocate groups */
  747. hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
  748. sizeof(*hw->groups), GFP_KERNEL);
  749. if (!hw->groups)
  750. return -ENOMEM;
  751. /* We assume that one pin is one group, use pin name as group name. */
  752. hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
  753. sizeof(*hw->grp_names), GFP_KERNEL);
  754. if (!hw->grp_names)
  755. return -ENOMEM;
  756. for (i = 0; i < hw->soc->npins; i++) {
  757. const struct mtk_pin_desc *pin = hw->soc->pins + i;
  758. struct mtk_pinctrl_group *group = hw->groups + i;
  759. group->name = pin->name;
  760. group->pin = pin->number;
  761. hw->grp_names[i] = pin->name;
  762. }
  763. return 0;
  764. }
  765. int mtk_paris_pinctrl_probe(struct platform_device *pdev,
  766. const struct mtk_pin_soc *soc)
  767. {
  768. struct device_node *np = pdev->dev.of_node, *node;
  769. struct pinctrl_pin_desc *pins;
  770. struct mtk_pinctrl *hw;
  771. struct property *prop;
  772. struct resource *res;
  773. int err, i;
  774. hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
  775. if (!hw)
  776. return -ENOMEM;
  777. platform_set_drvdata(pdev, hw);
  778. hw->soc = soc;
  779. hw->dev = &pdev->dev;
  780. if (hw->soc->nbase_names) {
  781. hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
  782. sizeof(*hw->base), GFP_KERNEL);
  783. if (!hw->base)
  784. return -ENOMEM;
  785. for (i = 0; i < hw->soc->nbase_names; i++) {
  786. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  787. hw->soc->base_names[i]);
  788. if (!res) {
  789. dev_err(&pdev->dev, "missing IO resource\n");
  790. return -ENXIO;
  791. }
  792. hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
  793. if (IS_ERR(hw->base[i]))
  794. return PTR_ERR(hw->base[i]);
  795. }
  796. hw->nbase = hw->soc->nbase_names;
  797. } else {
  798. prop = of_find_property(np, "reg_bases", NULL);
  799. if (!prop)
  800. return -ENXIO;
  801. i = prop->length / sizeof(phandle);
  802. if (i < 1)
  803. return -EINVAL;
  804. hw->nbase = i;
  805. hw->base = devm_kmalloc_array(&pdev->dev, i, sizeof(*hw->base),
  806. GFP_KERNEL | __GFP_ZERO);
  807. if (IS_ERR(hw->base))
  808. return PTR_ERR(hw->base);
  809. for (i = 0; i < hw->nbase; i++) {
  810. node = of_parse_phandle(np, "reg_bases", i);
  811. if (!node)
  812. return -EINVAL;
  813. hw->base[i] = of_iomap(node, 0);
  814. if (IS_ERR(hw->base[i]))
  815. return PTR_ERR(hw->base[i]);
  816. of_node_put(node);
  817. }
  818. }
  819. err = mtk_pctrl_build_state(pdev);
  820. if (err) {
  821. dev_err(&pdev->dev, "build state failed: %d\n", err);
  822. return -EINVAL;
  823. }
  824. /* Copy from internal struct mtk_pin_desc to register to the core */
  825. pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
  826. GFP_KERNEL);
  827. if (!pins)
  828. return -ENOMEM;
  829. for (i = 0; i < hw->soc->npins; i++) {
  830. pins[i].number = hw->soc->pins[i].number;
  831. pins[i].name = hw->soc->pins[i].name;
  832. }
  833. /* Setup pins descriptions per SoC types */
  834. mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
  835. mtk_desc.npins = hw->soc->npins;
  836. mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
  837. mtk_desc.custom_params = mtk_custom_bindings;
  838. #ifdef CONFIG_DEBUG_FS
  839. mtk_desc.custom_conf_items = mtk_conf_items;
  840. #endif
  841. err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
  842. &hw->pctrl);
  843. if (err)
  844. return err;
  845. err = pinctrl_enable(hw->pctrl);
  846. if (err)
  847. return err;
  848. err = mtk_build_eint(hw, pdev);
  849. if (err)
  850. dev_warn(&pdev->dev,
  851. "Failed to add EINT, but pinctrl still can work\n");
  852. /* Build gpiochip should be after pinctrl_enable is done */
  853. err = mtk_build_gpiochip(hw, pdev->dev.of_node);
  854. if (err) {
  855. dev_err(&pdev->dev, "Failed to add gpio_chip\n");
  856. return err;
  857. }
  858. platform_set_drvdata(pdev, hw);
  859. return 0;
  860. }