Kconfig 3.7 KB

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  1. #
  2. # Broadcom pinctrl drivers
  3. #
  4. config PINCTRL_BCM281XX
  5. bool "Broadcom BCM281xx pinctrl driver"
  6. depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
  7. select PINMUX
  8. select PINCONF
  9. select GENERIC_PINCONF
  10. select REGMAP_MMIO
  11. default ARCH_BCM_MOBILE
  12. help
  13. Say Y here to support Broadcom BCM281xx pinctrl driver, which is used
  14. for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
  15. BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
  16. framework. GPIO is provided by a separate GPIO driver.
  17. config PINCTRL_BCM2835
  18. bool
  19. select PINMUX
  20. select PINCONF
  21. select GPIOLIB_IRQCHIP
  22. config PINCTRL_IPROC_GPIO
  23. bool "Broadcom iProc GPIO (with PINCONF) driver"
  24. depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
  25. select GPIOLIB_IRQCHIP
  26. select PINCONF
  27. select GENERIC_PINCONF
  28. default ARCH_BCM_IPROC
  29. help
  30. Say yes here to enable the Broadcom iProc GPIO driver.
  31. The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use
  32. same GPIO Controller IP hence this driver could be used for all.
  33. The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
  34. GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
  35. the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are
  36. supported by this driver.
  37. The Broadcom NSP has two GPIO controllers including the ChipcommonA
  38. GPIO, the ChipcommonB GPIO. Later controller is supported by this
  39. driver.
  40. The Broadcom NS2 has two GPIO controller including the CRMU GPIO,
  41. the ChipcommonG GPIO. Both controllers are supported by this driver.
  42. The Broadcom Stingray GPIO controllers are supported by this driver.
  43. All above SoCs GPIO controllers support basic PINCONF functions such
  44. as bias pull up, pull down, and drive strength configurations, when
  45. these pins are muxed to GPIO.
  46. It provides the framework where pins from the individual GPIO can be
  47. individually muxed to GPIO function, through interaction with the
  48. SoCs IOMUX controller. This features could be used only on SoCs which
  49. support individual pin muxing.
  50. config PINCTRL_CYGNUS_MUX
  51. bool "Broadcom Cygnus IOMUX driver"
  52. depends on (ARCH_BCM_CYGNUS || COMPILE_TEST)
  53. depends on OF
  54. select PINMUX
  55. select GENERIC_PINCONF
  56. default ARCH_BCM_CYGNUS
  57. help
  58. Say yes here to enable the Broadcom Cygnus IOMUX driver.
  59. The Broadcom Cygnus IOMUX driver supports group based IOMUX
  60. configuration, with the exception that certain individual pins
  61. can be overridden to GPIO function
  62. config PINCTRL_NSP_GPIO
  63. bool "Broadcom NSP GPIO (with PINCONF) driver"
  64. depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
  65. select GPIOLIB_IRQCHIP
  66. select PINCONF
  67. select GENERIC_PINCONF
  68. default ARCH_BCM_NSP
  69. help
  70. Say yes here to enable the Broadcom NSP GPIO driver.
  71. The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is
  72. supported by this driver.
  73. The ChipcommonA GPIO controller support basic PINCONF functions such
  74. as bias pull up, pull down, and drive strength configurations, when
  75. these pins are muxed to GPIO.
  76. config PINCTRL_NS2_MUX
  77. bool "Broadcom Northstar2 pinmux driver"
  78. depends on OF
  79. depends on ARCH_BCM_IPROC || COMPILE_TEST
  80. select PINMUX
  81. select GENERIC_PINCONF
  82. default ARM64 && ARCH_BCM_IPROC
  83. help
  84. Say yes here to enable the Broadcom NS2 MUX driver.
  85. The Broadcom Northstar2 IOMUX driver supports group based IOMUX
  86. configuration.
  87. config PINCTRL_NSP_MUX
  88. bool "Broadcom NSP IOMUX driver"
  89. depends on (ARCH_BCM_NSP || COMPILE_TEST)
  90. depends on OF
  91. select PINMUX
  92. select GENERIC_PINCONF
  93. default ARCH_BCM_NSP
  94. help
  95. Say yes here to enable the Broadcom NSP SOC IOMUX driver.
  96. The Broadcom Northstar Plus IOMUX driver supports pin based IOMUX
  97. configuration, with certain individual pins can be overridden
  98. to GPIO function.