p73.c 22 KB

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  1. /*
  2. * Copyright (C) 2012-2014 NXP Semiconductors
  3. * Copyright (C) 2021 XiaoMi, Inc.
  4. *
  5. * Licensed under the Apache License, Version 2.0 (the "License");
  6. * you may not use this file except in compliance with the License.
  7. * You may obtain a copy of the License at
  8. *
  9. * http://www.apache.org/licenses/LICENSE-2.0
  10. *
  11. * Unless required by applicable law or agreed to in writing, software
  12. * distributed under the License is distributed on an "AS IS" BASIS,
  13. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  14. * See the License for the specific language governing permissions and
  15. * limitations under the License.
  16. */
  17. /**
  18. * \addtogroup spi_driver
  19. *
  20. * @{ */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/fs.h>
  24. #include <linux/slab.h>
  25. #include <linux/init.h>
  26. #include <linux/list.h>
  27. #include <linux/irq.h>
  28. #include <linux/jiffies.h>
  29. #include <linux/uaccess.h>
  30. #include <linux/delay.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/io.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/gpio.h>
  35. #include <linux/of_gpio.h>
  36. #include <linux/miscdevice.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/spi/spi.h>
  39. #include <linux/sched.h>
  40. #include <linux/poll.h>
  41. #include <linux/regulator/consumer.h>
  42. #include <linux/platform_data/spi-mt65xx.h>
  43. #include "p73.h"
  44. #include "../nfc/pn553.h"
  45. extern long pn544_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
  46. extern long p61_cold_reset(void);
  47. extern void mt_spi_enable_master_clk(struct spi_device *spidev);
  48. extern void mt_spi_disable_master_clk(struct spi_device *spidev);
  49. #define DRAGON_P61 1
  50. /* Device driver's configuration macro */
  51. /* Macro to configure poll/interrupt based req*/
  52. #undef P61_IRQ_ENABLE
  53. //#define P61_IRQ_ENABLE
  54. /* Macro to configure Hard/Soft reset to P61 */
  55. //#define P61_HARD_RESET
  56. #undef P61_HARD_RESET
  57. //#define P61_IRQ 33 /* this is the same used in omap3beagle.c */
  58. //#define P61_RST 138
  59. /* Macro to define SPI clock frequency */
  60. //#define P61_SPI_CLOCK_7Mzh
  61. //#undef P61_SPI_CLOCK_20Mzh
  62. #undef P61_SPI_CLOCK_13_3_Mzh
  63. #undef P61_SPI_CLOCK_8Mzh
  64. //#define P61_SPI_CLOCK_7Mzh
  65. #define P61_SPI_CLOCK_20Mzh
  66. #ifdef P61_SPI_CLOCK_13_3_Mzh
  67. //#define P61_SPI_CLOCK 13300000L;Further debug needed
  68. #define P61_SPI_CLOCK 19000000L;
  69. #else
  70. #ifdef P61_SPI_CLOCK_7Mzh
  71. #define P61_SPI_CLOCK 7000000L;
  72. #else
  73. #ifdef P61_SPI_CLOCK_8Mzh
  74. #define P61_SPI_CLOCK 8000000L;
  75. #else
  76. #ifdef P61_SPI_CLOCK_20Mzh
  77. #define P61_SPI_CLOCK 20000000L;
  78. #else
  79. #define P61_SPI_CLOCK 4000000L;
  80. #endif
  81. #endif
  82. #endif
  83. #endif
  84. /* size of maximum read/write buffer supported by driver */
  85. #define MAX_BUFFER_SIZE 780U
  86. /* Different driver debug lever */
  87. enum P61_DEBUG_LEVEL {
  88. P61_DEBUG_OFF,
  89. P61_FULL_DEBUG
  90. };
  91. #define READ_THROUGH_PUT 0x01
  92. #define WRITE_THROUGH_PUT 0x02
  93. #define MXAX_THROUGH_PUT_TIME 999000L
  94. /* Variable to store current debug level request by ioctl */
  95. static unsigned char debug_level;
  96. #define P61_DBG_MSG(msg...) printk(KERN_ERR "[NXP-P61] : " msg);
  97. #define P61_ERR_MSG(msg...) printk(KERN_ERR "[NFC-P61] : " msg);
  98. /* Device specific macro and structure */
  99. struct p61_dev {
  100. wait_queue_head_t read_wq; /* wait queue for read interrupt */
  101. struct mutex read_mutex; /* read mutex */
  102. struct mutex write_mutex; /* write mutex */
  103. struct spi_device *spi; /* spi device structure */
  104. struct miscdevice p61_device; /* char device as misc driver */
  105. //unsigned int rst_gpio; /* SW Reset gpio */
  106. //unsigned int irq_gpio; /* P61 will interrupt DH for any ntf */
  107. //bool irq_enabled; /* flag to indicate irq is used */
  108. unsigned char enable_poll_mode; /* enable the poll mode */
  109. //spinlock_t irq_enabled_lock; /*spin lock for read irq */
  110. };
  111. const struct mtk_chip_config nfc_ctrdata = {
  112. .rx_mlsb = 1,
  113. .tx_mlsb = 1,
  114. .cs_pol = 0,
  115. .deassert_mode = 1,
  116. };
  117. /* T==1 protocol specific global data */
  118. const unsigned char SOF = 0xA5u;
  119. struct p61_through_put {
  120. struct timeval rstart_tv;
  121. struct timeval rstop_tv;
  122. struct timeval wstart_tv;
  123. struct timeval wstop_tv;
  124. unsigned long total_through_put_wbytes;
  125. unsigned long total_through_put_rbytes;
  126. unsigned long total_through_put_rtime;
  127. unsigned long total_through_put_wtime;
  128. bool enable_through_put_measure;
  129. };
  130. static struct p61_through_put p61_through_put_t;
  131. static void p61_start_throughput_measurement(unsigned int type);
  132. static void p61_stop_throughput_measurement(unsigned int type, int no_of_bytes);
  133. static void nfc_spi_clk_enable(struct p61_dev *nfc_dev, u8 bonoff)
  134. {
  135. static int count;
  136. pr_err("%s line:%d try to control spi clk\n", __func__, __LINE__);
  137. if (bonoff && (count == 0)) {
  138. pr_err("%s line:%d enable spi clk\n", __func__, __LINE__);
  139. mt_spi_enable_master_clk(nfc_dev->spi);
  140. count = 1;
  141. } else if ((count > 0) && (bonoff == 0)) {
  142. pr_err("%s line:%d disable spi clk\n", __func__, __LINE__);
  143. mt_spi_disable_master_clk(nfc_dev->spi);
  144. count = 0;
  145. }
  146. }
  147. static void p61_start_throughput_measurement(unsigned int type)
  148. {
  149. if (type == READ_THROUGH_PUT) {
  150. memset(&p61_through_put_t.rstart_tv, 0x00,
  151. sizeof(struct timeval));
  152. do_gettimeofday(&p61_through_put_t.rstart_tv);
  153. } else if (type == WRITE_THROUGH_PUT) {
  154. memset(&p61_through_put_t.wstart_tv, 0x00,
  155. sizeof(struct timeval));
  156. do_gettimeofday(&p61_through_put_t.wstart_tv);
  157. } else {
  158. P61_DBG_MSG(KERN_ALERT
  159. " p61_start_throughput_measurement: wrong type = %d",
  160. type);
  161. }
  162. }
  163. static void p61_stop_throughput_measurement(unsigned int type, int no_of_bytes)
  164. {
  165. if (type == READ_THROUGH_PUT) {
  166. memset(&p61_through_put_t.rstop_tv, 0x00,
  167. sizeof(struct timeval));
  168. do_gettimeofday(&p61_through_put_t.rstop_tv);
  169. p61_through_put_t.total_through_put_rbytes += no_of_bytes;
  170. p61_through_put_t.total_through_put_rtime +=
  171. (p61_through_put_t.rstop_tv.tv_usec -
  172. p61_through_put_t.rstart_tv.tv_usec) +
  173. ((p61_through_put_t.rstop_tv.tv_sec -
  174. p61_through_put_t.rstart_tv.tv_sec) * 1000000);
  175. if (p61_through_put_t.total_through_put_rtime >=
  176. MXAX_THROUGH_PUT_TIME) {
  177. printk(KERN_ALERT
  178. " **************** Read Throughput: **************");
  179. printk(KERN_ALERT " No of Read Bytes = %ld",
  180. p61_through_put_t.total_through_put_rbytes);
  181. printk(KERN_ALERT " Total Read Time (uSec) = %ld",
  182. p61_through_put_t.total_through_put_rtime);
  183. p61_through_put_t.total_through_put_rbytes = 0;
  184. p61_through_put_t.total_through_put_rtime = 0;
  185. printk(KERN_ALERT
  186. " **************** Read Throughput: **************");
  187. }
  188. printk(KERN_ALERT " No of Read Bytes = %ld",
  189. p61_through_put_t.total_through_put_rbytes);
  190. printk(KERN_ALERT " Total Read Time (uSec) = %ld",
  191. p61_through_put_t.total_through_put_rtime);
  192. } else if (type == WRITE_THROUGH_PUT) {
  193. memset(&p61_through_put_t.wstop_tv, 0x00,
  194. sizeof(struct timeval));
  195. do_gettimeofday(&p61_through_put_t.wstop_tv);
  196. p61_through_put_t.total_through_put_wbytes += no_of_bytes;
  197. p61_through_put_t.total_through_put_wtime +=
  198. (p61_through_put_t.wstop_tv.tv_usec -
  199. p61_through_put_t.wstart_tv.tv_usec) +
  200. ((p61_through_put_t.wstop_tv.tv_sec -
  201. p61_through_put_t.wstart_tv.tv_sec) * 1000000);
  202. if (p61_through_put_t.total_through_put_wtime >=
  203. MXAX_THROUGH_PUT_TIME) {
  204. printk(KERN_ALERT
  205. " **************** Write Throughput: **************");
  206. printk(KERN_ALERT " No of Write Bytes = %ld",
  207. p61_through_put_t.total_through_put_wbytes);
  208. printk(KERN_ALERT " Total Write Time (uSec) = %ld",
  209. p61_through_put_t.total_through_put_wtime);
  210. p61_through_put_t.total_through_put_wbytes = 0;
  211. p61_through_put_t.total_through_put_wtime = 0;
  212. printk(KERN_ALERT
  213. " **************** WRITE Throughput: **************");
  214. }
  215. printk(KERN_ALERT " No of Write Bytes = %ld",
  216. p61_through_put_t.total_through_put_wbytes);
  217. printk(KERN_ALERT " Total Write Time (uSec) = %ld",
  218. p61_through_put_t.total_through_put_wtime);
  219. } else {
  220. printk(KERN_ALERT
  221. " p61_stop_throughput_measurement: wrong type = %d",
  222. type);
  223. }
  224. }
  225. /**
  226. * \ingroup spi_driver
  227. * \brief Called from SPI LibEse to initilaize the P61 device
  228. *
  229. * \param[in] struct inode *
  230. * \param[in] struct file *
  231. *
  232. * \retval 0 if ok.
  233. *
  234. */
  235. static int p61_dev_open(struct inode *inode, struct file *filp)
  236. {
  237. struct p61_dev
  238. *p61_dev = container_of(filp->private_data,
  239. struct p61_dev,
  240. p61_device);
  241. filp->private_data = p61_dev;
  242. P61_DBG_MSG("%s : Major No: %d, Minor No: %d\n", __func__,
  243. imajor(inode), iminor(inode));
  244. return 0;
  245. }
  246. /**
  247. * \ingroup spi_driver
  248. * \brief To configure the P61_SET_PWR/P61_SET_DBG/P61_SET_POLL
  249. * \n P61_SET_PWR - hard reset (arg=2), soft reset (arg=1)
  250. * \n P61_SET_DBG - Enable/Disable (based on arg value) the driver logs
  251. * \n P61_SET_POLL - Configure the driver in poll (arg = 1), interrupt (arg = 0) based read operation
  252. * \param[in] struct file *
  253. * \param[in] unsigned int
  254. * \param[in] unsigned long
  255. *
  256. * \retval 0 if ok.
  257. *
  258. */
  259. static long p61_dev_ioctl(struct file *filp, unsigned int cmd,
  260. unsigned long arg)
  261. {
  262. int ret = 0;
  263. struct p61_dev *p61_dev = NULL;
  264. unsigned char buf[100];
  265. P61_DBG_MSG(KERN_ALERT "p61_dev_ioctl-Enter %u arg = %ld\n", cmd, arg);
  266. p61_dev = filp->private_data;
  267. switch (cmd) {
  268. case P61_SET_PWR:
  269. if (arg == 2) {
  270. } else if (arg == 1) {
  271. P61_DBG_MSG(KERN_ALERT " Soft Reset");
  272. //gpio_set_value(p61_dev->rst_gpio, 1);
  273. //msleep(20);
  274. //gpio_set_value(p61_dev->rst_gpio, 0);
  275. msleep(50);
  276. ret = spi_read(p61_dev->spi, (void *)buf, sizeof(buf));
  277. msleep(50);
  278. //gpio_set_value(p61_dev->rst_gpio, 1);
  279. //msleep(20);
  280. }
  281. break;
  282. case P61_SET_DBG:
  283. debug_level = (unsigned char)arg;
  284. P61_DBG_MSG(KERN_INFO "[NXP-P61] - Debug level %d",
  285. debug_level);
  286. break;
  287. case P61_SET_POLL:
  288. p61_dev->enable_poll_mode = (unsigned char)arg;
  289. if (p61_dev->enable_poll_mode == 0) {
  290. P61_DBG_MSG(KERN_INFO "[NXP-P61] - IRQ Mode is set \n");
  291. } else {
  292. P61_DBG_MSG(KERN_INFO
  293. "[NXP-P61] - Poll Mode is set \n");
  294. p61_dev->enable_poll_mode = 1;
  295. }
  296. break;
  297. case P61_SET_SPM_PWR:
  298. P61_DBG_MSG(" P61_SET_SPM_PWR: enter");
  299. ret = pn544_dev_ioctl(filp, P61_SET_SPI_PWR, arg);
  300. P61_DBG_MSG(" P61_SET_SPM_PWR: exit");
  301. break;
  302. case P61_GET_SPM_STATUS:
  303. P61_DBG_MSG(KERN_ALERT " P61_GET_SPM_STATUS: enter");
  304. ret = pn544_dev_ioctl(filp, P61_GET_PWR_STATUS, arg);
  305. P61_DBG_MSG(KERN_ALERT " P61_GET_SPM_STATUS: exit");
  306. break;
  307. case P61_SET_DWNLD_STATUS:
  308. /*P61_DBG_MSG(KERN_ALERT " P61_SET_DWNLD_STATUS: enter");
  309. ret = pn544_dev_ioctl(filp, PN544_SET_DWNLD_STATUS, arg);
  310. P61_DBG_MSG(KERN_ALERT " P61_SET_DWNLD_STATUS: =%d exit",arg); */
  311. break;
  312. /*
  313. case P61_SET_THROUGHPUT:
  314. p61_through_put_t.enable_through_put_measure = true;
  315. P61_DBG_MSG(KERN_INFO"[NXP-P61] - P61_SET_THROUGHPUT enable %d", p61_through_put_t.enable_through_put_measure);
  316. break;
  317. case P61_GET_ESE_ACCESS:
  318. P61_DBG_MSG(KERN_ALERT " P61_GET_ESE_ACCESS: enter");
  319. ret = pn544_dev_ioctl(filp, P544_GET_ESE_ACCESS, arg);
  320. P61_DBG_MSG(KERN_ALERT " P61_GET_ESE_ACCESS ret: %d exit",ret);
  321. break;
  322. case P61_SET_POWER_SCHEME:
  323. P61_DBG_MSG(KERN_ALERT " P61_SET_POWER_SCHEME: enter");
  324. ret = pn544_dev_ioctl(filp, P544_SET_POWER_SCHEME, arg);
  325. P61_DBG_MSG(KERN_ALERT " P61_SET_POWER_SCHEME ret: %d exit",ret);
  326. break;
  327. case P61_INHIBIT_PWR_CNTRL:
  328. P61_DBG_MSG(KERN_ALERT " P61_INHIBIT_PWR_CNTRL: enter");
  329. ret = pn544_dev_ioctl(filp, P544_SECURE_TIMER_SESSION, arg);
  330. P61_DBG_MSG(KERN_ALERT " P61_INHIBIT_PWR_CNTRL ret: %d exit", ret);
  331. break; */
  332. case ESE_PERFORM_COLD_RESET:
  333. ret = p61_cold_reset();
  334. break;
  335. case ENBLE_SPI_CLK:
  336. P61_DBG_MSG(KERN_ALERT " ENBLE_SPI_CLK: enter");
  337. nfc_spi_clk_enable(p61_dev, 1);
  338. break;
  339. case DISABLE_SPI_CLK:
  340. P61_DBG_MSG(KERN_ALERT " DISABLE_SPI_CLK: enter");
  341. nfc_spi_clk_enable(p61_dev, 0);
  342. break;
  343. default:
  344. P61_DBG_MSG(KERN_ALERT " Error case");
  345. ret = -EINVAL;
  346. }
  347. P61_DBG_MSG(KERN_ALERT "p61_dev_ioctl-exit %u arg = %ld\n", cmd, arg);
  348. return ret;
  349. }
  350. /**
  351. * \ingroup spi_driver
  352. * \brief Write data to P61 on SPI
  353. *
  354. * \param[in] struct file *
  355. * \param[in] const char *
  356. * \param[in] size_t
  357. * \param[in] loff_t *
  358. *
  359. * \retval data size
  360. *
  361. */
  362. static ssize_t p61_dev_write(struct file *filp, const char *buf, size_t count,
  363. loff_t *offset)
  364. {
  365. int ret = -1;
  366. struct p61_dev *p61_dev;
  367. unsigned char tx_buffer[MAX_BUFFER_SIZE];
  368. P61_DBG_MSG(KERN_ALERT "p61_dev_write -Enter count %d\n", count);
  369. p61_dev = filp->private_data;
  370. mutex_lock(&p61_dev->write_mutex);
  371. if (count > MAX_BUFFER_SIZE)
  372. count = MAX_BUFFER_SIZE;
  373. memset(&tx_buffer[0], 0, sizeof(tx_buffer));
  374. if (copy_from_user(&tx_buffer[0], &buf[0], count)) {
  375. P61_ERR_MSG("%s : failed to copy from user space\n", __func__);
  376. mutex_unlock(&p61_dev->write_mutex);
  377. return -EFAULT;
  378. }
  379. if (p61_through_put_t.enable_through_put_measure)
  380. p61_start_throughput_measurement(WRITE_THROUGH_PUT);
  381. /* Write data */
  382. ret = spi_write(p61_dev->spi, &tx_buffer[0], count);
  383. if (ret < 0) {
  384. ret = -EIO;
  385. } else {
  386. ret = count;
  387. if (p61_through_put_t.enable_through_put_measure)
  388. p61_stop_throughput_measurement(WRITE_THROUGH_PUT, ret);
  389. }
  390. mutex_unlock(&p61_dev->write_mutex);
  391. P61_DBG_MSG(KERN_ALERT "p61_dev_write ret %d- Exit \n", ret);
  392. return ret;
  393. }
  394. /**
  395. * \ingroup spi_driver
  396. * \brief Used to read data from P61 in Poll/interrupt mode configured using ioctl call
  397. *
  398. * \param[in] struct file *
  399. * \param[in] char *
  400. * \param[in] size_t
  401. * \param[in] loff_t *
  402. *
  403. * \retval read size
  404. *
  405. */
  406. static ssize_t p61_dev_read(struct file *filp, char *buf, size_t count,
  407. loff_t *offset)
  408. {
  409. int ret = -EIO;
  410. struct p61_dev *p61_dev = filp->private_data;
  411. int i = 0;
  412. unsigned char rx_buffer[MAX_BUFFER_SIZE] = { 0 };
  413. P61_DBG_MSG("p61_dev_read count %d - Enter \n", count);
  414. mutex_lock(&p61_dev->read_mutex);
  415. if (count > MAX_BUFFER_SIZE) {
  416. count = MAX_BUFFER_SIZE;
  417. }
  418. memset(&rx_buffer[0], 0x00, sizeof(rx_buffer));
  419. if (p61_dev->enable_poll_mode) {
  420. P61_DBG_MSG(" %s Poll Mode Enabled \n", __FUNCTION__);
  421. P61_DBG_MSG(KERN_INFO "SPI_READ returned 0x%x", count);
  422. ret = spi_read(p61_dev->spi, (void *)&rx_buffer[0], count);
  423. if (0 > ret) {
  424. P61_ERR_MSG(KERN_ALERT "spi_read failed [SOF] \n");
  425. goto fail;
  426. }
  427. } else {
  428. P61_DBG_MSG(" %s P61_IRQ_ENABLE not Enabled \n", __FUNCTION__);
  429. ret = spi_read(p61_dev->spi, (void *)&rx_buffer[0], count);
  430. if (0 > ret) {
  431. P61_DBG_MSG(KERN_INFO "SPI_READ returned 0x%x", ret);
  432. ret = -EIO;
  433. goto fail;
  434. }
  435. }
  436. if (p61_through_put_t.enable_through_put_measure)
  437. p61_start_throughput_measurement(READ_THROUGH_PUT);
  438. if (p61_through_put_t.enable_through_put_measure)
  439. p61_stop_throughput_measurement(READ_THROUGH_PUT, count);
  440. P61_DBG_MSG(KERN_INFO "total_count = %d", count);
  441. if (copy_to_user(buf, &rx_buffer[0], sizeof(rx_buffer))) {
  442. P61_ERR_MSG("%s : failed to copy to user space\n", __func__);
  443. ret = -EFAULT;
  444. goto fail;
  445. }
  446. P61_DBG_MSG("p61_dev_read ret %d Exit\n", ret);
  447. P61_DBG_MSG("p61_dev_read rx_buffer %d Exit\n", rx_buffer[0]);
  448. for (i = 0; i < count; i++) {
  449. P61_ERR_MSG("p61_dev_read rx_buffer is %d\n ", rx_buffer[i]);
  450. }
  451. mutex_unlock(&p61_dev->read_mutex);
  452. return ret;
  453. fail:
  454. P61_ERR_MSG("Error p61_dev_read ret %d Exit\n", ret);
  455. mutex_unlock(&p61_dev->read_mutex);
  456. return ret;
  457. }
  458. /**
  459. * \ingroup spi_driver
  460. * \brief It will configure the GPIOs required for soft reset, read interrupt & regulated power supply to P61.
  461. *
  462. * \param[in] struct p61_spi_platform_data *
  463. * \param[in] struct p61_dev *
  464. * \param[in] struct spi_device *
  465. *
  466. * \retval 0 if ok.
  467. *
  468. */
  469. static int p61_hw_setup(struct p61_spi_platform_data *platform_data,
  470. struct p61_dev *p61_dev, struct spi_device *spi)
  471. {
  472. int ret = -1;
  473. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  474. /* ret = gpio_request( platform_data->rst_gpio, "p61 reset");
  475. if (ret < 0)
  476. {
  477. P61_ERR_MSG("gpio reset request failed = 0x%x\n", platform_data->rst_gpio);
  478. goto fail_gpio;
  479. } */
  480. /*soft reset gpio is set to default high */
  481. /*ret = gpio_direction_output(platform_data->rst_gpio,1);
  482. if (ret < 0)
  483. {
  484. P61_ERR_MSG("gpio rst request failed gpio = 0x%x\n", platform_data->rst_gpio);
  485. goto fail_gpio;
  486. } */
  487. ret = 0;
  488. P61_DBG_MSG("Exit : %s\n", __FUNCTION__);
  489. return ret;
  490. //fail_gpio:
  491. //gpio_free(platform_data->rst_gpio);
  492. return ret;
  493. }
  494. /**
  495. * \ingroup spi_driver
  496. * \brief Set the P61 device specific context for future use.
  497. *
  498. * \param[in] struct spi_device *
  499. * \param[in] void *
  500. *
  501. * \retval void
  502. *
  503. */
  504. static inline void p61_set_data(struct spi_device *spi, void *data)
  505. {
  506. dev_set_drvdata(&spi->dev, data);
  507. }
  508. /**
  509. * \ingroup spi_driver
  510. * \brief Get the P61 device specific context.
  511. *
  512. * \param[in] const struct spi_device *
  513. *
  514. * \retval Device Parameters
  515. *
  516. */
  517. static inline void *p61_get_data(const struct spi_device *spi)
  518. {
  519. return dev_get_drvdata(&spi->dev);
  520. }
  521. /* possible fops on the p61 device */
  522. static const struct file_operations p61_dev_fops = {
  523. .owner = THIS_MODULE,
  524. .read = p61_dev_read,
  525. .write = p61_dev_write,
  526. .open = p61_dev_open,
  527. .unlocked_ioctl = p61_dev_ioctl,
  528. };
  529. #if DRAGON_P61
  530. static int p61_parse_dt(struct device *dev, struct p61_spi_platform_data *data)
  531. {
  532. int errorno = 0;
  533. pr_info("%s: %d\n", __func__, errorno);
  534. return errorno;
  535. }
  536. #endif
  537. static int p61_probe(struct spi_device *spi)
  538. {
  539. int ret = -1;
  540. struct p61_spi_platform_data *platform_data = NULL;
  541. struct p61_spi_platform_data platform_data1;
  542. struct p61_dev *p61_dev = NULL;
  543. //struct mtk_chip_config *chip_config = spi->controller_data;
  544. P61_DBG_MSG("%s chip select : %d , bus number = %d \n",
  545. __FUNCTION__, spi->chip_select, spi->master->bus_num);
  546. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  547. printk("[nxp]p61_probe");
  548. #if !DRAGON_P61
  549. platform_data = spi->dev.platform_data;
  550. if (platform_data == NULL) {
  551. /* RC : rename the platformdata1 name */
  552. /* TBD: This is only for Panda as we are passing NULL for platform data */
  553. P61_ERR_MSG("%s : p61 probe fail\n", __func__);
  554. //platform_data1.irq_gpio = P61_IRQ;
  555. //platform_data1.rst_gpio = P61_RST;
  556. platform_data = &platform_data1;
  557. P61_ERR_MSG("%s : p61 probe fail1\n", __func__);
  558. //return -ENODEV;
  559. }
  560. #else
  561. ret = p61_parse_dt(&spi->dev, &platform_data1);
  562. if (ret) {
  563. pr_err("%s - Failed to parse DT\n", __func__);
  564. goto err_exit;
  565. }
  566. platform_data = &platform_data1;
  567. #endif
  568. p61_dev = kzalloc(sizeof(*p61_dev), GFP_KERNEL);
  569. if (p61_dev == NULL) {
  570. P61_ERR_MSG("failed to allocate memory for module data\n");
  571. ret = -ENOMEM;
  572. goto err_exit;
  573. }
  574. ret = p61_hw_setup(platform_data, p61_dev, spi);
  575. if (ret < 0) {
  576. P61_ERR_MSG("Failed to p61_enable_P61_IRQ_ENABLE\n");
  577. goto err_exit0;
  578. }
  579. // set clock deassert mode for nxp chipset
  580. /*if (chip_config == NULL) {
  581. P61_ERR_MSG("Replaced chip_info!\n");
  582. } else {
  583. chip_config->deassert_mode = 1;
  584. P61_ERR_MSG("Added into chip_info!\n");
  585. }*/
  586. spi->controller_data = (void *)&nfc_ctrdata;
  587. spi->bits_per_word = 8;
  588. spi->mode = SPI_MODE_0;
  589. spi->max_speed_hz = P61_SPI_CLOCK;
  590. //spi->chip_select = SPI_NO_CS;
  591. ret = spi_setup(spi);
  592. if (ret < 0) {
  593. P61_ERR_MSG("failed to do spi_setup()\n");
  594. goto err_exit0;
  595. }
  596. p61_dev->spi = spi;
  597. p61_dev->p61_device.minor = MISC_DYNAMIC_MINOR;
  598. p61_dev->p61_device.name = "p73";
  599. p61_dev->p61_device.fops = &p61_dev_fops;
  600. p61_dev->p61_device.parent = &spi->dev;
  601. //p61_dev->irq_gpio = platform_data->irq_gpio;
  602. //p61_dev->rst_gpio = platform_data->rst_gpio;
  603. dev_set_drvdata(&spi->dev, p61_dev);
  604. /* init mutex and queues */
  605. init_waitqueue_head(&p61_dev->read_wq);
  606. mutex_init(&p61_dev->read_mutex);
  607. mutex_init(&p61_dev->write_mutex);
  608. ret = misc_register(&p61_dev->p61_device);
  609. if (ret < 0) {
  610. P61_ERR_MSG("misc_register failed! %d\n", ret);
  611. goto err_exit0;
  612. }
  613. p61_dev->enable_poll_mode = 1; /* Default poll read mode */
  614. pr_err("%s %d now enable spi clk API", __func__, __LINE__);
  615. nfc_spi_clk_enable(p61_dev, 1);
  616. P61_DBG_MSG("Exit : %s\n", __FUNCTION__);
  617. pr_err("%s %d now disable spi clk API", __func__, __LINE__);
  618. nfc_spi_clk_enable(p61_dev, 0);
  619. return ret;
  620. /*err_exit1:
  621. misc_deregister(&p61_dev->p61_device); */
  622. err_exit0:
  623. mutex_destroy(&p61_dev->read_mutex);
  624. mutex_destroy(&p61_dev->write_mutex);
  625. if (p61_dev != NULL)
  626. kfree(p61_dev);
  627. err_exit:
  628. P61_DBG_MSG("go to error Entry : %s\n", __FUNCTION__);
  629. return ret;
  630. }
  631. static int p61_suspend(struct device *dev, pm_message_t state)
  632. {
  633. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  634. return 0;
  635. }
  636. static int p61_resume(struct device *dev)
  637. {
  638. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  639. return 0;
  640. }
  641. static void p61_shutdown(struct spi_device *spi)
  642. {
  643. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  644. }
  645. /**
  646. * \ingroup spi_driver
  647. * \brief Will get called when the device is removed to release the resources.
  648. *
  649. * \param[in] struct spi_device
  650. *
  651. * \retval 0 if ok.
  652. *
  653. */
  654. static int p61_remove(struct spi_device *spi)
  655. {
  656. struct p61_dev *p61_dev = p61_get_data(spi);
  657. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  658. //gpio_free(p61_dev->rst_gpio);
  659. mutex_destroy(&p61_dev->read_mutex);
  660. misc_deregister(&p61_dev->p61_device);
  661. if (p61_dev != NULL)
  662. kfree(p61_dev);
  663. P61_DBG_MSG("Exit : %s\n", __FUNCTION__);
  664. return 0;
  665. }
  666. #if DRAGON_P61
  667. static struct of_device_id p61_dt_match[] = {
  668. {
  669. .compatible = "nxp,p61",
  670. },
  671. {}
  672. };
  673. #endif
  674. static const struct spi_device_id p61_id[] = {
  675. {"p61", 0},
  676. {}
  677. };
  678. MODULE_DEVICE_TABLE(spi, p61_id);
  679. static struct spi_driver p61_driver = {
  680. .driver = {
  681. .name = "p61",
  682. .bus = &spi_bus_type,
  683. .owner = THIS_MODULE,
  684. .suspend = p61_suspend,
  685. .resume = p61_resume,
  686. #if DRAGON_P61
  687. .of_match_table = p61_dt_match,
  688. #endif
  689. },
  690. .id_table = p61_id,
  691. .probe = p61_probe,
  692. .remove = p61_remove,
  693. .shutdown = p61_shutdown,
  694. };
  695. /**
  696. * \ingroup spi_driver
  697. * \brief Module init interface
  698. *
  699. * \param[in] void
  700. *
  701. * \retval handle
  702. *
  703. */
  704. static int __init p61_dev_init(void)
  705. {
  706. int32_t ret = 0;
  707. debug_level = P61_FULL_DEBUG;
  708. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  709. printk("[nxp]p61_dev_init");
  710. //return spi_register_driver(&p61_driver);
  711. //---add spi driver---
  712. ret = spi_register_driver(&p61_driver);
  713. if (ret) {
  714. P61_DBG_MSG("nxp failed to add spi driver");
  715. goto err_driver;
  716. }
  717. P61_DBG_MSG("finished\n");
  718. err_driver:
  719. P61_DBG_MSG("Exit : %s\n", __FUNCTION__);
  720. return ret;
  721. }
  722. module_init(p61_dev_init);
  723. /**
  724. * \ingroup spi_driver
  725. * \brief Module exit interface
  726. *
  727. * \param[in] void
  728. *
  729. * \retval void
  730. *
  731. */
  732. static void __exit p61_dev_exit(void)
  733. {
  734. P61_DBG_MSG("Entry : %s\n", __FUNCTION__);
  735. spi_unregister_driver(&p61_driver);
  736. P61_DBG_MSG("Exit : %s\n", __FUNCTION__);
  737. }
  738. module_exit(p61_dev_exit);
  739. MODULE_AUTHOR("BHUPENDRA PAWAR");
  740. MODULE_DESCRIPTION("NXP P61 SPI driver");
  741. MODULE_LICENSE("GPL");
  742. /** @} */