ichxrom.c 9.7 KB

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  1. /*
  2. * ichxrom.c
  3. *
  4. * Normal mappings of chips in physical memory
  5. */
  6. #include <linux/module.h>
  7. #include <linux/types.h>
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/slab.h>
  11. #include <asm/io.h>
  12. #include <linux/mtd/mtd.h>
  13. #include <linux/mtd/map.h>
  14. #include <linux/mtd/cfi.h>
  15. #include <linux/mtd/flashchip.h>
  16. #include <linux/pci.h>
  17. #include <linux/pci_ids.h>
  18. #include <linux/list.h>
  19. #define xstr(s) str(s)
  20. #define str(s) #s
  21. #define MOD_NAME xstr(KBUILD_BASENAME)
  22. #define ADDRESS_NAME_LEN 18
  23. #define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
  24. #define BIOS_CNTL 0x4e
  25. #define FWH_DEC_EN1 0xE3
  26. #define FWH_DEC_EN2 0xF0
  27. #define FWH_SEL1 0xE8
  28. #define FWH_SEL2 0xEE
  29. struct ichxrom_window {
  30. void __iomem* virt;
  31. unsigned long phys;
  32. unsigned long size;
  33. struct list_head maps;
  34. struct resource rsrc;
  35. struct pci_dev *pdev;
  36. };
  37. struct ichxrom_map_info {
  38. struct list_head list;
  39. struct map_info map;
  40. struct mtd_info *mtd;
  41. struct resource rsrc;
  42. char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
  43. };
  44. static struct ichxrom_window ichxrom_window = {
  45. .maps = LIST_HEAD_INIT(ichxrom_window.maps),
  46. };
  47. static void ichxrom_cleanup(struct ichxrom_window *window)
  48. {
  49. struct ichxrom_map_info *map, *scratch;
  50. u16 word;
  51. int ret;
  52. /* Disable writes through the rom window */
  53. ret = pci_read_config_word(window->pdev, BIOS_CNTL, &word);
  54. if (!ret)
  55. pci_write_config_word(window->pdev, BIOS_CNTL, word & ~1);
  56. pci_dev_put(window->pdev);
  57. /* Free all of the mtd devices */
  58. list_for_each_entry_safe(map, scratch, &window->maps, list) {
  59. if (map->rsrc.parent)
  60. release_resource(&map->rsrc);
  61. mtd_device_unregister(map->mtd);
  62. map_destroy(map->mtd);
  63. list_del(&map->list);
  64. kfree(map);
  65. }
  66. if (window->rsrc.parent)
  67. release_resource(&window->rsrc);
  68. if (window->virt) {
  69. iounmap(window->virt);
  70. window->virt = NULL;
  71. window->phys = 0;
  72. window->size = 0;
  73. window->pdev = NULL;
  74. }
  75. }
  76. static int __init ichxrom_init_one(struct pci_dev *pdev,
  77. const struct pci_device_id *ent)
  78. {
  79. static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
  80. struct ichxrom_window *window = &ichxrom_window;
  81. struct ichxrom_map_info *map = NULL;
  82. unsigned long map_top;
  83. u8 byte;
  84. u16 word;
  85. /* For now I just handle the ichx and I assume there
  86. * are not a lot of resources up at the top of the address
  87. * space. It is possible to handle other devices in the
  88. * top 16MB but it is very painful. Also since
  89. * you can only really attach a FWH to an ICHX there
  90. * a number of simplifications you can make.
  91. *
  92. * Also you can page firmware hubs if an 8MB window isn't enough
  93. * but don't currently handle that case either.
  94. */
  95. window->pdev = pdev;
  96. /* Find a region continuous to the end of the ROM window */
  97. window->phys = 0;
  98. pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
  99. if (byte == 0xff) {
  100. window->phys = 0xffc00000;
  101. pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
  102. if ((byte & 0x0f) == 0x0f) {
  103. window->phys = 0xff400000;
  104. }
  105. else if ((byte & 0x0e) == 0x0e) {
  106. window->phys = 0xff500000;
  107. }
  108. else if ((byte & 0x0c) == 0x0c) {
  109. window->phys = 0xff600000;
  110. }
  111. else if ((byte & 0x08) == 0x08) {
  112. window->phys = 0xff700000;
  113. }
  114. }
  115. else if ((byte & 0xfe) == 0xfe) {
  116. window->phys = 0xffc80000;
  117. }
  118. else if ((byte & 0xfc) == 0xfc) {
  119. window->phys = 0xffd00000;
  120. }
  121. else if ((byte & 0xf8) == 0xf8) {
  122. window->phys = 0xffd80000;
  123. }
  124. else if ((byte & 0xf0) == 0xf0) {
  125. window->phys = 0xffe00000;
  126. }
  127. else if ((byte & 0xe0) == 0xe0) {
  128. window->phys = 0xffe80000;
  129. }
  130. else if ((byte & 0xc0) == 0xc0) {
  131. window->phys = 0xfff00000;
  132. }
  133. else if ((byte & 0x80) == 0x80) {
  134. window->phys = 0xfff80000;
  135. }
  136. if (window->phys == 0) {
  137. printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
  138. goto out;
  139. }
  140. window->phys -= 0x400000UL;
  141. window->size = (0xffffffffUL - window->phys) + 1UL;
  142. /* Enable writes through the rom window */
  143. pci_read_config_word(pdev, BIOS_CNTL, &word);
  144. if (!(word & 1) && (word & (1<<1))) {
  145. /* The BIOS will generate an error if I enable
  146. * this device, so don't even try.
  147. */
  148. printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
  149. goto out;
  150. }
  151. pci_write_config_word(pdev, BIOS_CNTL, word | 1);
  152. /*
  153. * Try to reserve the window mem region. If this fails then
  154. * it is likely due to the window being "reserved" by the BIOS.
  155. */
  156. window->rsrc.name = MOD_NAME;
  157. window->rsrc.start = window->phys;
  158. window->rsrc.end = window->phys + window->size - 1;
  159. window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  160. if (request_resource(&iomem_resource, &window->rsrc)) {
  161. window->rsrc.parent = NULL;
  162. printk(KERN_DEBUG MOD_NAME ": "
  163. "%s(): Unable to register resource %pR - kernel bug?\n",
  164. __func__, &window->rsrc);
  165. }
  166. /* Map the firmware hub into my address space. */
  167. window->virt = ioremap_nocache(window->phys, window->size);
  168. if (!window->virt) {
  169. printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
  170. window->phys, window->size);
  171. goto out;
  172. }
  173. /* Get the first address to look for an rom chip at */
  174. map_top = window->phys;
  175. if ((window->phys & 0x3fffff) != 0) {
  176. map_top = window->phys + 0x400000;
  177. }
  178. #if 1
  179. /* The probe sequence run over the firmware hub lock
  180. * registers sets them to 0x7 (no access).
  181. * Probe at most the last 4M of the address space.
  182. */
  183. if (map_top < 0xffc00000) {
  184. map_top = 0xffc00000;
  185. }
  186. #endif
  187. /* Loop through and look for rom chips */
  188. while((map_top - 1) < 0xffffffffUL) {
  189. struct cfi_private *cfi;
  190. unsigned long offset;
  191. int i;
  192. if (!map) {
  193. map = kmalloc(sizeof(*map), GFP_KERNEL);
  194. }
  195. if (!map) {
  196. printk(KERN_ERR MOD_NAME ": kmalloc failed");
  197. goto out;
  198. }
  199. memset(map, 0, sizeof(*map));
  200. INIT_LIST_HEAD(&map->list);
  201. map->map.name = map->map_name;
  202. map->map.phys = map_top;
  203. offset = map_top - window->phys;
  204. map->map.virt = (void __iomem *)
  205. (((unsigned long)(window->virt)) + offset);
  206. map->map.size = 0xffffffffUL - map_top + 1UL;
  207. /* Set the name of the map to the address I am trying */
  208. sprintf(map->map_name, "%s @%08Lx",
  209. MOD_NAME, (unsigned long long)map->map.phys);
  210. /* Firmware hubs only use vpp when being programmed
  211. * in a factory setting. So in-place programming
  212. * needs to use a different method.
  213. */
  214. for(map->map.bankwidth = 32; map->map.bankwidth;
  215. map->map.bankwidth >>= 1)
  216. {
  217. char **probe_type;
  218. /* Skip bankwidths that are not supported */
  219. if (!map_bankwidth_supported(map->map.bankwidth))
  220. continue;
  221. /* Setup the map methods */
  222. simple_map_init(&map->map);
  223. /* Try all of the probe methods */
  224. probe_type = rom_probe_types;
  225. for(; *probe_type; probe_type++) {
  226. map->mtd = do_map_probe(*probe_type, &map->map);
  227. if (map->mtd)
  228. goto found;
  229. }
  230. }
  231. map_top += ROM_PROBE_STEP_SIZE;
  232. continue;
  233. found:
  234. /* Trim the size if we are larger than the map */
  235. if (map->mtd->size > map->map.size) {
  236. printk(KERN_WARNING MOD_NAME
  237. " rom(%llu) larger than window(%lu). fixing...\n",
  238. (unsigned long long)map->mtd->size, map->map.size);
  239. map->mtd->size = map->map.size;
  240. }
  241. if (window->rsrc.parent) {
  242. /*
  243. * Registering the MTD device in iomem may not be possible
  244. * if there is a BIOS "reserved" and BUSY range. If this
  245. * fails then continue anyway.
  246. */
  247. map->rsrc.name = map->map_name;
  248. map->rsrc.start = map->map.phys;
  249. map->rsrc.end = map->map.phys + map->mtd->size - 1;
  250. map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  251. if (request_resource(&window->rsrc, &map->rsrc)) {
  252. printk(KERN_ERR MOD_NAME
  253. ": cannot reserve MTD resource\n");
  254. map->rsrc.parent = NULL;
  255. }
  256. }
  257. /* Make the whole region visible in the map */
  258. map->map.virt = window->virt;
  259. map->map.phys = window->phys;
  260. cfi = map->map.fldrv_priv;
  261. for(i = 0; i < cfi->numchips; i++) {
  262. cfi->chips[i].start += offset;
  263. }
  264. /* Now that the mtd devices is complete claim and export it */
  265. map->mtd->owner = THIS_MODULE;
  266. if (mtd_device_register(map->mtd, NULL, 0)) {
  267. map_destroy(map->mtd);
  268. map->mtd = NULL;
  269. goto out;
  270. }
  271. /* Calculate the new value of map_top */
  272. map_top += map->mtd->size;
  273. /* File away the map structure */
  274. list_add(&map->list, &window->maps);
  275. map = NULL;
  276. }
  277. out:
  278. /* Free any left over map structures */
  279. kfree(map);
  280. /* See if I have any map structures */
  281. if (list_empty(&window->maps)) {
  282. ichxrom_cleanup(window);
  283. return -ENODEV;
  284. }
  285. return 0;
  286. }
  287. static void ichxrom_remove_one(struct pci_dev *pdev)
  288. {
  289. struct ichxrom_window *window = &ichxrom_window;
  290. ichxrom_cleanup(window);
  291. }
  292. static const struct pci_device_id ichxrom_pci_tbl[] = {
  293. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
  294. PCI_ANY_ID, PCI_ANY_ID, },
  295. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
  296. PCI_ANY_ID, PCI_ANY_ID, },
  297. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
  298. PCI_ANY_ID, PCI_ANY_ID, },
  299. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
  300. PCI_ANY_ID, PCI_ANY_ID, },
  301. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
  302. PCI_ANY_ID, PCI_ANY_ID, },
  303. { 0, },
  304. };
  305. #if 0
  306. MODULE_DEVICE_TABLE(pci, ichxrom_pci_tbl);
  307. static struct pci_driver ichxrom_driver = {
  308. .name = MOD_NAME,
  309. .id_table = ichxrom_pci_tbl,
  310. .probe = ichxrom_init_one,
  311. .remove = ichxrom_remove_one,
  312. };
  313. #endif
  314. static int __init init_ichxrom(void)
  315. {
  316. struct pci_dev *pdev;
  317. const struct pci_device_id *id;
  318. pdev = NULL;
  319. for (id = ichxrom_pci_tbl; id->vendor; id++) {
  320. pdev = pci_get_device(id->vendor, id->device, NULL);
  321. if (pdev) {
  322. break;
  323. }
  324. }
  325. if (pdev) {
  326. return ichxrom_init_one(pdev, &ichxrom_pci_tbl[0]);
  327. }
  328. return -ENXIO;
  329. #if 0
  330. return pci_register_driver(&ichxrom_driver);
  331. #endif
  332. }
  333. static void __exit cleanup_ichxrom(void)
  334. {
  335. ichxrom_remove_one(ichxrom_window.pdev);
  336. }
  337. module_init(init_ichxrom);
  338. module_exit(cleanup_ichxrom);
  339. MODULE_LICENSE("GPL");
  340. MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");
  341. MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ICHX southbridge");