ngene.h 24 KB

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  1. /*
  2. * ngene.h: nGene PCIe bridge driver
  3. *
  4. * Copyright (C) 2005-2007 Micronas
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 only, as published by the Free Software Foundation.
  9. *
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * To obtain the license, point your browser to
  17. * http://www.gnu.org/copyleft/gpl.html
  18. */
  19. #ifndef _NGENE_H_
  20. #define _NGENE_H_
  21. #include <linux/types.h>
  22. #include <linux/sched.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/i2c.h>
  25. #include <asm/dma.h>
  26. #include <linux/scatterlist.h>
  27. #include <linux/dvb/frontend.h>
  28. #include "dmxdev.h"
  29. #include "dvbdev.h"
  30. #include "dvb_demux.h"
  31. #include "dvb_ca_en50221.h"
  32. #include "dvb_frontend.h"
  33. #include "dvb_ringbuffer.h"
  34. #include "dvb_net.h"
  35. #include "cxd2099.h"
  36. #define DEVICE_NAME "ngene"
  37. #define NGENE_VID 0x18c3
  38. #define NGENE_PID 0x0720
  39. #ifndef VIDEO_CAP_VC1
  40. #define VIDEO_CAP_AVC 128
  41. #define VIDEO_CAP_H264 128
  42. #define VIDEO_CAP_VC1 256
  43. #define VIDEO_CAP_WMV9 256
  44. #define VIDEO_CAP_MPEG4 512
  45. #endif
  46. enum STREAM {
  47. STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
  48. STREAM_VIDEOIN2,
  49. STREAM_AUDIOIN1, /* I2S or SPI Input */
  50. STREAM_AUDIOIN2,
  51. STREAM_AUDIOOUT,
  52. MAX_STREAM
  53. };
  54. enum SMODE_BITS {
  55. SMODE_AUDIO_SPDIF = 0x20,
  56. SMODE_AVSYNC = 0x10,
  57. SMODE_TRANSPORT_STREAM = 0x08,
  58. SMODE_AUDIO_CAPTURE = 0x04,
  59. SMODE_VBI_CAPTURE = 0x02,
  60. SMODE_VIDEO_CAPTURE = 0x01
  61. };
  62. enum STREAM_FLAG_BITS {
  63. SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
  64. SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
  65. SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
  66. SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
  67. SFLAG_COLORBAR = 0x04, /* Select colorbar */
  68. };
  69. #define PROGRAM_ROM 0x0000
  70. #define PROGRAM_SRAM 0x1000
  71. #define PERIPHERALS0 0x8000
  72. #define PERIPHERALS1 0x9000
  73. #define SHARED_BUFFER 0xC000
  74. #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
  75. #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
  76. #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
  77. #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
  78. #define NGENE_STATUS (SHARED_BUFFER+0x0208)
  79. #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
  80. #define NGENE_EVENT (SHARED_BUFFER+0x0210)
  81. #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
  82. #define VARIABLES (SHARED_BUFFER+0x0210)
  83. #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
  84. #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
  85. #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
  86. #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
  87. #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
  88. #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
  89. #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
  90. #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
  91. #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
  92. #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
  93. #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
  94. #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
  95. #define SG_V_OUT (SHARED_BUFFER+0x0D80)
  96. #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
  97. #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
  98. #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
  99. #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
  100. #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
  101. #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
  102. #define DATA_V_OUT (SHARED_BUFFER+0x3000)
  103. #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
  104. #define TIMESTAMPS 0xA000
  105. #define SCRATCHPAD 0xA080
  106. #define FORCE_INT 0xA088
  107. #define FORCE_NMI 0xA090
  108. #define INT_STATUS 0xA0A0
  109. #define DEV_VER 0x9004
  110. #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
  111. struct SG_ADDR {
  112. u64 start;
  113. u64 curr;
  114. u16 curr_ptr;
  115. u16 elements;
  116. u32 pad[3];
  117. } __attribute__ ((__packed__));
  118. struct SHARED_MEMORY {
  119. /* C000 */
  120. u32 HostToNgene[64];
  121. /* C100 */
  122. u32 NgeneToHost[64];
  123. /* C200 */
  124. u64 NgeneCommand;
  125. u64 NgeneStatus;
  126. u64 NgeneEvent;
  127. /* C210 */
  128. u8 pad1[0xc260 - 0xc218];
  129. /* C260 */
  130. u32 IntCounts;
  131. u32 IntEnable;
  132. /* C268 */
  133. u8 pad2[0xd000 - 0xc268];
  134. } __attribute__ ((__packed__));
  135. struct BUFFER_STREAM_RESULTS {
  136. u32 Clock; /* Stream time in 100ns units */
  137. u16 RemainingLines; /* Remaining lines in this field.
  138. 0 for complete field */
  139. u8 FieldCount; /* Video field number */
  140. u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
  141. Bit 0 = FieldID */
  142. u16 BlockCount; /* Audio block count (unused) */
  143. u8 Reserved[2];
  144. u32 DTOUpdate;
  145. } __attribute__ ((__packed__));
  146. struct HW_SCATTER_GATHER_ELEMENT {
  147. u64 Address;
  148. u32 Length;
  149. u32 Reserved;
  150. } __attribute__ ((__packed__));
  151. struct BUFFER_HEADER {
  152. u64 Next;
  153. struct BUFFER_STREAM_RESULTS SR;
  154. u32 Number_of_entries_1;
  155. u32 Reserved5;
  156. u64 Address_of_first_entry_1;
  157. u32 Number_of_entries_2;
  158. u32 Reserved7;
  159. u64 Address_of_first_entry_2;
  160. } __attribute__ ((__packed__));
  161. struct EVENT_BUFFER {
  162. u32 TimeStamp;
  163. u8 GPIOStatus;
  164. u8 UARTStatus;
  165. u8 RXCharacter;
  166. u8 EventStatus;
  167. u32 Reserved[2];
  168. } __attribute__ ((__packed__));
  169. /* Firmware commands. */
  170. enum OPCODES {
  171. CMD_NOP = 0,
  172. CMD_FWLOAD_PREPARE = 0x01,
  173. CMD_FWLOAD_FINISH = 0x02,
  174. CMD_I2C_READ = 0x03,
  175. CMD_I2C_WRITE = 0x04,
  176. CMD_I2C_WRITE_NOSTOP = 0x05,
  177. CMD_I2C_CONTINUE_WRITE = 0x06,
  178. CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
  179. CMD_DEBUG_OUTPUT = 0x09,
  180. CMD_CONTROL = 0x10,
  181. CMD_CONFIGURE_BUFFER = 0x11,
  182. CMD_CONFIGURE_FREE_BUFFER = 0x12,
  183. CMD_SPI_READ = 0x13,
  184. CMD_SPI_WRITE = 0x14,
  185. CMD_MEM_READ = 0x20,
  186. CMD_MEM_WRITE = 0x21,
  187. CMD_SFR_READ = 0x22,
  188. CMD_SFR_WRITE = 0x23,
  189. CMD_IRAM_READ = 0x24,
  190. CMD_IRAM_WRITE = 0x25,
  191. CMD_SET_GPIO_PIN = 0x26,
  192. CMD_SET_GPIO_INT = 0x27,
  193. CMD_CONFIGURE_UART = 0x28,
  194. CMD_WRITE_UART = 0x29,
  195. MAX_CMD
  196. };
  197. enum RESPONSES {
  198. OK = 0,
  199. ERROR = 1
  200. };
  201. struct FW_HEADER {
  202. u8 Opcode;
  203. u8 Length;
  204. } __attribute__ ((__packed__));
  205. struct FW_I2C_WRITE {
  206. struct FW_HEADER hdr;
  207. u8 Device;
  208. u8 Data[250];
  209. } __attribute__ ((__packed__));
  210. struct FW_I2C_CONTINUE_WRITE {
  211. struct FW_HEADER hdr;
  212. u8 Data[250];
  213. } __attribute__ ((__packed__));
  214. struct FW_I2C_READ {
  215. struct FW_HEADER hdr;
  216. u8 Device;
  217. u8 Data[252]; /* followed by two bytes of read data count */
  218. } __attribute__ ((__packed__));
  219. struct FW_SPI_WRITE {
  220. struct FW_HEADER hdr;
  221. u8 ModeSelect;
  222. u8 Data[250];
  223. } __attribute__ ((__packed__));
  224. struct FW_SPI_READ {
  225. struct FW_HEADER hdr;
  226. u8 ModeSelect;
  227. u8 Data[252]; /* followed by two bytes of read data count */
  228. } __attribute__ ((__packed__));
  229. struct FW_FWLOAD_PREPARE {
  230. struct FW_HEADER hdr;
  231. } __attribute__ ((__packed__));
  232. struct FW_FWLOAD_FINISH {
  233. struct FW_HEADER hdr;
  234. u16 Address; /* address of final block */
  235. u16 Length;
  236. } __attribute__ ((__packed__));
  237. /*
  238. * Meaning of FW_STREAM_CONTROL::Mode bits:
  239. * Bit 7: Loopback PEXin to PEXout using TVOut channel
  240. * Bit 6: AVLOOP
  241. * Bit 5: Audio select; 0=I2S, 1=SPDIF
  242. * Bit 4: AVSYNC
  243. * Bit 3: Enable transport stream
  244. * Bit 2: Enable audio capture
  245. * Bit 1: Enable ITU-Video VBI capture
  246. * Bit 0: Enable ITU-Video capture
  247. *
  248. * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
  249. * Bit 7: continuous capture
  250. * Bit 6: capture one field
  251. * Bit 5: capture one frame
  252. * Bit 4: unused
  253. * Bit 3: starting field; 0=odd, 1=even
  254. * Bit 2: sample size; 0=8-bit, 1=10-bit
  255. * Bit 1: data format; 0=UYVY, 1=YUY2
  256. * Bit 0: resets buffer pointers
  257. */
  258. enum FSC_MODE_BITS {
  259. SMODE_LOOPBACK = 0x80,
  260. SMODE_AVLOOP = 0x40,
  261. _SMODE_AUDIO_SPDIF = 0x20,
  262. _SMODE_AVSYNC = 0x10,
  263. _SMODE_TRANSPORT_STREAM = 0x08,
  264. _SMODE_AUDIO_CAPTURE = 0x04,
  265. _SMODE_VBI_CAPTURE = 0x02,
  266. _SMODE_VIDEO_CAPTURE = 0x01
  267. };
  268. /* Meaning of FW_STREAM_CONTROL::Stream bits:
  269. * Bit 3: Audio sample count: 0 = relative, 1 = absolute
  270. * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
  271. * Bits 1-0: stream select, UVI1, UVI2, TVOUT
  272. */
  273. struct FW_STREAM_CONTROL {
  274. struct FW_HEADER hdr;
  275. u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
  276. u8 Control; /* Value written to UVI1_CTL */
  277. u8 Mode; /* Controls clock source */
  278. u8 SetupDataLen; /* Length of setup data, MSB=1 write
  279. backwards */
  280. u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
  281. for TS and Audio */
  282. u64 Buffer_Address; /* Address of first buffer header */
  283. u16 BytesPerVideoLine;
  284. u16 MaxLinesPerField;
  285. u16 MinLinesPerField;
  286. u16 Reserved_1;
  287. u16 BytesPerVBILine;
  288. u16 MaxVBILinesPerField;
  289. u16 MinVBILinesPerField;
  290. u16 SetupDataAddr; /* ngene relative address of setup data */
  291. u8 SetupData[32]; /* setup data */
  292. } __attribute__((__packed__));
  293. #define AUDIO_BLOCK_SIZE 256
  294. #define TS_BLOCK_SIZE 256
  295. struct FW_MEM_READ {
  296. struct FW_HEADER hdr;
  297. u16 address;
  298. } __attribute__ ((__packed__));
  299. struct FW_MEM_WRITE {
  300. struct FW_HEADER hdr;
  301. u16 address;
  302. u8 data;
  303. } __attribute__ ((__packed__));
  304. struct FW_SFR_IRAM_READ {
  305. struct FW_HEADER hdr;
  306. u8 address;
  307. } __attribute__ ((__packed__));
  308. struct FW_SFR_IRAM_WRITE {
  309. struct FW_HEADER hdr;
  310. u8 address;
  311. u8 data;
  312. } __attribute__ ((__packed__));
  313. struct FW_SET_GPIO_PIN {
  314. struct FW_HEADER hdr;
  315. u8 select;
  316. } __attribute__ ((__packed__));
  317. struct FW_SET_GPIO_INT {
  318. struct FW_HEADER hdr;
  319. u8 select;
  320. } __attribute__ ((__packed__));
  321. struct FW_SET_DEBUGMODE {
  322. struct FW_HEADER hdr;
  323. u8 debug_flags;
  324. } __attribute__ ((__packed__));
  325. struct FW_CONFIGURE_BUFFERS {
  326. struct FW_HEADER hdr;
  327. u8 config;
  328. } __attribute__ ((__packed__));
  329. enum _BUFFER_CONFIGS {
  330. /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
  331. BUFFER_CONFIG_4422 = 0,
  332. /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
  333. BUFFER_CONFIG_3333 = 1,
  334. /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
  335. BUFFER_CONFIG_8022 = 2,
  336. BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
  337. };
  338. struct FW_CONFIGURE_FREE_BUFFERS {
  339. struct FW_HEADER hdr;
  340. u8 UVI1_BufferLength;
  341. u8 UVI2_BufferLength;
  342. u8 TVO_BufferLength;
  343. u8 AUD1_BufferLength;
  344. u8 AUD2_BufferLength;
  345. u8 TVA_BufferLength;
  346. } __attribute__ ((__packed__));
  347. struct FW_CONFIGURE_UART {
  348. struct FW_HEADER hdr;
  349. u8 UartControl;
  350. } __attribute__ ((__packed__));
  351. enum _UART_CONFIG {
  352. _UART_BAUDRATE_19200 = 0,
  353. _UART_BAUDRATE_9600 = 1,
  354. _UART_BAUDRATE_4800 = 2,
  355. _UART_BAUDRATE_2400 = 3,
  356. _UART_RX_ENABLE = 0x40,
  357. _UART_TX_ENABLE = 0x80,
  358. };
  359. struct FW_WRITE_UART {
  360. struct FW_HEADER hdr;
  361. u8 Data[252];
  362. } __attribute__ ((__packed__));
  363. struct ngene_command {
  364. u32 in_len;
  365. u32 out_len;
  366. union {
  367. u32 raw[64];
  368. u8 raw8[256];
  369. struct FW_HEADER hdr;
  370. struct FW_I2C_WRITE I2CWrite;
  371. struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
  372. struct FW_I2C_READ I2CRead;
  373. struct FW_STREAM_CONTROL StreamControl;
  374. struct FW_FWLOAD_PREPARE FWLoadPrepare;
  375. struct FW_FWLOAD_FINISH FWLoadFinish;
  376. struct FW_MEM_READ MemoryRead;
  377. struct FW_MEM_WRITE MemoryWrite;
  378. struct FW_SFR_IRAM_READ SfrIramRead;
  379. struct FW_SFR_IRAM_WRITE SfrIramWrite;
  380. struct FW_SPI_WRITE SPIWrite;
  381. struct FW_SPI_READ SPIRead;
  382. struct FW_SET_GPIO_PIN SetGpioPin;
  383. struct FW_SET_GPIO_INT SetGpioInt;
  384. struct FW_SET_DEBUGMODE SetDebugMode;
  385. struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
  386. struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
  387. struct FW_CONFIGURE_UART ConfigureUart;
  388. struct FW_WRITE_UART WriteUart;
  389. } cmd;
  390. } __attribute__ ((__packed__));
  391. #define NGENE_INTERFACE_VERSION 0x103
  392. #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
  393. #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
  394. #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
  395. #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
  396. #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
  397. Max: (1920x1080i60) */
  398. #define OVERFLOW_BUFFER_SIZE (8192)
  399. #define RING_SIZE_VIDEO 4
  400. #define RING_SIZE_AUDIO 8
  401. #define RING_SIZE_TS 8
  402. #define NUM_SCATTER_GATHER_ENTRIES 8
  403. #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
  404. RING_SIZE_VIDEO * 2) + \
  405. (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
  406. (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
  407. (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
  408. (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
  409. (RING_SIZE_TS * PAGE_SIZE * 4) + \
  410. 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
  411. #define EVENT_QUEUE_SIZE 16
  412. /* Gathers the current state of a single channel. */
  413. struct SBufferHeader {
  414. struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
  415. struct SBufferHeader *Next;
  416. void *Buffer1;
  417. struct HW_SCATTER_GATHER_ELEMENT *scList1;
  418. void *Buffer2;
  419. struct HW_SCATTER_GATHER_ELEMENT *scList2;
  420. };
  421. /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
  422. #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
  423. enum HWSTATE {
  424. HWSTATE_STOP,
  425. HWSTATE_STARTUP,
  426. HWSTATE_RUN,
  427. HWSTATE_PAUSE,
  428. };
  429. enum KSSTATE {
  430. KSSTATE_STOP,
  431. KSSTATE_ACQUIRE,
  432. KSSTATE_PAUSE,
  433. KSSTATE_RUN,
  434. };
  435. struct SRingBufferDescriptor {
  436. struct SBufferHeader *Head; /* Points to first buffer in ring buffer
  437. structure*/
  438. u64 PAHead; /* Physical address of first buffer */
  439. u32 MemSize; /* Memory size of allocated ring buffers
  440. (needed for freeing) */
  441. u32 NumBuffers; /* Number of buffers in the ring */
  442. u32 Buffer1Length; /* Allocated length of Buffer 1 */
  443. u32 Buffer2Length; /* Allocated length of Buffer 2 */
  444. void *SCListMem; /* Memory to hold scatter gather lists for this
  445. ring */
  446. u64 PASCListMem; /* Physical address .. */
  447. u32 SCListMemSize; /* Size of this memory */
  448. };
  449. enum STREAMMODEFLAGS {
  450. StreamMode_NONE = 0, /* Stream not used */
  451. StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
  452. StreamMode_TSIN = 2, /* Transport stream input (all) */
  453. StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
  454. (only stream 0) */
  455. StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
  456. };
  457. enum BufferExchangeFlags {
  458. BEF_EVEN_FIELD = 0x00000001,
  459. BEF_CONTINUATION = 0x00000002,
  460. BEF_MORE_DATA = 0x00000004,
  461. BEF_OVERFLOW = 0x00000008,
  462. DF_SWAP32 = 0x00010000,
  463. };
  464. typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
  465. struct MICI_STREAMINFO {
  466. IBufferExchange *pExchange;
  467. IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
  468. u8 Stream;
  469. u8 Flags;
  470. u8 Mode;
  471. u8 Reserved;
  472. u16 nLinesVideo;
  473. u16 nBytesPerLineVideo;
  474. u16 nLinesVBI;
  475. u16 nBytesPerLineVBI;
  476. u32 CaptureLength; /* Used for audio and transport stream */
  477. };
  478. /****************************************************************************/
  479. /* STRUCTS ******************************************************************/
  480. /****************************************************************************/
  481. /* sound hardware definition */
  482. #define MIXER_ADDR_TVTUNER 0
  483. #define MIXER_ADDR_LAST 0
  484. struct ngene_channel;
  485. /*struct sound chip*/
  486. struct mychip {
  487. struct ngene_channel *chan;
  488. struct snd_card *card;
  489. struct pci_dev *pci;
  490. struct snd_pcm_substream *substream;
  491. struct snd_pcm *pcm;
  492. unsigned long port;
  493. int irq;
  494. spinlock_t mixer_lock;
  495. spinlock_t lock;
  496. int mixer_volume[MIXER_ADDR_LAST + 1][2];
  497. int capture_source[MIXER_ADDR_LAST + 1][2];
  498. };
  499. #ifdef NGENE_V4L
  500. struct ngene_overlay {
  501. int tvnorm;
  502. struct v4l2_rect w;
  503. enum v4l2_field field;
  504. struct v4l2_clip *clips;
  505. int nclips;
  506. int setup_ok;
  507. };
  508. struct ngene_tvnorm {
  509. int v4l2_id;
  510. char *name;
  511. u16 swidth, sheight; /* scaled standard width, height */
  512. int tuner_norm;
  513. int soundstd;
  514. };
  515. struct ngene_vopen {
  516. struct ngene_channel *ch;
  517. enum v4l2_priority prio;
  518. int width;
  519. int height;
  520. int depth;
  521. struct videobuf_queue vbuf_q;
  522. struct videobuf_queue vbi;
  523. int fourcc;
  524. int picxcount;
  525. int resources;
  526. enum v4l2_buf_type type;
  527. const struct ngene_format *fmt;
  528. const struct ngene_format *ovfmt;
  529. struct ngene_overlay ov;
  530. };
  531. #endif
  532. struct ngene_channel {
  533. struct device device;
  534. struct i2c_adapter i2c_adapter;
  535. struct ngene *dev;
  536. int number;
  537. int type;
  538. int mode;
  539. bool has_adapter;
  540. bool has_demux;
  541. int demod_type;
  542. int (*gate_ctrl)(struct dvb_frontend *, int);
  543. struct dvb_frontend *fe;
  544. struct dvb_frontend *fe2;
  545. struct dmxdev dmxdev;
  546. struct dvb_demux demux;
  547. struct dvb_net dvbnet;
  548. struct dmx_frontend hw_frontend;
  549. struct dmx_frontend mem_frontend;
  550. int users;
  551. struct video_device *v4l_dev;
  552. struct dvb_device *ci_dev;
  553. struct tasklet_struct demux_tasklet;
  554. struct SBufferHeader *nextBuffer;
  555. enum KSSTATE State;
  556. enum HWSTATE HWState;
  557. u8 Stream;
  558. u8 Flags;
  559. u8 Mode;
  560. IBufferExchange *pBufferExchange;
  561. IBufferExchange *pBufferExchange2;
  562. spinlock_t state_lock;
  563. u16 nLines;
  564. u16 nBytesPerLine;
  565. u16 nVBILines;
  566. u16 nBytesPerVBILine;
  567. u16 itumode;
  568. u32 Capture1Length;
  569. u32 Capture2Length;
  570. struct SRingBufferDescriptor RingBuffer;
  571. struct SRingBufferDescriptor TSRingBuffer;
  572. struct SRingBufferDescriptor TSIdleBuffer;
  573. u32 DataFormatFlags;
  574. int AudioDTOUpdated;
  575. u32 AudioDTOValue;
  576. int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode);
  577. u8 lnbh;
  578. /* stuff from analog driver */
  579. int minor;
  580. struct mychip *mychip;
  581. struct snd_card *soundcard;
  582. u8 *evenbuffer;
  583. u8 dma_on;
  584. int soundstreamon;
  585. int audiomute;
  586. int soundbuffisallocated;
  587. int sndbuffflag;
  588. int tun_rdy;
  589. int dec_rdy;
  590. int tun_dec_rdy;
  591. int lastbufferflag;
  592. struct ngene_tvnorm *tvnorms;
  593. int tvnorm_num;
  594. int tvnorm;
  595. #ifdef NGENE_V4L
  596. int videousers;
  597. struct v4l2_prio_state prio;
  598. struct ngene_vopen init;
  599. int resources;
  600. struct v4l2_framebuffer fbuf;
  601. struct ngene_buffer *screen; /* overlay */
  602. struct list_head capture; /* video capture queue */
  603. spinlock_t s_lock;
  604. struct semaphore reslock;
  605. #endif
  606. int running;
  607. };
  608. struct ngene_ci {
  609. struct device device;
  610. struct i2c_adapter i2c_adapter;
  611. struct ngene *dev;
  612. struct dvb_ca_en50221 *en;
  613. };
  614. struct ngene;
  615. typedef void (rx_cb_t)(struct ngene *, u32, u8);
  616. typedef void (tx_cb_t)(struct ngene *, u32);
  617. struct ngene {
  618. int nr;
  619. struct pci_dev *pci_dev;
  620. unsigned char __iomem *iomem;
  621. /*struct i2c_adapter i2c_adapter;*/
  622. u32 device_version;
  623. u32 fw_interface_version;
  624. u32 icounts;
  625. bool msi_enabled;
  626. bool cmd_timeout_workaround;
  627. u8 *CmdDoneByte;
  628. int BootFirmware;
  629. void *OverflowBuffer;
  630. dma_addr_t PAOverflowBuffer;
  631. void *FWInterfaceBuffer;
  632. dma_addr_t PAFWInterfaceBuffer;
  633. u8 *ngenetohost;
  634. u8 *hosttongene;
  635. struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
  636. int EventQueueOverflowCount;
  637. int EventQueueOverflowFlag;
  638. struct tasklet_struct event_tasklet;
  639. struct EVENT_BUFFER *EventBuffer;
  640. int EventQueueWriteIndex;
  641. int EventQueueReadIndex;
  642. wait_queue_head_t cmd_wq;
  643. int cmd_done;
  644. struct mutex cmd_mutex;
  645. struct mutex stream_mutex;
  646. struct semaphore pll_mutex;
  647. struct mutex i2c_switch_mutex;
  648. int i2c_current_channel;
  649. int i2c_current_bus;
  650. spinlock_t cmd_lock;
  651. struct dvb_adapter adapter[MAX_STREAM];
  652. struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
  653. struct ngene_channel channel[MAX_STREAM];
  654. struct ngene_info *card_info;
  655. tx_cb_t *TxEventNotify;
  656. rx_cb_t *RxEventNotify;
  657. int tx_busy;
  658. wait_queue_head_t tx_wq;
  659. wait_queue_head_t rx_wq;
  660. #define UART_RBUF_LEN 4096
  661. u8 uart_rbuf[UART_RBUF_LEN];
  662. int uart_rp, uart_wp;
  663. #define TS_FILLER 0x6f
  664. u8 *tsout_buf;
  665. #define TSOUT_BUF_SIZE (512*188*8)
  666. struct dvb_ringbuffer tsout_rbuf;
  667. u8 *tsin_buf;
  668. #define TSIN_BUF_SIZE (512*188*8)
  669. struct dvb_ringbuffer tsin_rbuf;
  670. u8 *ain_buf;
  671. #define AIN_BUF_SIZE (128*1024)
  672. struct dvb_ringbuffer ain_rbuf;
  673. u8 *vin_buf;
  674. #define VIN_BUF_SIZE (4*1920*1080)
  675. struct dvb_ringbuffer vin_rbuf;
  676. unsigned long exp_val;
  677. int prev_cmd;
  678. struct ngene_ci ci;
  679. };
  680. struct ngene_info {
  681. int type;
  682. #define NGENE_APP 0
  683. #define NGENE_TERRATEC 1
  684. #define NGENE_SIDEWINDER 2
  685. #define NGENE_RACER 3
  686. #define NGENE_VIPER 4
  687. #define NGENE_PYTHON 5
  688. #define NGENE_VBOX_V1 6
  689. #define NGENE_VBOX_V2 7
  690. int fw_version;
  691. bool msi_supported;
  692. char *name;
  693. int io_type[MAX_STREAM];
  694. #define NGENE_IO_NONE 0
  695. #define NGENE_IO_TV 1
  696. #define NGENE_IO_HDTV 2
  697. #define NGENE_IO_TSIN 4
  698. #define NGENE_IO_TSOUT 8
  699. #define NGENE_IO_AIN 16
  700. void *fe_config[4];
  701. void *tuner_config[4];
  702. int (*demod_attach[4])(struct ngene_channel *);
  703. int (*tuner_attach[4])(struct ngene_channel *);
  704. u8 avf[4];
  705. u8 msp[4];
  706. u8 demoda[4];
  707. u8 lnb[4];
  708. int i2c_access;
  709. u8 ntsc;
  710. u8 tsf[4];
  711. u8 i2s[4];
  712. int (*gate_ctrl)(struct dvb_frontend *, int);
  713. int (*switch_ctrl)(struct ngene_channel *, int, int);
  714. };
  715. #ifdef NGENE_V4L
  716. struct ngene_format {
  717. char *name;
  718. int fourcc; /* video4linux 2 */
  719. int btformat; /* BT848_COLOR_FMT_* */
  720. int format;
  721. int btswap; /* BT848_COLOR_CTL_* */
  722. int depth; /* bit/pixel */
  723. int flags;
  724. int hshift, vshift; /* for planar modes */
  725. int palette;
  726. };
  727. #define RESOURCE_OVERLAY 1
  728. #define RESOURCE_VIDEO 2
  729. #define RESOURCE_VBI 4
  730. struct ngene_buffer {
  731. /* common v4l buffer stuff -- must be first */
  732. struct videobuf_buffer vb;
  733. /* ngene specific */
  734. const struct ngene_format *fmt;
  735. int tvnorm;
  736. int btformat;
  737. int btswap;
  738. };
  739. #endif
  740. /* Provided by ngene-core.c */
  741. int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);
  742. void ngene_remove(struct pci_dev *pdev);
  743. void ngene_shutdown(struct pci_dev *pdev);
  744. int ngene_command(struct ngene *dev, struct ngene_command *com);
  745. int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
  746. void set_transfer(struct ngene_channel *chan, int state);
  747. void FillTSBuffer(void *Buffer, int Length, u32 Flags);
  748. /* Provided by ngene-i2c.c */
  749. int ngene_i2c_init(struct ngene *dev, int dev_nr);
  750. /* Provided by ngene-dvb.c */
  751. extern struct dvb_device ngene_dvbdev_ci;
  752. void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
  753. void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
  754. int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
  755. int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
  756. int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
  757. int (*start_feed)(struct dvb_demux_feed *),
  758. int (*stop_feed)(struct dvb_demux_feed *),
  759. void *priv);
  760. int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
  761. struct dvb_demux *dvbdemux,
  762. struct dmx_frontend *hw_frontend,
  763. struct dmx_frontend *mem_frontend,
  764. struct dvb_adapter *dvb_adapter);
  765. #endif
  766. /* LocalWords: Endif
  767. */