ocrdma_verbs.c 80 KB

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  1. /* This file is part of the Emulex RoCE Device Driver for
  2. * RoCE (RDMA over Converged Ethernet) adapters.
  3. * Copyright (C) 2012-2015 Emulex. All rights reserved.
  4. * EMULEX and SLI are trademarks of Emulex.
  5. * www.emulex.com
  6. *
  7. * This software is available to you under a choice of one of two licenses.
  8. * You may choose to be licensed under the terms of the GNU General Public
  9. * License (GPL) Version 2, available from the file COPYING in the main
  10. * directory of this source tree, or the BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or without
  13. * modification, are permitted provided that the following conditions
  14. * are met:
  15. *
  16. * - Redistributions of source code must retain the above copyright notice,
  17. * this list of conditions and the following disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the distribution.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32. * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. * Contact Information:
  36. * linux-drivers@emulex.com
  37. *
  38. * Emulex
  39. * 3333 Susan Street
  40. * Costa Mesa, CA 92626
  41. */
  42. #include <linux/dma-mapping.h>
  43. #include <rdma/ib_verbs.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/iw_cm.h>
  46. #include <rdma/ib_umem.h>
  47. #include <rdma/ib_addr.h>
  48. #include <rdma/ib_cache.h>
  49. #include "ocrdma.h"
  50. #include "ocrdma_hw.h"
  51. #include "ocrdma_verbs.h"
  52. #include <rdma/ocrdma-abi.h>
  53. int ocrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  54. {
  55. if (index > 0)
  56. return -EINVAL;
  57. *pkey = 0xffff;
  58. return 0;
  59. }
  60. int ocrdma_query_gid(struct ib_device *ibdev, u8 port,
  61. int index, union ib_gid *sgid)
  62. {
  63. int ret;
  64. struct ocrdma_dev *dev;
  65. dev = get_ocrdma_dev(ibdev);
  66. memset(sgid, 0, sizeof(*sgid));
  67. if (index >= OCRDMA_MAX_SGID)
  68. return -EINVAL;
  69. ret = ib_get_cached_gid(ibdev, port, index, sgid, NULL);
  70. if (ret == -EAGAIN) {
  71. memcpy(sgid, &zgid, sizeof(*sgid));
  72. return 0;
  73. }
  74. return ret;
  75. }
  76. int ocrdma_add_gid(struct ib_device *device,
  77. u8 port_num,
  78. unsigned int index,
  79. const union ib_gid *gid,
  80. const struct ib_gid_attr *attr,
  81. void **context) {
  82. return 0;
  83. }
  84. int ocrdma_del_gid(struct ib_device *device,
  85. u8 port_num,
  86. unsigned int index,
  87. void **context) {
  88. return 0;
  89. }
  90. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr,
  91. struct ib_udata *uhw)
  92. {
  93. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  94. if (uhw->inlen || uhw->outlen)
  95. return -EINVAL;
  96. memset(attr, 0, sizeof *attr);
  97. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  98. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  99. ocrdma_get_guid(dev, (u8 *)&attr->sys_image_guid);
  100. attr->max_mr_size = dev->attr.max_mr_size;
  101. attr->page_size_cap = 0xffff000;
  102. attr->vendor_id = dev->nic_info.pdev->vendor;
  103. attr->vendor_part_id = dev->nic_info.pdev->device;
  104. attr->hw_ver = dev->asic_id;
  105. attr->max_qp = dev->attr.max_qp;
  106. attr->max_ah = OCRDMA_MAX_AH;
  107. attr->max_qp_wr = dev->attr.max_wqe;
  108. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  109. IB_DEVICE_RC_RNR_NAK_GEN |
  110. IB_DEVICE_SHUTDOWN_PORT |
  111. IB_DEVICE_SYS_IMAGE_GUID |
  112. IB_DEVICE_LOCAL_DMA_LKEY |
  113. IB_DEVICE_MEM_MGT_EXTENSIONS;
  114. attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_recv_sge);
  115. attr->max_sge_rd = dev->attr.max_rdma_sge;
  116. attr->max_cq = dev->attr.max_cq;
  117. attr->max_cqe = dev->attr.max_cqe;
  118. attr->max_mr = dev->attr.max_mr;
  119. attr->max_mw = dev->attr.max_mw;
  120. attr->max_pd = dev->attr.max_pd;
  121. attr->atomic_cap = 0;
  122. attr->max_fmr = 0;
  123. attr->max_map_per_fmr = 0;
  124. attr->max_qp_rd_atom =
  125. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  126. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  127. attr->max_srq = dev->attr.max_srq;
  128. attr->max_srq_sge = dev->attr.max_srq_sge;
  129. attr->max_srq_wr = dev->attr.max_rqe;
  130. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  131. attr->max_fast_reg_page_list_len = dev->attr.max_pages_per_frmr;
  132. attr->max_pkeys = 1;
  133. return 0;
  134. }
  135. struct net_device *ocrdma_get_netdev(struct ib_device *ibdev, u8 port_num)
  136. {
  137. struct ocrdma_dev *dev;
  138. struct net_device *ndev = NULL;
  139. rcu_read_lock();
  140. dev = get_ocrdma_dev(ibdev);
  141. if (dev)
  142. ndev = dev->nic_info.netdev;
  143. if (ndev)
  144. dev_hold(ndev);
  145. rcu_read_unlock();
  146. return ndev;
  147. }
  148. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  149. u8 *ib_speed, u8 *ib_width)
  150. {
  151. int status;
  152. u8 speed;
  153. status = ocrdma_mbx_get_link_speed(dev, &speed, NULL);
  154. if (status)
  155. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  156. switch (speed) {
  157. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  158. *ib_speed = IB_SPEED_SDR;
  159. *ib_width = IB_WIDTH_1X;
  160. break;
  161. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  162. *ib_speed = IB_SPEED_QDR;
  163. *ib_width = IB_WIDTH_1X;
  164. break;
  165. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  166. *ib_speed = IB_SPEED_DDR;
  167. *ib_width = IB_WIDTH_4X;
  168. break;
  169. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  170. *ib_speed = IB_SPEED_QDR;
  171. *ib_width = IB_WIDTH_4X;
  172. break;
  173. default:
  174. /* Unsupported */
  175. *ib_speed = IB_SPEED_SDR;
  176. *ib_width = IB_WIDTH_1X;
  177. }
  178. }
  179. int ocrdma_query_port(struct ib_device *ibdev,
  180. u8 port, struct ib_port_attr *props)
  181. {
  182. enum ib_port_state port_state;
  183. struct ocrdma_dev *dev;
  184. struct net_device *netdev;
  185. /* props being zeroed by the caller, avoid zeroing it here */
  186. dev = get_ocrdma_dev(ibdev);
  187. if (port > 1) {
  188. pr_err("%s(%d) invalid_port=0x%x\n", __func__,
  189. dev->id, port);
  190. return -EINVAL;
  191. }
  192. netdev = dev->nic_info.netdev;
  193. if (netif_running(netdev) && netif_oper_up(netdev)) {
  194. port_state = IB_PORT_ACTIVE;
  195. props->phys_state = 5;
  196. } else {
  197. port_state = IB_PORT_DOWN;
  198. props->phys_state = 3;
  199. }
  200. props->max_mtu = IB_MTU_4096;
  201. props->active_mtu = iboe_get_mtu(netdev->mtu);
  202. props->lid = 0;
  203. props->lmc = 0;
  204. props->sm_lid = 0;
  205. props->sm_sl = 0;
  206. props->state = port_state;
  207. props->port_cap_flags =
  208. IB_PORT_CM_SUP |
  209. IB_PORT_REINIT_SUP |
  210. IB_PORT_DEVICE_MGMT_SUP | IB_PORT_VENDOR_CLASS_SUP |
  211. IB_PORT_IP_BASED_GIDS;
  212. props->gid_tbl_len = OCRDMA_MAX_SGID;
  213. props->pkey_tbl_len = 1;
  214. props->bad_pkey_cntr = 0;
  215. props->qkey_viol_cntr = 0;
  216. get_link_speed_and_width(dev, &props->active_speed,
  217. &props->active_width);
  218. props->max_msg_sz = 0x80000000;
  219. props->max_vl_num = 4;
  220. return 0;
  221. }
  222. int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
  223. struct ib_port_modify *props)
  224. {
  225. struct ocrdma_dev *dev;
  226. dev = get_ocrdma_dev(ibdev);
  227. if (port > 1) {
  228. pr_err("%s(%d) invalid_port=0x%x\n", __func__, dev->id, port);
  229. return -EINVAL;
  230. }
  231. return 0;
  232. }
  233. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  234. unsigned long len)
  235. {
  236. struct ocrdma_mm *mm;
  237. mm = kzalloc(sizeof(*mm), GFP_KERNEL);
  238. if (mm == NULL)
  239. return -ENOMEM;
  240. mm->key.phy_addr = phy_addr;
  241. mm->key.len = len;
  242. INIT_LIST_HEAD(&mm->entry);
  243. mutex_lock(&uctx->mm_list_lock);
  244. list_add_tail(&mm->entry, &uctx->mm_head);
  245. mutex_unlock(&uctx->mm_list_lock);
  246. return 0;
  247. }
  248. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  249. unsigned long len)
  250. {
  251. struct ocrdma_mm *mm, *tmp;
  252. mutex_lock(&uctx->mm_list_lock);
  253. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  254. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  255. continue;
  256. list_del(&mm->entry);
  257. kfree(mm);
  258. break;
  259. }
  260. mutex_unlock(&uctx->mm_list_lock);
  261. }
  262. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  263. unsigned long len)
  264. {
  265. bool found = false;
  266. struct ocrdma_mm *mm;
  267. mutex_lock(&uctx->mm_list_lock);
  268. list_for_each_entry(mm, &uctx->mm_head, entry) {
  269. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  270. continue;
  271. found = true;
  272. break;
  273. }
  274. mutex_unlock(&uctx->mm_list_lock);
  275. return found;
  276. }
  277. static u16 _ocrdma_pd_mgr_get_bitmap(struct ocrdma_dev *dev, bool dpp_pool)
  278. {
  279. u16 pd_bitmap_idx = 0;
  280. const unsigned long *pd_bitmap;
  281. if (dpp_pool) {
  282. pd_bitmap = dev->pd_mgr->pd_dpp_bitmap;
  283. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  284. dev->pd_mgr->max_dpp_pd);
  285. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_dpp_bitmap);
  286. dev->pd_mgr->pd_dpp_count++;
  287. if (dev->pd_mgr->pd_dpp_count > dev->pd_mgr->pd_dpp_thrsh)
  288. dev->pd_mgr->pd_dpp_thrsh = dev->pd_mgr->pd_dpp_count;
  289. } else {
  290. pd_bitmap = dev->pd_mgr->pd_norm_bitmap;
  291. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  292. dev->pd_mgr->max_normal_pd);
  293. __set_bit(pd_bitmap_idx, dev->pd_mgr->pd_norm_bitmap);
  294. dev->pd_mgr->pd_norm_count++;
  295. if (dev->pd_mgr->pd_norm_count > dev->pd_mgr->pd_norm_thrsh)
  296. dev->pd_mgr->pd_norm_thrsh = dev->pd_mgr->pd_norm_count;
  297. }
  298. return pd_bitmap_idx;
  299. }
  300. static int _ocrdma_pd_mgr_put_bitmap(struct ocrdma_dev *dev, u16 pd_id,
  301. bool dpp_pool)
  302. {
  303. u16 pd_count;
  304. u16 pd_bit_index;
  305. pd_count = dpp_pool ? dev->pd_mgr->pd_dpp_count :
  306. dev->pd_mgr->pd_norm_count;
  307. if (pd_count == 0)
  308. return -EINVAL;
  309. if (dpp_pool) {
  310. pd_bit_index = pd_id - dev->pd_mgr->pd_dpp_start;
  311. if (pd_bit_index >= dev->pd_mgr->max_dpp_pd) {
  312. return -EINVAL;
  313. } else {
  314. __clear_bit(pd_bit_index, dev->pd_mgr->pd_dpp_bitmap);
  315. dev->pd_mgr->pd_dpp_count--;
  316. }
  317. } else {
  318. pd_bit_index = pd_id - dev->pd_mgr->pd_norm_start;
  319. if (pd_bit_index >= dev->pd_mgr->max_normal_pd) {
  320. return -EINVAL;
  321. } else {
  322. __clear_bit(pd_bit_index, dev->pd_mgr->pd_norm_bitmap);
  323. dev->pd_mgr->pd_norm_count--;
  324. }
  325. }
  326. return 0;
  327. }
  328. static int ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,
  329. bool dpp_pool)
  330. {
  331. int status;
  332. mutex_lock(&dev->dev_lock);
  333. status = _ocrdma_pd_mgr_put_bitmap(dev, pd_id, dpp_pool);
  334. mutex_unlock(&dev->dev_lock);
  335. return status;
  336. }
  337. static int ocrdma_get_pd_num(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
  338. {
  339. u16 pd_idx = 0;
  340. int status = 0;
  341. mutex_lock(&dev->dev_lock);
  342. if (pd->dpp_enabled) {
  343. /* try allocating DPP PD, if not available then normal PD */
  344. if (dev->pd_mgr->pd_dpp_count < dev->pd_mgr->max_dpp_pd) {
  345. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, true);
  346. pd->id = dev->pd_mgr->pd_dpp_start + pd_idx;
  347. pd->dpp_page = dev->pd_mgr->dpp_page_index + pd_idx;
  348. } else if (dev->pd_mgr->pd_norm_count <
  349. dev->pd_mgr->max_normal_pd) {
  350. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  351. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  352. pd->dpp_enabled = false;
  353. } else {
  354. status = -EINVAL;
  355. }
  356. } else {
  357. if (dev->pd_mgr->pd_norm_count < dev->pd_mgr->max_normal_pd) {
  358. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  359. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  360. } else {
  361. status = -EINVAL;
  362. }
  363. }
  364. mutex_unlock(&dev->dev_lock);
  365. return status;
  366. }
  367. static struct ocrdma_pd *_ocrdma_alloc_pd(struct ocrdma_dev *dev,
  368. struct ocrdma_ucontext *uctx,
  369. struct ib_udata *udata)
  370. {
  371. struct ocrdma_pd *pd = NULL;
  372. int status;
  373. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  374. if (!pd)
  375. return ERR_PTR(-ENOMEM);
  376. if (udata && uctx && dev->attr.max_dpp_pds) {
  377. pd->dpp_enabled =
  378. ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R;
  379. pd->num_dpp_qp =
  380. pd->dpp_enabled ? (dev->nic_info.db_page_size /
  381. dev->attr.wqe_size) : 0;
  382. }
  383. if (dev->pd_mgr->pd_prealloc_valid) {
  384. status = ocrdma_get_pd_num(dev, pd);
  385. if (status == 0) {
  386. return pd;
  387. } else {
  388. kfree(pd);
  389. return ERR_PTR(status);
  390. }
  391. }
  392. retry:
  393. status = ocrdma_mbx_alloc_pd(dev, pd);
  394. if (status) {
  395. if (pd->dpp_enabled) {
  396. pd->dpp_enabled = false;
  397. pd->num_dpp_qp = 0;
  398. goto retry;
  399. } else {
  400. kfree(pd);
  401. return ERR_PTR(status);
  402. }
  403. }
  404. return pd;
  405. }
  406. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  407. struct ocrdma_pd *pd)
  408. {
  409. return (uctx->cntxt_pd == pd ? true : false);
  410. }
  411. static int _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  412. struct ocrdma_pd *pd)
  413. {
  414. int status;
  415. if (dev->pd_mgr->pd_prealloc_valid)
  416. status = ocrdma_put_pd_num(dev, pd->id, pd->dpp_enabled);
  417. else
  418. status = ocrdma_mbx_dealloc_pd(dev, pd);
  419. kfree(pd);
  420. return status;
  421. }
  422. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  423. struct ocrdma_ucontext *uctx,
  424. struct ib_udata *udata)
  425. {
  426. int status = 0;
  427. uctx->cntxt_pd = _ocrdma_alloc_pd(dev, uctx, udata);
  428. if (IS_ERR(uctx->cntxt_pd)) {
  429. status = PTR_ERR(uctx->cntxt_pd);
  430. uctx->cntxt_pd = NULL;
  431. goto err;
  432. }
  433. uctx->cntxt_pd->uctx = uctx;
  434. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  435. err:
  436. return status;
  437. }
  438. static int ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  439. {
  440. struct ocrdma_pd *pd = uctx->cntxt_pd;
  441. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  442. if (uctx->pd_in_use) {
  443. pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
  444. __func__, dev->id, pd->id);
  445. }
  446. uctx->cntxt_pd = NULL;
  447. (void)_ocrdma_dealloc_pd(dev, pd);
  448. return 0;
  449. }
  450. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  451. {
  452. struct ocrdma_pd *pd = NULL;
  453. mutex_lock(&uctx->mm_list_lock);
  454. if (!uctx->pd_in_use) {
  455. uctx->pd_in_use = true;
  456. pd = uctx->cntxt_pd;
  457. }
  458. mutex_unlock(&uctx->mm_list_lock);
  459. return pd;
  460. }
  461. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  462. {
  463. mutex_lock(&uctx->mm_list_lock);
  464. uctx->pd_in_use = false;
  465. mutex_unlock(&uctx->mm_list_lock);
  466. }
  467. struct ib_ucontext *ocrdma_alloc_ucontext(struct ib_device *ibdev,
  468. struct ib_udata *udata)
  469. {
  470. int status;
  471. struct ocrdma_ucontext *ctx;
  472. struct ocrdma_alloc_ucontext_resp resp;
  473. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  474. struct pci_dev *pdev = dev->nic_info.pdev;
  475. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  476. if (!udata)
  477. return ERR_PTR(-EFAULT);
  478. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  479. if (!ctx)
  480. return ERR_PTR(-ENOMEM);
  481. INIT_LIST_HEAD(&ctx->mm_head);
  482. mutex_init(&ctx->mm_list_lock);
  483. ctx->ah_tbl.va = dma_alloc_coherent(&pdev->dev, map_len,
  484. &ctx->ah_tbl.pa, GFP_KERNEL);
  485. if (!ctx->ah_tbl.va) {
  486. kfree(ctx);
  487. return ERR_PTR(-ENOMEM);
  488. }
  489. memset(ctx->ah_tbl.va, 0, map_len);
  490. ctx->ah_tbl.len = map_len;
  491. memset(&resp, 0, sizeof(resp));
  492. resp.ah_tbl_len = ctx->ah_tbl.len;
  493. resp.ah_tbl_page = virt_to_phys(ctx->ah_tbl.va);
  494. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  495. if (status)
  496. goto map_err;
  497. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  498. if (status)
  499. goto pd_err;
  500. resp.dev_id = dev->id;
  501. resp.max_inline_data = dev->attr.max_inline_data;
  502. resp.wqe_size = dev->attr.wqe_size;
  503. resp.rqe_size = dev->attr.rqe_size;
  504. resp.dpp_wqe_size = dev->attr.wqe_size;
  505. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  506. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  507. if (status)
  508. goto cpy_err;
  509. return &ctx->ibucontext;
  510. cpy_err:
  511. pd_err:
  512. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  513. map_err:
  514. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  515. ctx->ah_tbl.pa);
  516. kfree(ctx);
  517. return ERR_PTR(status);
  518. }
  519. int ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  520. {
  521. int status;
  522. struct ocrdma_mm *mm, *tmp;
  523. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  524. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  525. struct pci_dev *pdev = dev->nic_info.pdev;
  526. status = ocrdma_dealloc_ucontext_pd(uctx);
  527. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  528. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  529. uctx->ah_tbl.pa);
  530. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  531. list_del(&mm->entry);
  532. kfree(mm);
  533. }
  534. kfree(uctx);
  535. return status;
  536. }
  537. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  538. {
  539. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  540. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  541. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  542. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  543. unsigned long len = (vma->vm_end - vma->vm_start);
  544. int status;
  545. bool found;
  546. if (vma->vm_start & (PAGE_SIZE - 1))
  547. return -EINVAL;
  548. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  549. if (!found)
  550. return -EINVAL;
  551. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  552. dev->nic_info.db_total_size)) &&
  553. (len <= dev->nic_info.db_page_size)) {
  554. if (vma->vm_flags & VM_READ)
  555. return -EPERM;
  556. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  557. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  558. len, vma->vm_page_prot);
  559. } else if (dev->nic_info.dpp_unmapped_len &&
  560. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  561. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  562. dev->nic_info.dpp_unmapped_len)) &&
  563. (len <= dev->nic_info.dpp_unmapped_len)) {
  564. if (vma->vm_flags & VM_READ)
  565. return -EPERM;
  566. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  567. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  568. len, vma->vm_page_prot);
  569. } else {
  570. status = remap_pfn_range(vma, vma->vm_start,
  571. vma->vm_pgoff, len, vma->vm_page_prot);
  572. }
  573. return status;
  574. }
  575. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  576. struct ib_ucontext *ib_ctx,
  577. struct ib_udata *udata)
  578. {
  579. int status;
  580. u64 db_page_addr;
  581. u64 dpp_page_addr = 0;
  582. u32 db_page_size;
  583. struct ocrdma_alloc_pd_uresp rsp;
  584. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  585. memset(&rsp, 0, sizeof(rsp));
  586. rsp.id = pd->id;
  587. rsp.dpp_enabled = pd->dpp_enabled;
  588. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  589. db_page_size = dev->nic_info.db_page_size;
  590. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  591. if (status)
  592. return status;
  593. if (pd->dpp_enabled) {
  594. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  595. (pd->id * PAGE_SIZE);
  596. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  597. PAGE_SIZE);
  598. if (status)
  599. goto dpp_map_err;
  600. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  601. rsp.dpp_page_addr_lo = dpp_page_addr;
  602. }
  603. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  604. if (status)
  605. goto ucopy_err;
  606. pd->uctx = uctx;
  607. return 0;
  608. ucopy_err:
  609. if (pd->dpp_enabled)
  610. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  611. dpp_map_err:
  612. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  613. return status;
  614. }
  615. struct ib_pd *ocrdma_alloc_pd(struct ib_device *ibdev,
  616. struct ib_ucontext *context,
  617. struct ib_udata *udata)
  618. {
  619. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  620. struct ocrdma_pd *pd;
  621. struct ocrdma_ucontext *uctx = NULL;
  622. int status;
  623. u8 is_uctx_pd = false;
  624. if (udata && context) {
  625. uctx = get_ocrdma_ucontext(context);
  626. pd = ocrdma_get_ucontext_pd(uctx);
  627. if (pd) {
  628. is_uctx_pd = true;
  629. goto pd_mapping;
  630. }
  631. }
  632. pd = _ocrdma_alloc_pd(dev, uctx, udata);
  633. if (IS_ERR(pd)) {
  634. status = PTR_ERR(pd);
  635. goto exit;
  636. }
  637. pd_mapping:
  638. if (udata && context) {
  639. status = ocrdma_copy_pd_uresp(dev, pd, context, udata);
  640. if (status)
  641. goto err;
  642. }
  643. return &pd->ibpd;
  644. err:
  645. if (is_uctx_pd) {
  646. ocrdma_release_ucontext_pd(uctx);
  647. } else {
  648. if (_ocrdma_dealloc_pd(dev, pd))
  649. pr_err("%s: _ocrdma_dealloc_pd() failed\n", __func__);
  650. }
  651. exit:
  652. return ERR_PTR(status);
  653. }
  654. int ocrdma_dealloc_pd(struct ib_pd *ibpd)
  655. {
  656. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  657. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  658. struct ocrdma_ucontext *uctx = NULL;
  659. int status = 0;
  660. u64 usr_db;
  661. uctx = pd->uctx;
  662. if (uctx) {
  663. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  664. (pd->id * PAGE_SIZE);
  665. if (pd->dpp_enabled)
  666. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  667. usr_db = ocrdma_get_db_addr(dev, pd->id);
  668. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  669. if (is_ucontext_pd(uctx, pd)) {
  670. ocrdma_release_ucontext_pd(uctx);
  671. return status;
  672. }
  673. }
  674. status = _ocrdma_dealloc_pd(dev, pd);
  675. return status;
  676. }
  677. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  678. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  679. {
  680. int status;
  681. mr->hwmr.fr_mr = 0;
  682. mr->hwmr.local_rd = 1;
  683. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  684. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  685. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  686. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  687. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  688. mr->hwmr.num_pbls = num_pbls;
  689. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  690. if (status)
  691. return status;
  692. mr->ibmr.lkey = mr->hwmr.lkey;
  693. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  694. mr->ibmr.rkey = mr->hwmr.lkey;
  695. return 0;
  696. }
  697. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  698. {
  699. int status;
  700. struct ocrdma_mr *mr;
  701. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  702. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  703. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  704. pr_err("%s err, invalid access rights\n", __func__);
  705. return ERR_PTR(-EINVAL);
  706. }
  707. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  708. if (!mr)
  709. return ERR_PTR(-ENOMEM);
  710. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  711. OCRDMA_ADDR_CHECK_DISABLE);
  712. if (status) {
  713. kfree(mr);
  714. return ERR_PTR(status);
  715. }
  716. return &mr->ibmr;
  717. }
  718. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  719. struct ocrdma_hw_mr *mr)
  720. {
  721. struct pci_dev *pdev = dev->nic_info.pdev;
  722. int i = 0;
  723. if (mr->pbl_table) {
  724. for (i = 0; i < mr->num_pbls; i++) {
  725. if (!mr->pbl_table[i].va)
  726. continue;
  727. dma_free_coherent(&pdev->dev, mr->pbl_size,
  728. mr->pbl_table[i].va,
  729. mr->pbl_table[i].pa);
  730. }
  731. kfree(mr->pbl_table);
  732. mr->pbl_table = NULL;
  733. }
  734. }
  735. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  736. u32 num_pbes)
  737. {
  738. u32 num_pbls = 0;
  739. u32 idx = 0;
  740. int status = 0;
  741. u32 pbl_size;
  742. do {
  743. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  744. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  745. status = -EFAULT;
  746. break;
  747. }
  748. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  749. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  750. idx++;
  751. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  752. mr->hwmr.num_pbes = num_pbes;
  753. mr->hwmr.num_pbls = num_pbls;
  754. mr->hwmr.pbl_size = pbl_size;
  755. return status;
  756. }
  757. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  758. {
  759. int status = 0;
  760. int i;
  761. u32 dma_len = mr->pbl_size;
  762. struct pci_dev *pdev = dev->nic_info.pdev;
  763. void *va;
  764. dma_addr_t pa;
  765. mr->pbl_table = kzalloc(sizeof(struct ocrdma_pbl) *
  766. mr->num_pbls, GFP_KERNEL);
  767. if (!mr->pbl_table)
  768. return -ENOMEM;
  769. for (i = 0; i < mr->num_pbls; i++) {
  770. va = dma_alloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  771. if (!va) {
  772. ocrdma_free_mr_pbl_tbl(dev, mr);
  773. status = -ENOMEM;
  774. break;
  775. }
  776. memset(va, 0, dma_len);
  777. mr->pbl_table[i].va = va;
  778. mr->pbl_table[i].pa = pa;
  779. }
  780. return status;
  781. }
  782. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  783. u32 num_pbes)
  784. {
  785. struct ocrdma_pbe *pbe;
  786. struct scatterlist *sg;
  787. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  788. struct ib_umem *umem = mr->umem;
  789. int shift, pg_cnt, pages, pbe_cnt, entry, total_num_pbes = 0;
  790. if (!mr->hwmr.num_pbes)
  791. return;
  792. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  793. pbe_cnt = 0;
  794. shift = umem->page_shift;
  795. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  796. pages = sg_dma_len(sg) >> shift;
  797. for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
  798. /* store the page address in pbe */
  799. pbe->pa_lo =
  800. cpu_to_le32(sg_dma_address(sg) +
  801. (pg_cnt << shift));
  802. pbe->pa_hi =
  803. cpu_to_le32(upper_32_bits(sg_dma_address(sg) +
  804. (pg_cnt << shift)));
  805. pbe_cnt += 1;
  806. total_num_pbes += 1;
  807. pbe++;
  808. /* if done building pbes, issue the mbx cmd. */
  809. if (total_num_pbes == num_pbes)
  810. return;
  811. /* if the given pbl is full storing the pbes,
  812. * move to next pbl.
  813. */
  814. if (pbe_cnt ==
  815. (mr->hwmr.pbl_size / sizeof(u64))) {
  816. pbl_tbl++;
  817. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  818. pbe_cnt = 0;
  819. }
  820. }
  821. }
  822. }
  823. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  824. u64 usr_addr, int acc, struct ib_udata *udata)
  825. {
  826. int status = -ENOMEM;
  827. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  828. struct ocrdma_mr *mr;
  829. struct ocrdma_pd *pd;
  830. u32 num_pbes;
  831. pd = get_ocrdma_pd(ibpd);
  832. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  833. return ERR_PTR(-EINVAL);
  834. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  835. if (!mr)
  836. return ERR_PTR(status);
  837. mr->umem = ib_umem_get(ibpd->uobject->context, start, len, acc, 0);
  838. if (IS_ERR(mr->umem)) {
  839. status = -EFAULT;
  840. goto umem_err;
  841. }
  842. num_pbes = ib_umem_page_count(mr->umem);
  843. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  844. if (status)
  845. goto umem_err;
  846. mr->hwmr.pbe_size = BIT(mr->umem->page_shift);
  847. mr->hwmr.fbo = ib_umem_offset(mr->umem);
  848. mr->hwmr.va = usr_addr;
  849. mr->hwmr.len = len;
  850. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  851. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  852. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  853. mr->hwmr.local_rd = 1;
  854. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  855. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  856. if (status)
  857. goto umem_err;
  858. build_user_pbes(dev, mr, num_pbes);
  859. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  860. if (status)
  861. goto mbx_err;
  862. mr->ibmr.lkey = mr->hwmr.lkey;
  863. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  864. mr->ibmr.rkey = mr->hwmr.lkey;
  865. return &mr->ibmr;
  866. mbx_err:
  867. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  868. umem_err:
  869. kfree(mr);
  870. return ERR_PTR(status);
  871. }
  872. int ocrdma_dereg_mr(struct ib_mr *ib_mr)
  873. {
  874. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  875. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  876. (void) ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  877. kfree(mr->pages);
  878. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  879. /* it could be user registered memory. */
  880. if (mr->umem)
  881. ib_umem_release(mr->umem);
  882. kfree(mr);
  883. /* Don't stop cleanup, in case FW is unresponsive */
  884. if (dev->mqe_ctx.fw_error_state) {
  885. pr_err("%s(%d) fw not responding.\n",
  886. __func__, dev->id);
  887. }
  888. return 0;
  889. }
  890. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  891. struct ib_udata *udata,
  892. struct ib_ucontext *ib_ctx)
  893. {
  894. int status;
  895. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  896. struct ocrdma_create_cq_uresp uresp;
  897. memset(&uresp, 0, sizeof(uresp));
  898. uresp.cq_id = cq->id;
  899. uresp.page_size = PAGE_ALIGN(cq->len);
  900. uresp.num_pages = 1;
  901. uresp.max_hw_cqe = cq->max_hw_cqe;
  902. uresp.page_addr[0] = virt_to_phys(cq->va);
  903. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  904. uresp.db_page_size = dev->nic_info.db_page_size;
  905. uresp.phase_change = cq->phase_change ? 1 : 0;
  906. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  907. if (status) {
  908. pr_err("%s(%d) copy error cqid=0x%x.\n",
  909. __func__, dev->id, cq->id);
  910. goto err;
  911. }
  912. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  913. if (status)
  914. goto err;
  915. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  916. if (status) {
  917. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  918. goto err;
  919. }
  920. cq->ucontext = uctx;
  921. err:
  922. return status;
  923. }
  924. struct ib_cq *ocrdma_create_cq(struct ib_device *ibdev,
  925. const struct ib_cq_init_attr *attr,
  926. struct ib_ucontext *ib_ctx,
  927. struct ib_udata *udata)
  928. {
  929. int entries = attr->cqe;
  930. struct ocrdma_cq *cq;
  931. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  932. struct ocrdma_ucontext *uctx = NULL;
  933. u16 pd_id = 0;
  934. int status;
  935. struct ocrdma_create_cq_ureq ureq;
  936. if (attr->flags)
  937. return ERR_PTR(-EINVAL);
  938. if (udata) {
  939. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  940. return ERR_PTR(-EFAULT);
  941. } else
  942. ureq.dpp_cq = 0;
  943. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  944. if (!cq)
  945. return ERR_PTR(-ENOMEM);
  946. spin_lock_init(&cq->cq_lock);
  947. spin_lock_init(&cq->comp_handler_lock);
  948. INIT_LIST_HEAD(&cq->sq_head);
  949. INIT_LIST_HEAD(&cq->rq_head);
  950. if (ib_ctx) {
  951. uctx = get_ocrdma_ucontext(ib_ctx);
  952. pd_id = uctx->cntxt_pd->id;
  953. }
  954. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  955. if (status) {
  956. kfree(cq);
  957. return ERR_PTR(status);
  958. }
  959. if (ib_ctx) {
  960. status = ocrdma_copy_cq_uresp(dev, cq, udata, ib_ctx);
  961. if (status)
  962. goto ctx_err;
  963. }
  964. cq->phase = OCRDMA_CQE_VALID;
  965. dev->cq_tbl[cq->id] = cq;
  966. return &cq->ibcq;
  967. ctx_err:
  968. ocrdma_mbx_destroy_cq(dev, cq);
  969. kfree(cq);
  970. return ERR_PTR(status);
  971. }
  972. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  973. struct ib_udata *udata)
  974. {
  975. int status = 0;
  976. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  977. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  978. status = -EINVAL;
  979. return status;
  980. }
  981. ibcq->cqe = new_cnt;
  982. return status;
  983. }
  984. static void ocrdma_flush_cq(struct ocrdma_cq *cq)
  985. {
  986. int cqe_cnt;
  987. int valid_count = 0;
  988. unsigned long flags;
  989. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  990. struct ocrdma_cqe *cqe = NULL;
  991. cqe = cq->va;
  992. cqe_cnt = cq->cqe_cnt;
  993. /* Last irq might have scheduled a polling thread
  994. * sync-up with it before hard flushing.
  995. */
  996. spin_lock_irqsave(&cq->cq_lock, flags);
  997. while (cqe_cnt) {
  998. if (is_cqe_valid(cq, cqe))
  999. valid_count++;
  1000. cqe++;
  1001. cqe_cnt--;
  1002. }
  1003. ocrdma_ring_cq_db(dev, cq->id, false, false, valid_count);
  1004. spin_unlock_irqrestore(&cq->cq_lock, flags);
  1005. }
  1006. int ocrdma_destroy_cq(struct ib_cq *ibcq)
  1007. {
  1008. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  1009. struct ocrdma_eq *eq = NULL;
  1010. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  1011. int pdid = 0;
  1012. u32 irq, indx;
  1013. dev->cq_tbl[cq->id] = NULL;
  1014. indx = ocrdma_get_eq_table_index(dev, cq->eqn);
  1015. BUG_ON(indx == -EINVAL);
  1016. eq = &dev->eq_tbl[indx];
  1017. irq = ocrdma_get_irq(dev, eq);
  1018. synchronize_irq(irq);
  1019. ocrdma_flush_cq(cq);
  1020. (void)ocrdma_mbx_destroy_cq(dev, cq);
  1021. if (cq->ucontext) {
  1022. pdid = cq->ucontext->cntxt_pd->id;
  1023. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  1024. PAGE_ALIGN(cq->len));
  1025. ocrdma_del_mmap(cq->ucontext,
  1026. ocrdma_get_db_addr(dev, pdid),
  1027. dev->nic_info.db_page_size);
  1028. }
  1029. kfree(cq);
  1030. return 0;
  1031. }
  1032. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  1033. {
  1034. int status = -EINVAL;
  1035. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  1036. dev->qp_tbl[qp->id] = qp;
  1037. status = 0;
  1038. }
  1039. return status;
  1040. }
  1041. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  1042. {
  1043. dev->qp_tbl[qp->id] = NULL;
  1044. }
  1045. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  1046. struct ib_qp_init_attr *attrs)
  1047. {
  1048. if ((attrs->qp_type != IB_QPT_GSI) &&
  1049. (attrs->qp_type != IB_QPT_RC) &&
  1050. (attrs->qp_type != IB_QPT_UC) &&
  1051. (attrs->qp_type != IB_QPT_UD)) {
  1052. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  1053. __func__, dev->id, attrs->qp_type);
  1054. return -EINVAL;
  1055. }
  1056. /* Skip the check for QP1 to support CM size of 128 */
  1057. if ((attrs->qp_type != IB_QPT_GSI) &&
  1058. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  1059. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  1060. __func__, dev->id, attrs->cap.max_send_wr);
  1061. pr_err("%s(%d) supported send_wr=0x%x\n",
  1062. __func__, dev->id, dev->attr.max_wqe);
  1063. return -EINVAL;
  1064. }
  1065. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  1066. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  1067. __func__, dev->id, attrs->cap.max_recv_wr);
  1068. pr_err("%s(%d) supported recv_wr=0x%x\n",
  1069. __func__, dev->id, dev->attr.max_rqe);
  1070. return -EINVAL;
  1071. }
  1072. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  1073. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  1074. __func__, dev->id, attrs->cap.max_inline_data);
  1075. pr_err("%s(%d) supported inline data size=0x%x\n",
  1076. __func__, dev->id, dev->attr.max_inline_data);
  1077. return -EINVAL;
  1078. }
  1079. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  1080. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  1081. __func__, dev->id, attrs->cap.max_send_sge);
  1082. pr_err("%s(%d) supported send_sge=0x%x\n",
  1083. __func__, dev->id, dev->attr.max_send_sge);
  1084. return -EINVAL;
  1085. }
  1086. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  1087. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  1088. __func__, dev->id, attrs->cap.max_recv_sge);
  1089. pr_err("%s(%d) supported recv_sge=0x%x\n",
  1090. __func__, dev->id, dev->attr.max_recv_sge);
  1091. return -EINVAL;
  1092. }
  1093. /* unprivileged user space cannot create special QP */
  1094. if (ibpd->uobject && attrs->qp_type == IB_QPT_GSI) {
  1095. pr_err
  1096. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  1097. __func__, dev->id, attrs->qp_type);
  1098. return -EINVAL;
  1099. }
  1100. /* allow creating only one GSI type of QP */
  1101. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  1102. pr_err("%s(%d) GSI special QPs already created.\n",
  1103. __func__, dev->id);
  1104. return -EINVAL;
  1105. }
  1106. /* verify consumer QPs are not trying to use GSI QP's CQ */
  1107. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  1108. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  1109. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  1110. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  1111. __func__, dev->id);
  1112. return -EINVAL;
  1113. }
  1114. }
  1115. return 0;
  1116. }
  1117. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  1118. struct ib_udata *udata, int dpp_offset,
  1119. int dpp_credit_lmt, int srq)
  1120. {
  1121. int status;
  1122. u64 usr_db;
  1123. struct ocrdma_create_qp_uresp uresp;
  1124. struct ocrdma_pd *pd = qp->pd;
  1125. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  1126. memset(&uresp, 0, sizeof(uresp));
  1127. usr_db = dev->nic_info.unmapped_db +
  1128. (pd->id * dev->nic_info.db_page_size);
  1129. uresp.qp_id = qp->id;
  1130. uresp.sq_dbid = qp->sq.dbid;
  1131. uresp.num_sq_pages = 1;
  1132. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  1133. uresp.sq_page_addr[0] = virt_to_phys(qp->sq.va);
  1134. uresp.num_wqe_allocated = qp->sq.max_cnt;
  1135. if (!srq) {
  1136. uresp.rq_dbid = qp->rq.dbid;
  1137. uresp.num_rq_pages = 1;
  1138. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  1139. uresp.rq_page_addr[0] = virt_to_phys(qp->rq.va);
  1140. uresp.num_rqe_allocated = qp->rq.max_cnt;
  1141. }
  1142. uresp.db_page_addr = usr_db;
  1143. uresp.db_page_size = dev->nic_info.db_page_size;
  1144. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  1145. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1146. uresp.db_shift = OCRDMA_DB_RQ_SHIFT;
  1147. if (qp->dpp_enabled) {
  1148. uresp.dpp_credit = dpp_credit_lmt;
  1149. uresp.dpp_offset = dpp_offset;
  1150. }
  1151. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1152. if (status) {
  1153. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  1154. goto err;
  1155. }
  1156. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  1157. uresp.sq_page_size);
  1158. if (status)
  1159. goto err;
  1160. if (!srq) {
  1161. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  1162. uresp.rq_page_size);
  1163. if (status)
  1164. goto rq_map_err;
  1165. }
  1166. return status;
  1167. rq_map_err:
  1168. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  1169. err:
  1170. return status;
  1171. }
  1172. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  1173. struct ocrdma_pd *pd)
  1174. {
  1175. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1176. qp->sq_db = dev->nic_info.db +
  1177. (pd->id * dev->nic_info.db_page_size) +
  1178. OCRDMA_DB_GEN2_SQ_OFFSET;
  1179. qp->rq_db = dev->nic_info.db +
  1180. (pd->id * dev->nic_info.db_page_size) +
  1181. OCRDMA_DB_GEN2_RQ_OFFSET;
  1182. } else {
  1183. qp->sq_db = dev->nic_info.db +
  1184. (pd->id * dev->nic_info.db_page_size) +
  1185. OCRDMA_DB_SQ_OFFSET;
  1186. qp->rq_db = dev->nic_info.db +
  1187. (pd->id * dev->nic_info.db_page_size) +
  1188. OCRDMA_DB_RQ_OFFSET;
  1189. }
  1190. }
  1191. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1192. {
  1193. qp->wqe_wr_id_tbl =
  1194. kzalloc(sizeof(*(qp->wqe_wr_id_tbl)) * qp->sq.max_cnt,
  1195. GFP_KERNEL);
  1196. if (qp->wqe_wr_id_tbl == NULL)
  1197. return -ENOMEM;
  1198. qp->rqe_wr_id_tbl =
  1199. kzalloc(sizeof(u64) * qp->rq.max_cnt, GFP_KERNEL);
  1200. if (qp->rqe_wr_id_tbl == NULL)
  1201. return -ENOMEM;
  1202. return 0;
  1203. }
  1204. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1205. struct ocrdma_pd *pd,
  1206. struct ib_qp_init_attr *attrs)
  1207. {
  1208. qp->pd = pd;
  1209. spin_lock_init(&qp->q_lock);
  1210. INIT_LIST_HEAD(&qp->sq_entry);
  1211. INIT_LIST_HEAD(&qp->rq_entry);
  1212. qp->qp_type = attrs->qp_type;
  1213. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1214. qp->max_inline_data = attrs->cap.max_inline_data;
  1215. qp->sq.max_sges = attrs->cap.max_send_sge;
  1216. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1217. qp->state = OCRDMA_QPS_RST;
  1218. qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
  1219. }
  1220. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1221. struct ib_qp_init_attr *attrs)
  1222. {
  1223. if (attrs->qp_type == IB_QPT_GSI) {
  1224. dev->gsi_qp_created = 1;
  1225. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1226. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1227. }
  1228. }
  1229. struct ib_qp *ocrdma_create_qp(struct ib_pd *ibpd,
  1230. struct ib_qp_init_attr *attrs,
  1231. struct ib_udata *udata)
  1232. {
  1233. int status;
  1234. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1235. struct ocrdma_qp *qp;
  1236. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1237. struct ocrdma_create_qp_ureq ureq;
  1238. u16 dpp_credit_lmt, dpp_offset;
  1239. status = ocrdma_check_qp_params(ibpd, dev, attrs);
  1240. if (status)
  1241. goto gen_err;
  1242. memset(&ureq, 0, sizeof(ureq));
  1243. if (udata) {
  1244. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1245. return ERR_PTR(-EFAULT);
  1246. }
  1247. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  1248. if (!qp) {
  1249. status = -ENOMEM;
  1250. goto gen_err;
  1251. }
  1252. ocrdma_set_qp_init_params(qp, pd, attrs);
  1253. if (udata == NULL)
  1254. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1255. OCRDMA_QP_FAST_REG);
  1256. mutex_lock(&dev->dev_lock);
  1257. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1258. ureq.dpp_cq_id,
  1259. &dpp_offset, &dpp_credit_lmt);
  1260. if (status)
  1261. goto mbx_err;
  1262. /* user space QP's wr_id table are managed in library */
  1263. if (udata == NULL) {
  1264. status = ocrdma_alloc_wr_id_tbl(qp);
  1265. if (status)
  1266. goto map_err;
  1267. }
  1268. status = ocrdma_add_qpn_map(dev, qp);
  1269. if (status)
  1270. goto map_err;
  1271. ocrdma_set_qp_db(dev, qp, pd);
  1272. if (udata) {
  1273. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1274. dpp_credit_lmt,
  1275. (attrs->srq != NULL));
  1276. if (status)
  1277. goto cpy_err;
  1278. }
  1279. ocrdma_store_gsi_qp_cq(dev, attrs);
  1280. qp->ibqp.qp_num = qp->id;
  1281. mutex_unlock(&dev->dev_lock);
  1282. return &qp->ibqp;
  1283. cpy_err:
  1284. ocrdma_del_qpn_map(dev, qp);
  1285. map_err:
  1286. ocrdma_mbx_destroy_qp(dev, qp);
  1287. mbx_err:
  1288. mutex_unlock(&dev->dev_lock);
  1289. kfree(qp->wqe_wr_id_tbl);
  1290. kfree(qp->rqe_wr_id_tbl);
  1291. kfree(qp);
  1292. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1293. gen_err:
  1294. return ERR_PTR(status);
  1295. }
  1296. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1297. int attr_mask)
  1298. {
  1299. int status = 0;
  1300. struct ocrdma_qp *qp;
  1301. struct ocrdma_dev *dev;
  1302. enum ib_qp_state old_qps;
  1303. qp = get_ocrdma_qp(ibqp);
  1304. dev = get_ocrdma_dev(ibqp->device);
  1305. if (attr_mask & IB_QP_STATE)
  1306. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1307. /* if new and previous states are same hw doesn't need to
  1308. * know about it.
  1309. */
  1310. if (status < 0)
  1311. return status;
  1312. return ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask);
  1313. }
  1314. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1315. int attr_mask, struct ib_udata *udata)
  1316. {
  1317. unsigned long flags;
  1318. int status = -EINVAL;
  1319. struct ocrdma_qp *qp;
  1320. struct ocrdma_dev *dev;
  1321. enum ib_qp_state old_qps, new_qps;
  1322. qp = get_ocrdma_qp(ibqp);
  1323. dev = get_ocrdma_dev(ibqp->device);
  1324. /* syncronize with multiple context trying to change, retrive qps */
  1325. mutex_lock(&dev->dev_lock);
  1326. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1327. spin_lock_irqsave(&qp->q_lock, flags);
  1328. old_qps = get_ibqp_state(qp->state);
  1329. if (attr_mask & IB_QP_STATE)
  1330. new_qps = attr->qp_state;
  1331. else
  1332. new_qps = old_qps;
  1333. spin_unlock_irqrestore(&qp->q_lock, flags);
  1334. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask,
  1335. IB_LINK_LAYER_ETHERNET)) {
  1336. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1337. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1338. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1339. old_qps, new_qps);
  1340. goto param_err;
  1341. }
  1342. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1343. if (status > 0)
  1344. status = 0;
  1345. param_err:
  1346. mutex_unlock(&dev->dev_lock);
  1347. return status;
  1348. }
  1349. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1350. {
  1351. switch (mtu) {
  1352. case 256:
  1353. return IB_MTU_256;
  1354. case 512:
  1355. return IB_MTU_512;
  1356. case 1024:
  1357. return IB_MTU_1024;
  1358. case 2048:
  1359. return IB_MTU_2048;
  1360. case 4096:
  1361. return IB_MTU_4096;
  1362. default:
  1363. return IB_MTU_1024;
  1364. }
  1365. }
  1366. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1367. {
  1368. int ib_qp_acc_flags = 0;
  1369. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1370. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1371. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1372. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1373. return ib_qp_acc_flags;
  1374. }
  1375. int ocrdma_query_qp(struct ib_qp *ibqp,
  1376. struct ib_qp_attr *qp_attr,
  1377. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1378. {
  1379. int status;
  1380. u32 qp_state;
  1381. struct ocrdma_qp_params params;
  1382. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1383. struct ocrdma_dev *dev = get_ocrdma_dev(ibqp->device);
  1384. memset(&params, 0, sizeof(params));
  1385. mutex_lock(&dev->dev_lock);
  1386. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1387. mutex_unlock(&dev->dev_lock);
  1388. if (status)
  1389. goto mbx_err;
  1390. if (qp->qp_type == IB_QPT_UD)
  1391. qp_attr->qkey = params.qkey;
  1392. qp_attr->path_mtu =
  1393. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1394. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1395. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1396. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1397. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1398. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1399. qp_attr->dest_qp_num =
  1400. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1401. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1402. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1403. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1404. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1405. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1406. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1407. qp_init_attr->cap = qp_attr->cap;
  1408. qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
  1409. rdma_ah_set_grh(&qp_attr->ah_attr, NULL,
  1410. params.rnt_rc_sl_fl &
  1411. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK,
  1412. qp->sgid_idx,
  1413. (params.hop_lmt_rq_psn &
  1414. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1415. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
  1416. (params.tclass_sq_psn &
  1417. OCRDMA_QP_PARAMS_TCLASS_MASK) >>
  1418. OCRDMA_QP_PARAMS_TCLASS_SHIFT);
  1419. rdma_ah_set_dgid_raw(&qp_attr->ah_attr, &params.dgid[0]);
  1420. rdma_ah_set_port_num(&qp_attr->ah_attr, 1);
  1421. rdma_ah_set_sl(&qp_attr->ah_attr, (params.rnt_rc_sl_fl &
  1422. OCRDMA_QP_PARAMS_SL_MASK) >>
  1423. OCRDMA_QP_PARAMS_SL_SHIFT);
  1424. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1425. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1426. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1427. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1428. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1429. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1430. qp_attr->retry_cnt =
  1431. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1432. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1433. qp_attr->min_rnr_timer = 0;
  1434. qp_attr->pkey_index = 0;
  1435. qp_attr->port_num = 1;
  1436. rdma_ah_set_path_bits(&qp_attr->ah_attr, 0);
  1437. rdma_ah_set_static_rate(&qp_attr->ah_attr, 0);
  1438. qp_attr->alt_pkey_index = 0;
  1439. qp_attr->alt_port_num = 0;
  1440. qp_attr->alt_timeout = 0;
  1441. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1442. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1443. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1444. qp_attr->qp_state = get_ibqp_state(qp_state);
  1445. qp_attr->cur_qp_state = qp_attr->qp_state;
  1446. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1447. qp_attr->max_dest_rd_atomic =
  1448. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1449. qp_attr->max_rd_atomic =
  1450. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1451. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1452. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1453. /* Sync driver QP state with FW */
  1454. ocrdma_qp_state_change(qp, qp_attr->qp_state, NULL);
  1455. mbx_err:
  1456. return status;
  1457. }
  1458. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, unsigned int idx)
  1459. {
  1460. unsigned int i = idx / 32;
  1461. u32 mask = (1U << (idx % 32));
  1462. srq->idx_bit_fields[i] ^= mask;
  1463. }
  1464. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1465. {
  1466. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1467. }
  1468. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1469. {
  1470. return (qp->sq.tail == qp->sq.head);
  1471. }
  1472. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1473. {
  1474. return (qp->rq.tail == qp->rq.head);
  1475. }
  1476. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1477. {
  1478. return q->va + (q->head * q->entry_size);
  1479. }
  1480. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1481. u32 idx)
  1482. {
  1483. return q->va + (idx * q->entry_size);
  1484. }
  1485. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1486. {
  1487. q->head = (q->head + 1) & q->max_wqe_idx;
  1488. }
  1489. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1490. {
  1491. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1492. }
  1493. /* discard the cqe for a given QP */
  1494. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1495. {
  1496. unsigned long cq_flags;
  1497. unsigned long flags;
  1498. int discard_cnt = 0;
  1499. u32 cur_getp, stop_getp;
  1500. struct ocrdma_cqe *cqe;
  1501. u32 qpn = 0, wqe_idx = 0;
  1502. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1503. /* traverse through the CQEs in the hw CQ,
  1504. * find the matching CQE for a given qp,
  1505. * mark the matching one discarded by clearing qpn.
  1506. * ring the doorbell in the poll_cq() as
  1507. * we don't complete out of order cqe.
  1508. */
  1509. cur_getp = cq->getp;
  1510. /* find upto when do we reap the cq. */
  1511. stop_getp = cur_getp;
  1512. do {
  1513. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1514. break;
  1515. cqe = cq->va + cur_getp;
  1516. /* if (a) done reaping whole hw cq, or
  1517. * (b) qp_xq becomes empty.
  1518. * then exit
  1519. */
  1520. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1521. /* if previously discarded cqe found, skip that too. */
  1522. /* check for matching qp */
  1523. if (qpn == 0 || qpn != qp->id)
  1524. goto skip_cqe;
  1525. if (is_cqe_for_sq(cqe)) {
  1526. ocrdma_hwq_inc_tail(&qp->sq);
  1527. } else {
  1528. if (qp->srq) {
  1529. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  1530. OCRDMA_CQE_BUFTAG_SHIFT) &
  1531. qp->srq->rq.max_wqe_idx;
  1532. BUG_ON(wqe_idx < 1);
  1533. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1534. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1535. ocrdma_srq_toggle_bit(qp->srq, wqe_idx - 1);
  1536. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1537. } else {
  1538. ocrdma_hwq_inc_tail(&qp->rq);
  1539. }
  1540. }
  1541. /* mark cqe discarded so that it is not picked up later
  1542. * in the poll_cq().
  1543. */
  1544. discard_cnt += 1;
  1545. cqe->cmn.qpn = 0;
  1546. skip_cqe:
  1547. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1548. } while (cur_getp != stop_getp);
  1549. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1550. }
  1551. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1552. {
  1553. int found = false;
  1554. unsigned long flags;
  1555. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1556. /* sync with any active CQ poll */
  1557. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1558. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1559. if (found)
  1560. list_del(&qp->sq_entry);
  1561. if (!qp->srq) {
  1562. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1563. if (found)
  1564. list_del(&qp->rq_entry);
  1565. }
  1566. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1567. }
  1568. int ocrdma_destroy_qp(struct ib_qp *ibqp)
  1569. {
  1570. struct ocrdma_pd *pd;
  1571. struct ocrdma_qp *qp;
  1572. struct ocrdma_dev *dev;
  1573. struct ib_qp_attr attrs;
  1574. int attr_mask;
  1575. unsigned long flags;
  1576. qp = get_ocrdma_qp(ibqp);
  1577. dev = get_ocrdma_dev(ibqp->device);
  1578. pd = qp->pd;
  1579. /* change the QP state to ERROR */
  1580. if (qp->state != OCRDMA_QPS_RST) {
  1581. attrs.qp_state = IB_QPS_ERR;
  1582. attr_mask = IB_QP_STATE;
  1583. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1584. }
  1585. /* ensure that CQEs for newly created QP (whose id may be same with
  1586. * one which just getting destroyed are same), dont get
  1587. * discarded until the old CQEs are discarded.
  1588. */
  1589. mutex_lock(&dev->dev_lock);
  1590. (void) ocrdma_mbx_destroy_qp(dev, qp);
  1591. /*
  1592. * acquire CQ lock while destroy is in progress, in order to
  1593. * protect against proessing in-flight CQEs for this QP.
  1594. */
  1595. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1596. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1597. spin_lock(&qp->rq_cq->cq_lock);
  1598. ocrdma_del_qpn_map(dev, qp);
  1599. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1600. spin_unlock(&qp->rq_cq->cq_lock);
  1601. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1602. if (!pd->uctx) {
  1603. ocrdma_discard_cqes(qp, qp->sq_cq);
  1604. ocrdma_discard_cqes(qp, qp->rq_cq);
  1605. }
  1606. mutex_unlock(&dev->dev_lock);
  1607. if (pd->uctx) {
  1608. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1609. PAGE_ALIGN(qp->sq.len));
  1610. if (!qp->srq)
  1611. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1612. PAGE_ALIGN(qp->rq.len));
  1613. }
  1614. ocrdma_del_flush_qp(qp);
  1615. kfree(qp->wqe_wr_id_tbl);
  1616. kfree(qp->rqe_wr_id_tbl);
  1617. kfree(qp);
  1618. return 0;
  1619. }
  1620. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1621. struct ib_udata *udata)
  1622. {
  1623. int status;
  1624. struct ocrdma_create_srq_uresp uresp;
  1625. memset(&uresp, 0, sizeof(uresp));
  1626. uresp.rq_dbid = srq->rq.dbid;
  1627. uresp.num_rq_pages = 1;
  1628. uresp.rq_page_addr[0] = virt_to_phys(srq->rq.va);
  1629. uresp.rq_page_size = srq->rq.len;
  1630. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1631. (srq->pd->id * dev->nic_info.db_page_size);
  1632. uresp.db_page_size = dev->nic_info.db_page_size;
  1633. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1634. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1635. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1636. uresp.db_shift = 24;
  1637. } else {
  1638. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1639. uresp.db_shift = 16;
  1640. }
  1641. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1642. if (status)
  1643. return status;
  1644. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1645. uresp.rq_page_size);
  1646. if (status)
  1647. return status;
  1648. return status;
  1649. }
  1650. struct ib_srq *ocrdma_create_srq(struct ib_pd *ibpd,
  1651. struct ib_srq_init_attr *init_attr,
  1652. struct ib_udata *udata)
  1653. {
  1654. int status = -ENOMEM;
  1655. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1656. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1657. struct ocrdma_srq *srq;
  1658. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1659. return ERR_PTR(-EINVAL);
  1660. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1661. return ERR_PTR(-EINVAL);
  1662. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1663. if (!srq)
  1664. return ERR_PTR(status);
  1665. spin_lock_init(&srq->q_lock);
  1666. srq->pd = pd;
  1667. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1668. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1669. if (status)
  1670. goto err;
  1671. if (udata == NULL) {
  1672. status = -ENOMEM;
  1673. srq->rqe_wr_id_tbl = kzalloc(sizeof(u64) * srq->rq.max_cnt,
  1674. GFP_KERNEL);
  1675. if (srq->rqe_wr_id_tbl == NULL)
  1676. goto arm_err;
  1677. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1678. (srq->rq.max_cnt % 32 ? 1 : 0);
  1679. srq->idx_bit_fields =
  1680. kmalloc(srq->bit_fields_len * sizeof(u32), GFP_KERNEL);
  1681. if (srq->idx_bit_fields == NULL)
  1682. goto arm_err;
  1683. memset(srq->idx_bit_fields, 0xff,
  1684. srq->bit_fields_len * sizeof(u32));
  1685. }
  1686. if (init_attr->attr.srq_limit) {
  1687. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1688. if (status)
  1689. goto arm_err;
  1690. }
  1691. if (udata) {
  1692. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1693. if (status)
  1694. goto arm_err;
  1695. }
  1696. return &srq->ibsrq;
  1697. arm_err:
  1698. ocrdma_mbx_destroy_srq(dev, srq);
  1699. err:
  1700. kfree(srq->rqe_wr_id_tbl);
  1701. kfree(srq->idx_bit_fields);
  1702. kfree(srq);
  1703. return ERR_PTR(status);
  1704. }
  1705. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1706. struct ib_srq_attr *srq_attr,
  1707. enum ib_srq_attr_mask srq_attr_mask,
  1708. struct ib_udata *udata)
  1709. {
  1710. int status;
  1711. struct ocrdma_srq *srq;
  1712. srq = get_ocrdma_srq(ibsrq);
  1713. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1714. status = -EINVAL;
  1715. else
  1716. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1717. return status;
  1718. }
  1719. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1720. {
  1721. int status;
  1722. struct ocrdma_srq *srq;
  1723. srq = get_ocrdma_srq(ibsrq);
  1724. status = ocrdma_mbx_query_srq(srq, srq_attr);
  1725. return status;
  1726. }
  1727. int ocrdma_destroy_srq(struct ib_srq *ibsrq)
  1728. {
  1729. int status;
  1730. struct ocrdma_srq *srq;
  1731. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1732. srq = get_ocrdma_srq(ibsrq);
  1733. status = ocrdma_mbx_destroy_srq(dev, srq);
  1734. if (srq->pd->uctx)
  1735. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1736. PAGE_ALIGN(srq->rq.len));
  1737. kfree(srq->idx_bit_fields);
  1738. kfree(srq->rqe_wr_id_tbl);
  1739. kfree(srq);
  1740. return status;
  1741. }
  1742. /* unprivileged verbs and their support functions. */
  1743. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1744. struct ocrdma_hdr_wqe *hdr,
  1745. struct ib_send_wr *wr)
  1746. {
  1747. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1748. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1749. struct ocrdma_ah *ah = get_ocrdma_ah(ud_wr(wr)->ah);
  1750. ud_hdr->rsvd_dest_qpn = ud_wr(wr)->remote_qpn;
  1751. if (qp->qp_type == IB_QPT_GSI)
  1752. ud_hdr->qkey = qp->qkey;
  1753. else
  1754. ud_hdr->qkey = ud_wr(wr)->remote_qkey;
  1755. ud_hdr->rsvd_ahid = ah->id;
  1756. ud_hdr->hdr_type = ah->hdr_type;
  1757. if (ah->av->valid & OCRDMA_AV_VLAN_VALID)
  1758. hdr->cw |= (OCRDMA_FLAG_AH_VLAN_PR << OCRDMA_WQE_FLAGS_SHIFT);
  1759. }
  1760. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1761. struct ocrdma_sge *sge, int num_sge,
  1762. struct ib_sge *sg_list)
  1763. {
  1764. int i;
  1765. for (i = 0; i < num_sge; i++) {
  1766. sge[i].lrkey = sg_list[i].lkey;
  1767. sge[i].addr_lo = sg_list[i].addr;
  1768. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1769. sge[i].len = sg_list[i].length;
  1770. hdr->total_len += sg_list[i].length;
  1771. }
  1772. if (num_sge == 0)
  1773. memset(sge, 0, sizeof(*sge));
  1774. }
  1775. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1776. {
  1777. uint32_t total_len = 0, i;
  1778. for (i = 0; i < num_sge; i++)
  1779. total_len += sg_list[i].length;
  1780. return total_len;
  1781. }
  1782. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1783. struct ocrdma_hdr_wqe *hdr,
  1784. struct ocrdma_sge *sge,
  1785. struct ib_send_wr *wr, u32 wqe_size)
  1786. {
  1787. int i;
  1788. char *dpp_addr;
  1789. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1790. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1791. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1792. pr_err("%s() supported_len=0x%x,\n"
  1793. " unsupported len req=0x%x\n", __func__,
  1794. qp->max_inline_data, hdr->total_len);
  1795. return -EINVAL;
  1796. }
  1797. dpp_addr = (char *)sge;
  1798. for (i = 0; i < wr->num_sge; i++) {
  1799. memcpy(dpp_addr,
  1800. (void *)(unsigned long)wr->sg_list[i].addr,
  1801. wr->sg_list[i].length);
  1802. dpp_addr += wr->sg_list[i].length;
  1803. }
  1804. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1805. if (0 == hdr->total_len)
  1806. wqe_size += sizeof(struct ocrdma_sge);
  1807. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1808. } else {
  1809. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1810. if (wr->num_sge)
  1811. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1812. else
  1813. wqe_size += sizeof(struct ocrdma_sge);
  1814. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1815. }
  1816. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1817. return 0;
  1818. }
  1819. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1820. struct ib_send_wr *wr)
  1821. {
  1822. int status;
  1823. struct ocrdma_sge *sge;
  1824. u32 wqe_size = sizeof(*hdr);
  1825. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1826. ocrdma_build_ud_hdr(qp, hdr, wr);
  1827. sge = (struct ocrdma_sge *)(hdr + 2);
  1828. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1829. } else {
  1830. sge = (struct ocrdma_sge *)(hdr + 1);
  1831. }
  1832. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1833. return status;
  1834. }
  1835. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1836. struct ib_send_wr *wr)
  1837. {
  1838. int status;
  1839. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1840. struct ocrdma_sge *sge = ext_rw + 1;
  1841. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1842. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1843. if (status)
  1844. return status;
  1845. ext_rw->addr_lo = rdma_wr(wr)->remote_addr;
  1846. ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr);
  1847. ext_rw->lrkey = rdma_wr(wr)->rkey;
  1848. ext_rw->len = hdr->total_len;
  1849. return 0;
  1850. }
  1851. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1852. struct ib_send_wr *wr)
  1853. {
  1854. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1855. struct ocrdma_sge *sge = ext_rw + 1;
  1856. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1857. sizeof(struct ocrdma_hdr_wqe);
  1858. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1859. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1860. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1861. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1862. ext_rw->addr_lo = rdma_wr(wr)->remote_addr;
  1863. ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr);
  1864. ext_rw->lrkey = rdma_wr(wr)->rkey;
  1865. ext_rw->len = hdr->total_len;
  1866. }
  1867. static int get_encoded_page_size(int pg_sz)
  1868. {
  1869. /* Max size is 256M 4096 << 16 */
  1870. int i = 0;
  1871. for (; i < 17; i++)
  1872. if (pg_sz == (4096 << i))
  1873. break;
  1874. return i;
  1875. }
  1876. static int ocrdma_build_reg(struct ocrdma_qp *qp,
  1877. struct ocrdma_hdr_wqe *hdr,
  1878. struct ib_reg_wr *wr)
  1879. {
  1880. u64 fbo;
  1881. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1882. struct ocrdma_mr *mr = get_ocrdma_mr(wr->mr);
  1883. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  1884. struct ocrdma_pbe *pbe;
  1885. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1886. int num_pbes = 0, i;
  1887. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1888. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1889. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1890. if (wr->access & IB_ACCESS_LOCAL_WRITE)
  1891. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1892. if (wr->access & IB_ACCESS_REMOTE_WRITE)
  1893. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1894. if (wr->access & IB_ACCESS_REMOTE_READ)
  1895. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1896. hdr->lkey = wr->key;
  1897. hdr->total_len = mr->ibmr.length;
  1898. fbo = mr->ibmr.iova - mr->pages[0];
  1899. fast_reg->va_hi = upper_32_bits(mr->ibmr.iova);
  1900. fast_reg->va_lo = (u32) (mr->ibmr.iova & 0xffffffff);
  1901. fast_reg->fbo_hi = upper_32_bits(fbo);
  1902. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1903. fast_reg->num_sges = mr->npages;
  1904. fast_reg->size_sge = get_encoded_page_size(mr->ibmr.page_size);
  1905. pbe = pbl_tbl->va;
  1906. for (i = 0; i < mr->npages; i++) {
  1907. u64 buf_addr = mr->pages[i];
  1908. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1909. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1910. num_pbes += 1;
  1911. pbe++;
  1912. /* if the pbl is full storing the pbes,
  1913. * move to next pbl.
  1914. */
  1915. if (num_pbes == (mr->hwmr.pbl_size/sizeof(u64))) {
  1916. pbl_tbl++;
  1917. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1918. }
  1919. }
  1920. return 0;
  1921. }
  1922. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1923. {
  1924. u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT);
  1925. iowrite32(val, qp->sq_db);
  1926. }
  1927. int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  1928. struct ib_send_wr **bad_wr)
  1929. {
  1930. int status = 0;
  1931. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1932. struct ocrdma_hdr_wqe *hdr;
  1933. unsigned long flags;
  1934. spin_lock_irqsave(&qp->q_lock, flags);
  1935. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1936. spin_unlock_irqrestore(&qp->q_lock, flags);
  1937. *bad_wr = wr;
  1938. return -EINVAL;
  1939. }
  1940. while (wr) {
  1941. if (qp->qp_type == IB_QPT_UD &&
  1942. (wr->opcode != IB_WR_SEND &&
  1943. wr->opcode != IB_WR_SEND_WITH_IMM)) {
  1944. *bad_wr = wr;
  1945. status = -EINVAL;
  1946. break;
  1947. }
  1948. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1949. wr->num_sge > qp->sq.max_sges) {
  1950. *bad_wr = wr;
  1951. status = -ENOMEM;
  1952. break;
  1953. }
  1954. hdr = ocrdma_hwq_head(&qp->sq);
  1955. hdr->cw = 0;
  1956. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1957. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1958. if (wr->send_flags & IB_SEND_FENCE)
  1959. hdr->cw |=
  1960. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1961. if (wr->send_flags & IB_SEND_SOLICITED)
  1962. hdr->cw |=
  1963. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1964. hdr->total_len = 0;
  1965. switch (wr->opcode) {
  1966. case IB_WR_SEND_WITH_IMM:
  1967. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1968. hdr->immdt = ntohl(wr->ex.imm_data);
  1969. case IB_WR_SEND:
  1970. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1971. ocrdma_build_send(qp, hdr, wr);
  1972. break;
  1973. case IB_WR_SEND_WITH_INV:
  1974. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1975. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1976. hdr->lkey = wr->ex.invalidate_rkey;
  1977. status = ocrdma_build_send(qp, hdr, wr);
  1978. break;
  1979. case IB_WR_RDMA_WRITE_WITH_IMM:
  1980. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1981. hdr->immdt = ntohl(wr->ex.imm_data);
  1982. case IB_WR_RDMA_WRITE:
  1983. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  1984. status = ocrdma_build_write(qp, hdr, wr);
  1985. break;
  1986. case IB_WR_RDMA_READ:
  1987. ocrdma_build_read(qp, hdr, wr);
  1988. break;
  1989. case IB_WR_LOCAL_INV:
  1990. hdr->cw |=
  1991. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  1992. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  1993. sizeof(struct ocrdma_sge)) /
  1994. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  1995. hdr->lkey = wr->ex.invalidate_rkey;
  1996. break;
  1997. case IB_WR_REG_MR:
  1998. status = ocrdma_build_reg(qp, hdr, reg_wr(wr));
  1999. break;
  2000. default:
  2001. status = -EINVAL;
  2002. break;
  2003. }
  2004. if (status) {
  2005. *bad_wr = wr;
  2006. break;
  2007. }
  2008. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  2009. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  2010. else
  2011. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  2012. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  2013. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  2014. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  2015. /* make sure wqe is written before adapter can access it */
  2016. wmb();
  2017. /* inform hw to start processing it */
  2018. ocrdma_ring_sq_db(qp);
  2019. /* update pointer, counter for next wr */
  2020. ocrdma_hwq_inc_head(&qp->sq);
  2021. wr = wr->next;
  2022. }
  2023. spin_unlock_irqrestore(&qp->q_lock, flags);
  2024. return status;
  2025. }
  2026. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  2027. {
  2028. u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT);
  2029. iowrite32(val, qp->rq_db);
  2030. }
  2031. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe, struct ib_recv_wr *wr,
  2032. u16 tag)
  2033. {
  2034. u32 wqe_size = 0;
  2035. struct ocrdma_sge *sge;
  2036. if (wr->num_sge)
  2037. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  2038. else
  2039. wqe_size = sizeof(*sge) + sizeof(*rqe);
  2040. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  2041. OCRDMA_WQE_SIZE_SHIFT);
  2042. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  2043. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  2044. rqe->total_len = 0;
  2045. rqe->rsvd_tag = tag;
  2046. sge = (struct ocrdma_sge *)(rqe + 1);
  2047. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  2048. ocrdma_cpu_to_le32(rqe, wqe_size);
  2049. }
  2050. int ocrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  2051. struct ib_recv_wr **bad_wr)
  2052. {
  2053. int status = 0;
  2054. unsigned long flags;
  2055. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  2056. struct ocrdma_hdr_wqe *rqe;
  2057. spin_lock_irqsave(&qp->q_lock, flags);
  2058. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  2059. spin_unlock_irqrestore(&qp->q_lock, flags);
  2060. *bad_wr = wr;
  2061. return -EINVAL;
  2062. }
  2063. while (wr) {
  2064. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  2065. wr->num_sge > qp->rq.max_sges) {
  2066. *bad_wr = wr;
  2067. status = -ENOMEM;
  2068. break;
  2069. }
  2070. rqe = ocrdma_hwq_head(&qp->rq);
  2071. ocrdma_build_rqe(rqe, wr, 0);
  2072. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  2073. /* make sure rqe is written before adapter can access it */
  2074. wmb();
  2075. /* inform hw to start processing it */
  2076. ocrdma_ring_rq_db(qp);
  2077. /* update pointer, counter for next wr */
  2078. ocrdma_hwq_inc_head(&qp->rq);
  2079. wr = wr->next;
  2080. }
  2081. spin_unlock_irqrestore(&qp->q_lock, flags);
  2082. return status;
  2083. }
  2084. /* cqe for srq's rqe can potentially arrive out of order.
  2085. * index gives the entry in the shadow table where to store
  2086. * the wr_id. tag/index is returned in cqe to reference back
  2087. * for a given rqe.
  2088. */
  2089. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  2090. {
  2091. int row = 0;
  2092. int indx = 0;
  2093. for (row = 0; row < srq->bit_fields_len; row++) {
  2094. if (srq->idx_bit_fields[row]) {
  2095. indx = ffs(srq->idx_bit_fields[row]);
  2096. indx = (row * 32) + (indx - 1);
  2097. BUG_ON(indx >= srq->rq.max_cnt);
  2098. ocrdma_srq_toggle_bit(srq, indx);
  2099. break;
  2100. }
  2101. }
  2102. BUG_ON(row == srq->bit_fields_len);
  2103. return indx + 1; /* Use from index 1 */
  2104. }
  2105. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  2106. {
  2107. u32 val = srq->rq.dbid | (1 << 16);
  2108. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  2109. }
  2110. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  2111. struct ib_recv_wr **bad_wr)
  2112. {
  2113. int status = 0;
  2114. unsigned long flags;
  2115. struct ocrdma_srq *srq;
  2116. struct ocrdma_hdr_wqe *rqe;
  2117. u16 tag;
  2118. srq = get_ocrdma_srq(ibsrq);
  2119. spin_lock_irqsave(&srq->q_lock, flags);
  2120. while (wr) {
  2121. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  2122. wr->num_sge > srq->rq.max_sges) {
  2123. status = -ENOMEM;
  2124. *bad_wr = wr;
  2125. break;
  2126. }
  2127. tag = ocrdma_srq_get_idx(srq);
  2128. rqe = ocrdma_hwq_head(&srq->rq);
  2129. ocrdma_build_rqe(rqe, wr, tag);
  2130. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  2131. /* make sure rqe is written before adapter can perform DMA */
  2132. wmb();
  2133. /* inform hw to start processing it */
  2134. ocrdma_ring_srq_db(srq);
  2135. /* update pointer, counter for next wr */
  2136. ocrdma_hwq_inc_head(&srq->rq);
  2137. wr = wr->next;
  2138. }
  2139. spin_unlock_irqrestore(&srq->q_lock, flags);
  2140. return status;
  2141. }
  2142. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  2143. {
  2144. enum ib_wc_status ibwc_status;
  2145. switch (status) {
  2146. case OCRDMA_CQE_GENERAL_ERR:
  2147. ibwc_status = IB_WC_GENERAL_ERR;
  2148. break;
  2149. case OCRDMA_CQE_LOC_LEN_ERR:
  2150. ibwc_status = IB_WC_LOC_LEN_ERR;
  2151. break;
  2152. case OCRDMA_CQE_LOC_QP_OP_ERR:
  2153. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  2154. break;
  2155. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  2156. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  2157. break;
  2158. case OCRDMA_CQE_LOC_PROT_ERR:
  2159. ibwc_status = IB_WC_LOC_PROT_ERR;
  2160. break;
  2161. case OCRDMA_CQE_WR_FLUSH_ERR:
  2162. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2163. break;
  2164. case OCRDMA_CQE_MW_BIND_ERR:
  2165. ibwc_status = IB_WC_MW_BIND_ERR;
  2166. break;
  2167. case OCRDMA_CQE_BAD_RESP_ERR:
  2168. ibwc_status = IB_WC_BAD_RESP_ERR;
  2169. break;
  2170. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2171. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2172. break;
  2173. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2174. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2175. break;
  2176. case OCRDMA_CQE_REM_ACCESS_ERR:
  2177. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2178. break;
  2179. case OCRDMA_CQE_REM_OP_ERR:
  2180. ibwc_status = IB_WC_REM_OP_ERR;
  2181. break;
  2182. case OCRDMA_CQE_RETRY_EXC_ERR:
  2183. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2184. break;
  2185. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2186. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2187. break;
  2188. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2189. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2190. break;
  2191. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2192. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2193. break;
  2194. case OCRDMA_CQE_REM_ABORT_ERR:
  2195. ibwc_status = IB_WC_REM_ABORT_ERR;
  2196. break;
  2197. case OCRDMA_CQE_INV_EECN_ERR:
  2198. ibwc_status = IB_WC_INV_EECN_ERR;
  2199. break;
  2200. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2201. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2202. break;
  2203. case OCRDMA_CQE_FATAL_ERR:
  2204. ibwc_status = IB_WC_FATAL_ERR;
  2205. break;
  2206. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2207. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2208. break;
  2209. default:
  2210. ibwc_status = IB_WC_GENERAL_ERR;
  2211. break;
  2212. }
  2213. return ibwc_status;
  2214. }
  2215. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2216. u32 wqe_idx)
  2217. {
  2218. struct ocrdma_hdr_wqe *hdr;
  2219. struct ocrdma_sge *rw;
  2220. int opcode;
  2221. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2222. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2223. /* Undo the hdr->cw swap */
  2224. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2225. switch (opcode) {
  2226. case OCRDMA_WRITE:
  2227. ibwc->opcode = IB_WC_RDMA_WRITE;
  2228. break;
  2229. case OCRDMA_READ:
  2230. rw = (struct ocrdma_sge *)(hdr + 1);
  2231. ibwc->opcode = IB_WC_RDMA_READ;
  2232. ibwc->byte_len = rw->len;
  2233. break;
  2234. case OCRDMA_SEND:
  2235. ibwc->opcode = IB_WC_SEND;
  2236. break;
  2237. case OCRDMA_FR_MR:
  2238. ibwc->opcode = IB_WC_REG_MR;
  2239. break;
  2240. case OCRDMA_LKEY_INV:
  2241. ibwc->opcode = IB_WC_LOCAL_INV;
  2242. break;
  2243. default:
  2244. ibwc->status = IB_WC_GENERAL_ERR;
  2245. pr_err("%s() invalid opcode received = 0x%x\n",
  2246. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2247. break;
  2248. }
  2249. }
  2250. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2251. struct ocrdma_cqe *cqe)
  2252. {
  2253. if (is_cqe_for_sq(cqe)) {
  2254. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2255. cqe->flags_status_srcqpn) &
  2256. ~OCRDMA_CQE_STATUS_MASK);
  2257. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2258. cqe->flags_status_srcqpn) |
  2259. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2260. OCRDMA_CQE_STATUS_SHIFT));
  2261. } else {
  2262. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2263. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2264. cqe->flags_status_srcqpn) &
  2265. ~OCRDMA_CQE_UD_STATUS_MASK);
  2266. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2267. cqe->flags_status_srcqpn) |
  2268. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2269. OCRDMA_CQE_UD_STATUS_SHIFT));
  2270. } else {
  2271. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2272. cqe->flags_status_srcqpn) &
  2273. ~OCRDMA_CQE_STATUS_MASK);
  2274. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2275. cqe->flags_status_srcqpn) |
  2276. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2277. OCRDMA_CQE_STATUS_SHIFT));
  2278. }
  2279. }
  2280. }
  2281. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2282. struct ocrdma_qp *qp, int status)
  2283. {
  2284. bool expand = false;
  2285. ibwc->byte_len = 0;
  2286. ibwc->qp = &qp->ibqp;
  2287. ibwc->status = ocrdma_to_ibwc_err(status);
  2288. ocrdma_flush_qp(qp);
  2289. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2290. /* if wqe/rqe pending for which cqe needs to be returned,
  2291. * trigger inflating it.
  2292. */
  2293. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2294. expand = true;
  2295. ocrdma_set_cqe_status_flushed(qp, cqe);
  2296. }
  2297. return expand;
  2298. }
  2299. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2300. struct ocrdma_qp *qp, int status)
  2301. {
  2302. ibwc->opcode = IB_WC_RECV;
  2303. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2304. ocrdma_hwq_inc_tail(&qp->rq);
  2305. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2306. }
  2307. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2308. struct ocrdma_qp *qp, int status)
  2309. {
  2310. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2311. ocrdma_hwq_inc_tail(&qp->sq);
  2312. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2313. }
  2314. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2315. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2316. bool *polled, bool *stop)
  2317. {
  2318. bool expand;
  2319. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2320. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2321. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2322. if (status < OCRDMA_MAX_CQE_ERR)
  2323. atomic_inc(&dev->cqe_err_stats[status]);
  2324. /* when hw sq is empty, but rq is not empty, so we continue
  2325. * to keep the cqe in order to get the cq event again.
  2326. */
  2327. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2328. /* when cq for rq and sq is same, it is safe to return
  2329. * flush cqe for RQEs.
  2330. */
  2331. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2332. *polled = true;
  2333. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2334. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2335. } else {
  2336. /* stop processing further cqe as this cqe is used for
  2337. * triggering cq event on buddy cq of RQ.
  2338. * When QP is destroyed, this cqe will be removed
  2339. * from the cq's hardware q.
  2340. */
  2341. *polled = false;
  2342. *stop = true;
  2343. expand = false;
  2344. }
  2345. } else if (is_hw_sq_empty(qp)) {
  2346. /* Do nothing */
  2347. expand = false;
  2348. *polled = false;
  2349. *stop = false;
  2350. } else {
  2351. *polled = true;
  2352. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2353. }
  2354. return expand;
  2355. }
  2356. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2357. struct ocrdma_cqe *cqe,
  2358. struct ib_wc *ibwc, bool *polled)
  2359. {
  2360. bool expand = false;
  2361. int tail = qp->sq.tail;
  2362. u32 wqe_idx;
  2363. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2364. *polled = false; /* WC cannot be consumed yet */
  2365. } else {
  2366. ibwc->status = IB_WC_SUCCESS;
  2367. ibwc->wc_flags = 0;
  2368. ibwc->qp = &qp->ibqp;
  2369. ocrdma_update_wc(qp, ibwc, tail);
  2370. *polled = true;
  2371. }
  2372. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2373. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2374. if (tail != wqe_idx)
  2375. expand = true; /* Coalesced CQE can't be consumed yet */
  2376. ocrdma_hwq_inc_tail(&qp->sq);
  2377. return expand;
  2378. }
  2379. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2380. struct ib_wc *ibwc, bool *polled, bool *stop)
  2381. {
  2382. int status;
  2383. bool expand;
  2384. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2385. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2386. if (status == OCRDMA_CQE_SUCCESS)
  2387. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2388. else
  2389. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2390. return expand;
  2391. }
  2392. static int ocrdma_update_ud_rcqe(struct ocrdma_dev *dev, struct ib_wc *ibwc,
  2393. struct ocrdma_cqe *cqe)
  2394. {
  2395. int status;
  2396. u16 hdr_type = 0;
  2397. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2398. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2399. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2400. OCRDMA_CQE_SRCQP_MASK;
  2401. ibwc->pkey_index = 0;
  2402. ibwc->wc_flags = IB_WC_GRH;
  2403. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2404. OCRDMA_CQE_UD_XFER_LEN_SHIFT) &
  2405. OCRDMA_CQE_UD_XFER_LEN_MASK;
  2406. if (ocrdma_is_udp_encap_supported(dev)) {
  2407. hdr_type = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2408. OCRDMA_CQE_UD_L3TYPE_SHIFT) &
  2409. OCRDMA_CQE_UD_L3TYPE_MASK;
  2410. ibwc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
  2411. ibwc->network_hdr_type = hdr_type;
  2412. }
  2413. return status;
  2414. }
  2415. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2416. struct ocrdma_cqe *cqe,
  2417. struct ocrdma_qp *qp)
  2418. {
  2419. unsigned long flags;
  2420. struct ocrdma_srq *srq;
  2421. u32 wqe_idx;
  2422. srq = get_ocrdma_srq(qp->ibqp.srq);
  2423. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2424. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2425. BUG_ON(wqe_idx < 1);
  2426. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2427. spin_lock_irqsave(&srq->q_lock, flags);
  2428. ocrdma_srq_toggle_bit(srq, wqe_idx - 1);
  2429. spin_unlock_irqrestore(&srq->q_lock, flags);
  2430. ocrdma_hwq_inc_tail(&srq->rq);
  2431. }
  2432. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2433. struct ib_wc *ibwc, bool *polled, bool *stop,
  2434. int status)
  2435. {
  2436. bool expand;
  2437. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2438. if (status < OCRDMA_MAX_CQE_ERR)
  2439. atomic_inc(&dev->cqe_err_stats[status]);
  2440. /* when hw_rq is empty, but wq is not empty, so continue
  2441. * to keep the cqe to get the cq event again.
  2442. */
  2443. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2444. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2445. *polled = true;
  2446. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2447. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2448. } else {
  2449. *polled = false;
  2450. *stop = true;
  2451. expand = false;
  2452. }
  2453. } else if (is_hw_rq_empty(qp)) {
  2454. /* Do nothing */
  2455. expand = false;
  2456. *polled = false;
  2457. *stop = false;
  2458. } else {
  2459. *polled = true;
  2460. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2461. }
  2462. return expand;
  2463. }
  2464. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2465. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2466. {
  2467. struct ocrdma_dev *dev;
  2468. dev = get_ocrdma_dev(qp->ibqp.device);
  2469. ibwc->opcode = IB_WC_RECV;
  2470. ibwc->qp = &qp->ibqp;
  2471. ibwc->status = IB_WC_SUCCESS;
  2472. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2473. ocrdma_update_ud_rcqe(dev, ibwc, cqe);
  2474. else
  2475. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2476. if (is_cqe_imm(cqe)) {
  2477. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2478. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2479. } else if (is_cqe_wr_imm(cqe)) {
  2480. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2481. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2482. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2483. } else if (is_cqe_invalidated(cqe)) {
  2484. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2485. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2486. }
  2487. if (qp->ibqp.srq) {
  2488. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2489. } else {
  2490. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2491. ocrdma_hwq_inc_tail(&qp->rq);
  2492. }
  2493. }
  2494. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2495. struct ib_wc *ibwc, bool *polled, bool *stop)
  2496. {
  2497. int status;
  2498. bool expand = false;
  2499. ibwc->wc_flags = 0;
  2500. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2501. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2502. OCRDMA_CQE_UD_STATUS_MASK) >>
  2503. OCRDMA_CQE_UD_STATUS_SHIFT;
  2504. } else {
  2505. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2506. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2507. }
  2508. if (status == OCRDMA_CQE_SUCCESS) {
  2509. *polled = true;
  2510. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2511. } else {
  2512. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2513. status);
  2514. }
  2515. return expand;
  2516. }
  2517. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2518. u16 cur_getp)
  2519. {
  2520. if (cq->phase_change) {
  2521. if (cur_getp == 0)
  2522. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2523. } else {
  2524. /* clear valid bit */
  2525. cqe->flags_status_srcqpn = 0;
  2526. }
  2527. }
  2528. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2529. struct ib_wc *ibwc)
  2530. {
  2531. u16 qpn = 0;
  2532. int i = 0;
  2533. bool expand = false;
  2534. int polled_hw_cqes = 0;
  2535. struct ocrdma_qp *qp = NULL;
  2536. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2537. struct ocrdma_cqe *cqe;
  2538. u16 cur_getp; bool polled = false; bool stop = false;
  2539. cur_getp = cq->getp;
  2540. while (num_entries) {
  2541. cqe = cq->va + cur_getp;
  2542. /* check whether valid cqe or not */
  2543. if (!is_cqe_valid(cq, cqe))
  2544. break;
  2545. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2546. /* ignore discarded cqe */
  2547. if (qpn == 0)
  2548. goto skip_cqe;
  2549. qp = dev->qp_tbl[qpn];
  2550. BUG_ON(qp == NULL);
  2551. if (is_cqe_for_sq(cqe)) {
  2552. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2553. &stop);
  2554. } else {
  2555. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2556. &stop);
  2557. }
  2558. if (expand)
  2559. goto expand_cqe;
  2560. if (stop)
  2561. goto stop_cqe;
  2562. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2563. cqe->cmn.qpn = 0;
  2564. skip_cqe:
  2565. polled_hw_cqes += 1;
  2566. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2567. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2568. expand_cqe:
  2569. if (polled) {
  2570. num_entries -= 1;
  2571. i += 1;
  2572. ibwc = ibwc + 1;
  2573. polled = false;
  2574. }
  2575. }
  2576. stop_cqe:
  2577. cq->getp = cur_getp;
  2578. if (polled_hw_cqes)
  2579. ocrdma_ring_cq_db(dev, cq->id, false, false, polled_hw_cqes);
  2580. return i;
  2581. }
  2582. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2583. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2584. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2585. {
  2586. int err_cqes = 0;
  2587. while (num_entries) {
  2588. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2589. break;
  2590. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2591. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2592. ocrdma_hwq_inc_tail(&qp->sq);
  2593. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2594. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2595. ocrdma_hwq_inc_tail(&qp->rq);
  2596. } else {
  2597. return err_cqes;
  2598. }
  2599. ibwc->byte_len = 0;
  2600. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2601. ibwc = ibwc + 1;
  2602. err_cqes += 1;
  2603. num_entries -= 1;
  2604. }
  2605. return err_cqes;
  2606. }
  2607. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2608. {
  2609. int cqes_to_poll = num_entries;
  2610. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2611. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2612. int num_os_cqe = 0, err_cqes = 0;
  2613. struct ocrdma_qp *qp;
  2614. unsigned long flags;
  2615. /* poll cqes from adapter CQ */
  2616. spin_lock_irqsave(&cq->cq_lock, flags);
  2617. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2618. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2619. cqes_to_poll -= num_os_cqe;
  2620. if (cqes_to_poll) {
  2621. wc = wc + num_os_cqe;
  2622. /* adapter returns single error cqe when qp moves to
  2623. * error state. So insert error cqes with wc_status as
  2624. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2625. * respectively which uses this CQ.
  2626. */
  2627. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2628. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2629. if (cqes_to_poll == 0)
  2630. break;
  2631. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2632. cqes_to_poll -= err_cqes;
  2633. num_os_cqe += err_cqes;
  2634. wc = wc + err_cqes;
  2635. }
  2636. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2637. }
  2638. return num_os_cqe;
  2639. }
  2640. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2641. {
  2642. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2643. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2644. u16 cq_id;
  2645. unsigned long flags;
  2646. bool arm_needed = false, sol_needed = false;
  2647. cq_id = cq->id;
  2648. spin_lock_irqsave(&cq->cq_lock, flags);
  2649. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2650. arm_needed = true;
  2651. if (cq_flags & IB_CQ_SOLICITED)
  2652. sol_needed = true;
  2653. ocrdma_ring_cq_db(dev, cq_id, arm_needed, sol_needed, 0);
  2654. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2655. return 0;
  2656. }
  2657. struct ib_mr *ocrdma_alloc_mr(struct ib_pd *ibpd,
  2658. enum ib_mr_type mr_type,
  2659. u32 max_num_sg)
  2660. {
  2661. int status;
  2662. struct ocrdma_mr *mr;
  2663. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2664. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2665. if (mr_type != IB_MR_TYPE_MEM_REG)
  2666. return ERR_PTR(-EINVAL);
  2667. if (max_num_sg > dev->attr.max_pages_per_frmr)
  2668. return ERR_PTR(-EINVAL);
  2669. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2670. if (!mr)
  2671. return ERR_PTR(-ENOMEM);
  2672. mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
  2673. if (!mr->pages) {
  2674. status = -ENOMEM;
  2675. goto pl_err;
  2676. }
  2677. status = ocrdma_get_pbl_info(dev, mr, max_num_sg);
  2678. if (status)
  2679. goto pbl_err;
  2680. mr->hwmr.fr_mr = 1;
  2681. mr->hwmr.remote_rd = 0;
  2682. mr->hwmr.remote_wr = 0;
  2683. mr->hwmr.local_rd = 0;
  2684. mr->hwmr.local_wr = 0;
  2685. mr->hwmr.mw_bind = 0;
  2686. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2687. if (status)
  2688. goto pbl_err;
  2689. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2690. if (status)
  2691. goto mbx_err;
  2692. mr->ibmr.rkey = mr->hwmr.lkey;
  2693. mr->ibmr.lkey = mr->hwmr.lkey;
  2694. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] =
  2695. (unsigned long) mr;
  2696. return &mr->ibmr;
  2697. mbx_err:
  2698. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2699. pbl_err:
  2700. kfree(mr->pages);
  2701. pl_err:
  2702. kfree(mr);
  2703. return ERR_PTR(-ENOMEM);
  2704. }
  2705. static int ocrdma_set_page(struct ib_mr *ibmr, u64 addr)
  2706. {
  2707. struct ocrdma_mr *mr = get_ocrdma_mr(ibmr);
  2708. if (unlikely(mr->npages == mr->hwmr.num_pbes))
  2709. return -ENOMEM;
  2710. mr->pages[mr->npages++] = addr;
  2711. return 0;
  2712. }
  2713. int ocrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
  2714. unsigned int *sg_offset)
  2715. {
  2716. struct ocrdma_mr *mr = get_ocrdma_mr(ibmr);
  2717. mr->npages = 0;
  2718. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, ocrdma_set_page);
  2719. }