mthca_main.c 34 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/init.h>
  36. #include <linux/errno.h>
  37. #include <linux/pci.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/gfp.h>
  40. #include "mthca_dev.h"
  41. #include "mthca_config_reg.h"
  42. #include "mthca_cmd.h"
  43. #include "mthca_profile.h"
  44. #include "mthca_memfree.h"
  45. #include "mthca_wqe.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  50. int mthca_debug_level = 0;
  51. module_param_named(debug_level, mthca_debug_level, int, 0644);
  52. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  53. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  54. #ifdef CONFIG_PCI_MSI
  55. static int msi_x = 1;
  56. module_param(msi_x, int, 0444);
  57. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #endif /* CONFIG_PCI_MSI */
  61. static int tune_pci = 0;
  62. module_param(tune_pci, int, 0444);
  63. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  64. DEFINE_MUTEX(mthca_device_mutex);
  65. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  66. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  67. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  68. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  69. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  70. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  71. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  72. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  73. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  74. static struct mthca_profile hca_profile = {
  75. .num_qp = MTHCA_DEFAULT_NUM_QP,
  76. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  77. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  78. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  79. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  80. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  81. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  82. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  83. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  84. };
  85. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  86. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  87. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  88. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  89. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  90. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  91. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  92. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  93. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  94. MODULE_PARM_DESC(num_mpt,
  95. "maximum number of memory protection table entries per HCA");
  96. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  97. MODULE_PARM_DESC(num_mtt,
  98. "maximum number of memory translation table segments per HCA");
  99. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  100. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  101. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  102. MODULE_PARM_DESC(fmr_reserved_mtts,
  103. "number of memory translation table segments reserved for FMR");
  104. static int log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  105. module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
  106. MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
  107. static char mthca_version[] =
  108. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  109. DRV_VERSION " (" DRV_RELDATE ")\n";
  110. static int mthca_tune_pci(struct mthca_dev *mdev)
  111. {
  112. if (!tune_pci)
  113. return 0;
  114. /* First try to max out Read Byte Count */
  115. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  116. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  117. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  118. "aborting.\n");
  119. return -ENODEV;
  120. }
  121. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  122. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  123. if (pci_is_pcie(mdev->pdev)) {
  124. if (pcie_set_readrq(mdev->pdev, 4096)) {
  125. mthca_err(mdev, "Couldn't write PCI Express read request, "
  126. "aborting.\n");
  127. return -ENODEV;
  128. }
  129. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  130. mthca_info(mdev, "No PCI Express capability, "
  131. "not setting Max Read Request Size.\n");
  132. return 0;
  133. }
  134. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  135. {
  136. int err;
  137. mdev->limits.mtt_seg_size = (1 << log_mtts_per_seg) * 8;
  138. err = mthca_QUERY_DEV_LIM(mdev, dev_lim);
  139. if (err) {
  140. mthca_err(mdev, "QUERY_DEV_LIM command returned %d"
  141. ", aborting.\n", err);
  142. return err;
  143. }
  144. if (dev_lim->min_page_sz > PAGE_SIZE) {
  145. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  146. "kernel PAGE_SIZE of %ld, aborting.\n",
  147. dev_lim->min_page_sz, PAGE_SIZE);
  148. return -ENODEV;
  149. }
  150. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  151. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  152. "aborting.\n",
  153. dev_lim->num_ports, MTHCA_MAX_PORTS);
  154. return -ENODEV;
  155. }
  156. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  157. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  158. "PCI resource 2 size of 0x%llx, aborting.\n",
  159. dev_lim->uar_size,
  160. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  161. return -ENODEV;
  162. }
  163. mdev->limits.num_ports = dev_lim->num_ports;
  164. mdev->limits.vl_cap = dev_lim->max_vl;
  165. mdev->limits.mtu_cap = dev_lim->max_mtu;
  166. mdev->limits.gid_table_len = dev_lim->max_gids;
  167. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  168. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  169. /*
  170. * Need to allow for worst case send WQE overhead and check
  171. * whether max_desc_sz imposes a lower limit than max_sg; UD
  172. * send has the biggest overhead.
  173. */
  174. mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
  175. (dev_lim->max_desc_sz -
  176. sizeof (struct mthca_next_seg) -
  177. (mthca_is_memfree(mdev) ?
  178. sizeof (struct mthca_arbel_ud_seg) :
  179. sizeof (struct mthca_tavor_ud_seg))) /
  180. sizeof (struct mthca_data_seg));
  181. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  182. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  183. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  184. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  185. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  186. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  187. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  188. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  189. /*
  190. * Subtract 1 from the limit because we need to allocate a
  191. * spare CQE so the HCA HW can tell the difference between an
  192. * empty CQ and a full CQ.
  193. */
  194. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  195. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  196. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  197. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  198. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  199. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  200. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  201. mdev->limits.port_width_cap = dev_lim->max_port_width;
  202. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  203. mdev->limits.flags = dev_lim->flags;
  204. /*
  205. * For old FW that doesn't return static rate support, use a
  206. * value of 0x3 (only static rate values of 0 or 1 are handled),
  207. * except on Sinai, where even old FW can handle static rate
  208. * values of 2 and 3.
  209. */
  210. if (dev_lim->stat_rate_support)
  211. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  212. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  213. mdev->limits.stat_rate_support = 0xf;
  214. else
  215. mdev->limits.stat_rate_support = 0x3;
  216. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  217. May be doable since hardware supports it for SRQ.
  218. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  219. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  220. supported by driver. */
  221. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  222. IB_DEVICE_PORT_ACTIVE_EVENT |
  223. IB_DEVICE_SYS_IMAGE_GUID |
  224. IB_DEVICE_RC_RNR_NAK_GEN;
  225. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  226. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  227. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  228. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  229. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  230. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  231. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  232. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  233. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  234. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  235. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  236. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  237. if (mthca_is_memfree(mdev))
  238. if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
  239. mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  240. return 0;
  241. }
  242. static int mthca_init_tavor(struct mthca_dev *mdev)
  243. {
  244. s64 size;
  245. int err;
  246. struct mthca_dev_lim dev_lim;
  247. struct mthca_profile profile;
  248. struct mthca_init_hca_param init_hca;
  249. err = mthca_SYS_EN(mdev);
  250. if (err) {
  251. mthca_err(mdev, "SYS_EN command returned %d, aborting.\n", err);
  252. return err;
  253. }
  254. err = mthca_QUERY_FW(mdev);
  255. if (err) {
  256. mthca_err(mdev, "QUERY_FW command returned %d,"
  257. " aborting.\n", err);
  258. goto err_disable;
  259. }
  260. err = mthca_QUERY_DDR(mdev);
  261. if (err) {
  262. mthca_err(mdev, "QUERY_DDR command returned %d, aborting.\n", err);
  263. goto err_disable;
  264. }
  265. err = mthca_dev_lim(mdev, &dev_lim);
  266. if (err) {
  267. mthca_err(mdev, "QUERY_DEV_LIM command returned %d, aborting.\n", err);
  268. goto err_disable;
  269. }
  270. profile = hca_profile;
  271. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  272. profile.uarc_size = 0;
  273. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  274. profile.num_srq = dev_lim.max_srqs;
  275. size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  276. if (size < 0) {
  277. err = size;
  278. goto err_disable;
  279. }
  280. err = mthca_INIT_HCA(mdev, &init_hca);
  281. if (err) {
  282. mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err);
  283. goto err_disable;
  284. }
  285. return 0;
  286. err_disable:
  287. mthca_SYS_DIS(mdev);
  288. return err;
  289. }
  290. static int mthca_load_fw(struct mthca_dev *mdev)
  291. {
  292. int err;
  293. /* FIXME: use HCA-attached memory for FW if present */
  294. mdev->fw.arbel.fw_icm =
  295. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  296. GFP_HIGHUSER | __GFP_NOWARN, 0);
  297. if (!mdev->fw.arbel.fw_icm) {
  298. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  299. return -ENOMEM;
  300. }
  301. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm);
  302. if (err) {
  303. mthca_err(mdev, "MAP_FA command returned %d, aborting.\n", err);
  304. goto err_free;
  305. }
  306. err = mthca_RUN_FW(mdev);
  307. if (err) {
  308. mthca_err(mdev, "RUN_FW command returned %d, aborting.\n", err);
  309. goto err_unmap_fa;
  310. }
  311. return 0;
  312. err_unmap_fa:
  313. mthca_UNMAP_FA(mdev);
  314. err_free:
  315. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  316. return err;
  317. }
  318. static int mthca_init_icm(struct mthca_dev *mdev,
  319. struct mthca_dev_lim *dev_lim,
  320. struct mthca_init_hca_param *init_hca,
  321. u64 icm_size)
  322. {
  323. u64 aux_pages;
  324. int err;
  325. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages);
  326. if (err) {
  327. mthca_err(mdev, "SET_ICM_SIZE command returned %d, aborting.\n", err);
  328. return err;
  329. }
  330. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  331. (unsigned long long) icm_size >> 10,
  332. (unsigned long long) aux_pages << 2);
  333. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  334. GFP_HIGHUSER | __GFP_NOWARN, 0);
  335. if (!mdev->fw.arbel.aux_icm) {
  336. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  337. return -ENOMEM;
  338. }
  339. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm);
  340. if (err) {
  341. mthca_err(mdev, "MAP_ICM_AUX returned %d, aborting.\n", err);
  342. goto err_free_aux;
  343. }
  344. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  345. if (err) {
  346. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  347. goto err_unmap_aux;
  348. }
  349. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  350. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size,
  351. dma_get_cache_alignment()) / mdev->limits.mtt_seg_size;
  352. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  353. mdev->limits.mtt_seg_size,
  354. mdev->limits.num_mtt_segs,
  355. mdev->limits.reserved_mtts,
  356. 1, 0);
  357. if (!mdev->mr_table.mtt_table) {
  358. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  359. err = -ENOMEM;
  360. goto err_unmap_eq;
  361. }
  362. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  363. dev_lim->mpt_entry_sz,
  364. mdev->limits.num_mpts,
  365. mdev->limits.reserved_mrws,
  366. 1, 1);
  367. if (!mdev->mr_table.mpt_table) {
  368. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  369. err = -ENOMEM;
  370. goto err_unmap_mtt;
  371. }
  372. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  373. dev_lim->qpc_entry_sz,
  374. mdev->limits.num_qps,
  375. mdev->limits.reserved_qps,
  376. 0, 0);
  377. if (!mdev->qp_table.qp_table) {
  378. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  379. err = -ENOMEM;
  380. goto err_unmap_mpt;
  381. }
  382. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  383. dev_lim->eqpc_entry_sz,
  384. mdev->limits.num_qps,
  385. mdev->limits.reserved_qps,
  386. 0, 0);
  387. if (!mdev->qp_table.eqp_table) {
  388. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  389. err = -ENOMEM;
  390. goto err_unmap_qp;
  391. }
  392. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  393. MTHCA_RDB_ENTRY_SIZE,
  394. mdev->limits.num_qps <<
  395. mdev->qp_table.rdb_shift, 0,
  396. 0, 0);
  397. if (!mdev->qp_table.rdb_table) {
  398. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  399. err = -ENOMEM;
  400. goto err_unmap_eqp;
  401. }
  402. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  403. dev_lim->cqc_entry_sz,
  404. mdev->limits.num_cqs,
  405. mdev->limits.reserved_cqs,
  406. 0, 0);
  407. if (!mdev->cq_table.table) {
  408. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  409. err = -ENOMEM;
  410. goto err_unmap_rdb;
  411. }
  412. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  413. mdev->srq_table.table =
  414. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  415. dev_lim->srq_entry_sz,
  416. mdev->limits.num_srqs,
  417. mdev->limits.reserved_srqs,
  418. 0, 0);
  419. if (!mdev->srq_table.table) {
  420. mthca_err(mdev, "Failed to map SRQ context memory, "
  421. "aborting.\n");
  422. err = -ENOMEM;
  423. goto err_unmap_cq;
  424. }
  425. }
  426. /*
  427. * It's not strictly required, but for simplicity just map the
  428. * whole multicast group table now. The table isn't very big
  429. * and it's a lot easier than trying to track ref counts.
  430. */
  431. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  432. MTHCA_MGM_ENTRY_SIZE,
  433. mdev->limits.num_mgms +
  434. mdev->limits.num_amgms,
  435. mdev->limits.num_mgms +
  436. mdev->limits.num_amgms,
  437. 0, 0);
  438. if (!mdev->mcg_table.table) {
  439. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  440. err = -ENOMEM;
  441. goto err_unmap_srq;
  442. }
  443. return 0;
  444. err_unmap_srq:
  445. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  446. mthca_free_icm_table(mdev, mdev->srq_table.table);
  447. err_unmap_cq:
  448. mthca_free_icm_table(mdev, mdev->cq_table.table);
  449. err_unmap_rdb:
  450. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  451. err_unmap_eqp:
  452. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  453. err_unmap_qp:
  454. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  455. err_unmap_mpt:
  456. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  457. err_unmap_mtt:
  458. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  459. err_unmap_eq:
  460. mthca_unmap_eq_icm(mdev);
  461. err_unmap_aux:
  462. mthca_UNMAP_ICM_AUX(mdev);
  463. err_free_aux:
  464. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  465. return err;
  466. }
  467. static void mthca_free_icms(struct mthca_dev *mdev)
  468. {
  469. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  470. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  471. mthca_free_icm_table(mdev, mdev->srq_table.table);
  472. mthca_free_icm_table(mdev, mdev->cq_table.table);
  473. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  474. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  475. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  476. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  477. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  478. mthca_unmap_eq_icm(mdev);
  479. mthca_UNMAP_ICM_AUX(mdev);
  480. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  481. }
  482. static int mthca_init_arbel(struct mthca_dev *mdev)
  483. {
  484. struct mthca_dev_lim dev_lim;
  485. struct mthca_profile profile;
  486. struct mthca_init_hca_param init_hca;
  487. s64 icm_size;
  488. int err;
  489. err = mthca_QUERY_FW(mdev);
  490. if (err) {
  491. mthca_err(mdev, "QUERY_FW command failed %d, aborting.\n", err);
  492. return err;
  493. }
  494. err = mthca_ENABLE_LAM(mdev);
  495. if (err == -EAGAIN) {
  496. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  497. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  498. } else if (err) {
  499. mthca_err(mdev, "ENABLE_LAM returned %d, aborting.\n", err);
  500. return err;
  501. }
  502. err = mthca_load_fw(mdev);
  503. if (err) {
  504. mthca_err(mdev, "Loading FW returned %d, aborting.\n", err);
  505. goto err_disable;
  506. }
  507. err = mthca_dev_lim(mdev, &dev_lim);
  508. if (err) {
  509. mthca_err(mdev, "QUERY_DEV_LIM returned %d, aborting.\n", err);
  510. goto err_stop_fw;
  511. }
  512. profile = hca_profile;
  513. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  514. profile.num_udav = 0;
  515. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  516. profile.num_srq = dev_lim.max_srqs;
  517. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  518. if (icm_size < 0) {
  519. err = icm_size;
  520. goto err_stop_fw;
  521. }
  522. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  523. if (err)
  524. goto err_stop_fw;
  525. err = mthca_INIT_HCA(mdev, &init_hca);
  526. if (err) {
  527. mthca_err(mdev, "INIT_HCA command returned %d, aborting.\n", err);
  528. goto err_free_icm;
  529. }
  530. return 0;
  531. err_free_icm:
  532. mthca_free_icms(mdev);
  533. err_stop_fw:
  534. mthca_UNMAP_FA(mdev);
  535. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  536. err_disable:
  537. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  538. mthca_DISABLE_LAM(mdev);
  539. return err;
  540. }
  541. static void mthca_close_hca(struct mthca_dev *mdev)
  542. {
  543. mthca_CLOSE_HCA(mdev, 0);
  544. if (mthca_is_memfree(mdev)) {
  545. mthca_free_icms(mdev);
  546. mthca_UNMAP_FA(mdev);
  547. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  548. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  549. mthca_DISABLE_LAM(mdev);
  550. } else
  551. mthca_SYS_DIS(mdev);
  552. }
  553. static int mthca_init_hca(struct mthca_dev *mdev)
  554. {
  555. int err;
  556. struct mthca_adapter adapter;
  557. if (mthca_is_memfree(mdev))
  558. err = mthca_init_arbel(mdev);
  559. else
  560. err = mthca_init_tavor(mdev);
  561. if (err)
  562. return err;
  563. err = mthca_QUERY_ADAPTER(mdev, &adapter);
  564. if (err) {
  565. mthca_err(mdev, "QUERY_ADAPTER command returned %d, aborting.\n", err);
  566. goto err_close;
  567. }
  568. mdev->eq_table.inta_pin = adapter.inta_pin;
  569. if (!mthca_is_memfree(mdev))
  570. mdev->rev_id = adapter.revision_id;
  571. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  572. return 0;
  573. err_close:
  574. mthca_close_hca(mdev);
  575. return err;
  576. }
  577. static int mthca_setup_hca(struct mthca_dev *dev)
  578. {
  579. int err;
  580. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  581. err = mthca_init_uar_table(dev);
  582. if (err) {
  583. mthca_err(dev, "Failed to initialize "
  584. "user access region table, aborting.\n");
  585. return err;
  586. }
  587. err = mthca_uar_alloc(dev, &dev->driver_uar);
  588. if (err) {
  589. mthca_err(dev, "Failed to allocate driver access region, "
  590. "aborting.\n");
  591. goto err_uar_table_free;
  592. }
  593. dev->kar = ioremap((phys_addr_t) dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  594. if (!dev->kar) {
  595. mthca_err(dev, "Couldn't map kernel access region, "
  596. "aborting.\n");
  597. err = -ENOMEM;
  598. goto err_uar_free;
  599. }
  600. err = mthca_init_pd_table(dev);
  601. if (err) {
  602. mthca_err(dev, "Failed to initialize "
  603. "protection domain table, aborting.\n");
  604. goto err_kar_unmap;
  605. }
  606. err = mthca_init_mr_table(dev);
  607. if (err) {
  608. mthca_err(dev, "Failed to initialize "
  609. "memory region table, aborting.\n");
  610. goto err_pd_table_free;
  611. }
  612. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  613. if (err) {
  614. mthca_err(dev, "Failed to create driver PD, "
  615. "aborting.\n");
  616. goto err_mr_table_free;
  617. }
  618. err = mthca_init_eq_table(dev);
  619. if (err) {
  620. mthca_err(dev, "Failed to initialize "
  621. "event queue table, aborting.\n");
  622. goto err_pd_free;
  623. }
  624. err = mthca_cmd_use_events(dev);
  625. if (err) {
  626. mthca_err(dev, "Failed to switch to event-driven "
  627. "firmware commands, aborting.\n");
  628. goto err_eq_table_free;
  629. }
  630. err = mthca_NOP(dev);
  631. if (err) {
  632. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  633. mthca_warn(dev, "NOP command failed to generate interrupt "
  634. "(IRQ %d).\n",
  635. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  636. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  637. } else {
  638. mthca_err(dev, "NOP command failed to generate interrupt "
  639. "(IRQ %d), aborting.\n",
  640. dev->pdev->irq);
  641. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  642. }
  643. goto err_cmd_poll;
  644. }
  645. mthca_dbg(dev, "NOP command IRQ test passed\n");
  646. err = mthca_init_cq_table(dev);
  647. if (err) {
  648. mthca_err(dev, "Failed to initialize "
  649. "completion queue table, aborting.\n");
  650. goto err_cmd_poll;
  651. }
  652. err = mthca_init_srq_table(dev);
  653. if (err) {
  654. mthca_err(dev, "Failed to initialize "
  655. "shared receive queue table, aborting.\n");
  656. goto err_cq_table_free;
  657. }
  658. err = mthca_init_qp_table(dev);
  659. if (err) {
  660. mthca_err(dev, "Failed to initialize "
  661. "queue pair table, aborting.\n");
  662. goto err_srq_table_free;
  663. }
  664. err = mthca_init_av_table(dev);
  665. if (err) {
  666. mthca_err(dev, "Failed to initialize "
  667. "address vector table, aborting.\n");
  668. goto err_qp_table_free;
  669. }
  670. err = mthca_init_mcg_table(dev);
  671. if (err) {
  672. mthca_err(dev, "Failed to initialize "
  673. "multicast group table, aborting.\n");
  674. goto err_av_table_free;
  675. }
  676. return 0;
  677. err_av_table_free:
  678. mthca_cleanup_av_table(dev);
  679. err_qp_table_free:
  680. mthca_cleanup_qp_table(dev);
  681. err_srq_table_free:
  682. mthca_cleanup_srq_table(dev);
  683. err_cq_table_free:
  684. mthca_cleanup_cq_table(dev);
  685. err_cmd_poll:
  686. mthca_cmd_use_polling(dev);
  687. err_eq_table_free:
  688. mthca_cleanup_eq_table(dev);
  689. err_pd_free:
  690. mthca_pd_free(dev, &dev->driver_pd);
  691. err_mr_table_free:
  692. mthca_cleanup_mr_table(dev);
  693. err_pd_table_free:
  694. mthca_cleanup_pd_table(dev);
  695. err_kar_unmap:
  696. iounmap(dev->kar);
  697. err_uar_free:
  698. mthca_uar_free(dev, &dev->driver_uar);
  699. err_uar_table_free:
  700. mthca_cleanup_uar_table(dev);
  701. return err;
  702. }
  703. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  704. {
  705. int err;
  706. err = pci_alloc_irq_vectors(mdev->pdev, 3, 3, PCI_IRQ_MSIX);
  707. if (err < 0)
  708. return err;
  709. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector =
  710. pci_irq_vector(mdev->pdev, 0);
  711. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector =
  712. pci_irq_vector(mdev->pdev, 1);
  713. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector =
  714. pci_irq_vector(mdev->pdev, 2);
  715. return 0;
  716. }
  717. /* Types of supported HCA */
  718. enum {
  719. TAVOR, /* MT23108 */
  720. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  721. ARBEL_NATIVE, /* MT25208 with extended features */
  722. SINAI /* MT25204 */
  723. };
  724. #define MTHCA_FW_VER(major, minor, subminor) \
  725. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  726. static struct {
  727. u64 latest_fw;
  728. u32 flags;
  729. } mthca_hca_table[] = {
  730. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  731. .flags = 0 },
  732. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  733. .flags = MTHCA_FLAG_PCIE },
  734. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  735. .flags = MTHCA_FLAG_MEMFREE |
  736. MTHCA_FLAG_PCIE },
  737. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  738. .flags = MTHCA_FLAG_MEMFREE |
  739. MTHCA_FLAG_PCIE |
  740. MTHCA_FLAG_SINAI_OPT }
  741. };
  742. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  743. {
  744. int ddr_hidden = 0;
  745. int err;
  746. struct mthca_dev *mdev;
  747. printk(KERN_INFO PFX "Initializing %s\n",
  748. pci_name(pdev));
  749. err = pci_enable_device(pdev);
  750. if (err) {
  751. dev_err(&pdev->dev, "Cannot enable PCI device, "
  752. "aborting.\n");
  753. return err;
  754. }
  755. /*
  756. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  757. * be present)
  758. */
  759. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  760. pci_resource_len(pdev, 0) != 1 << 20) {
  761. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  762. err = -ENODEV;
  763. goto err_disable_pdev;
  764. }
  765. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  766. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  767. err = -ENODEV;
  768. goto err_disable_pdev;
  769. }
  770. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  771. ddr_hidden = 1;
  772. err = pci_request_regions(pdev, DRV_NAME);
  773. if (err) {
  774. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  775. "aborting.\n");
  776. goto err_disable_pdev;
  777. }
  778. pci_set_master(pdev);
  779. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  780. if (err) {
  781. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  782. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  783. if (err) {
  784. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  785. goto err_free_res;
  786. }
  787. }
  788. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  789. if (err) {
  790. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  791. "consistent PCI DMA mask.\n");
  792. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  793. if (err) {
  794. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  795. "aborting.\n");
  796. goto err_free_res;
  797. }
  798. }
  799. /* We can handle large RDMA requests, so allow larger segments. */
  800. dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
  801. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  802. if (!mdev) {
  803. dev_err(&pdev->dev, "Device struct alloc failed, "
  804. "aborting.\n");
  805. err = -ENOMEM;
  806. goto err_free_res;
  807. }
  808. mdev->pdev = pdev;
  809. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  810. if (ddr_hidden)
  811. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  812. /*
  813. * Now reset the HCA before we touch the PCI capabilities or
  814. * attempt a firmware command, since a boot ROM may have left
  815. * the HCA in an undefined state.
  816. */
  817. err = mthca_reset(mdev);
  818. if (err) {
  819. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  820. goto err_free_dev;
  821. }
  822. err = mthca_cmd_init(mdev);
  823. if (err) {
  824. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  825. goto err_free_dev;
  826. }
  827. err = mthca_tune_pci(mdev);
  828. if (err)
  829. goto err_cmd;
  830. err = mthca_init_hca(mdev);
  831. if (err)
  832. goto err_cmd;
  833. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  834. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  835. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  836. (int) (mdev->fw_ver & 0xffff),
  837. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  838. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  839. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  840. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  841. }
  842. if (msi_x && !mthca_enable_msi_x(mdev))
  843. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  844. err = mthca_setup_hca(mdev);
  845. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  846. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  847. pci_free_irq_vectors(pdev);
  848. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  849. err = mthca_setup_hca(mdev);
  850. }
  851. if (err)
  852. goto err_close;
  853. err = mthca_register_device(mdev);
  854. if (err)
  855. goto err_cleanup;
  856. err = mthca_create_agents(mdev);
  857. if (err)
  858. goto err_unregister;
  859. pci_set_drvdata(pdev, mdev);
  860. mdev->hca_type = hca_type;
  861. mdev->active = true;
  862. return 0;
  863. err_unregister:
  864. mthca_unregister_device(mdev);
  865. err_cleanup:
  866. mthca_cleanup_mcg_table(mdev);
  867. mthca_cleanup_av_table(mdev);
  868. mthca_cleanup_qp_table(mdev);
  869. mthca_cleanup_srq_table(mdev);
  870. mthca_cleanup_cq_table(mdev);
  871. mthca_cmd_use_polling(mdev);
  872. mthca_cleanup_eq_table(mdev);
  873. mthca_pd_free(mdev, &mdev->driver_pd);
  874. mthca_cleanup_mr_table(mdev);
  875. mthca_cleanup_pd_table(mdev);
  876. mthca_cleanup_uar_table(mdev);
  877. err_close:
  878. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  879. pci_free_irq_vectors(pdev);
  880. mthca_close_hca(mdev);
  881. err_cmd:
  882. mthca_cmd_cleanup(mdev);
  883. err_free_dev:
  884. ib_dealloc_device(&mdev->ib_dev);
  885. err_free_res:
  886. pci_release_regions(pdev);
  887. err_disable_pdev:
  888. pci_disable_device(pdev);
  889. pci_set_drvdata(pdev, NULL);
  890. return err;
  891. }
  892. static void __mthca_remove_one(struct pci_dev *pdev)
  893. {
  894. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  895. int p;
  896. if (mdev) {
  897. mthca_free_agents(mdev);
  898. mthca_unregister_device(mdev);
  899. for (p = 1; p <= mdev->limits.num_ports; ++p)
  900. mthca_CLOSE_IB(mdev, p);
  901. mthca_cleanup_mcg_table(mdev);
  902. mthca_cleanup_av_table(mdev);
  903. mthca_cleanup_qp_table(mdev);
  904. mthca_cleanup_srq_table(mdev);
  905. mthca_cleanup_cq_table(mdev);
  906. mthca_cmd_use_polling(mdev);
  907. mthca_cleanup_eq_table(mdev);
  908. mthca_pd_free(mdev, &mdev->driver_pd);
  909. mthca_cleanup_mr_table(mdev);
  910. mthca_cleanup_pd_table(mdev);
  911. iounmap(mdev->kar);
  912. mthca_uar_free(mdev, &mdev->driver_uar);
  913. mthca_cleanup_uar_table(mdev);
  914. mthca_close_hca(mdev);
  915. mthca_cmd_cleanup(mdev);
  916. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  917. pci_free_irq_vectors(pdev);
  918. ib_dealloc_device(&mdev->ib_dev);
  919. pci_release_regions(pdev);
  920. pci_disable_device(pdev);
  921. pci_set_drvdata(pdev, NULL);
  922. }
  923. }
  924. int __mthca_restart_one(struct pci_dev *pdev)
  925. {
  926. struct mthca_dev *mdev;
  927. int hca_type;
  928. mdev = pci_get_drvdata(pdev);
  929. if (!mdev)
  930. return -ENODEV;
  931. hca_type = mdev->hca_type;
  932. __mthca_remove_one(pdev);
  933. return __mthca_init_one(pdev, hca_type);
  934. }
  935. static int mthca_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  936. {
  937. int ret;
  938. mutex_lock(&mthca_device_mutex);
  939. printk_once(KERN_INFO "%s", mthca_version);
  940. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  941. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  942. pci_name(pdev), id->driver_data);
  943. mutex_unlock(&mthca_device_mutex);
  944. return -ENODEV;
  945. }
  946. ret = __mthca_init_one(pdev, id->driver_data);
  947. mutex_unlock(&mthca_device_mutex);
  948. return ret;
  949. }
  950. static void mthca_remove_one(struct pci_dev *pdev)
  951. {
  952. mutex_lock(&mthca_device_mutex);
  953. __mthca_remove_one(pdev);
  954. mutex_unlock(&mthca_device_mutex);
  955. }
  956. static const struct pci_device_id mthca_pci_table[] = {
  957. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  958. .driver_data = TAVOR },
  959. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  960. .driver_data = TAVOR },
  961. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  962. .driver_data = ARBEL_COMPAT },
  963. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  964. .driver_data = ARBEL_COMPAT },
  965. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  966. .driver_data = ARBEL_NATIVE },
  967. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  968. .driver_data = ARBEL_NATIVE },
  969. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  970. .driver_data = SINAI },
  971. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  972. .driver_data = SINAI },
  973. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  974. .driver_data = SINAI },
  975. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  976. .driver_data = SINAI },
  977. { 0, }
  978. };
  979. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  980. static struct pci_driver mthca_driver = {
  981. .name = DRV_NAME,
  982. .id_table = mthca_pci_table,
  983. .probe = mthca_init_one,
  984. .remove = mthca_remove_one,
  985. };
  986. static void __init __mthca_check_profile_val(const char *name, int *pval,
  987. int pval_default)
  988. {
  989. /* value must be positive and power of 2 */
  990. int old_pval = *pval;
  991. if (old_pval <= 0)
  992. *pval = pval_default;
  993. else
  994. *pval = roundup_pow_of_two(old_pval);
  995. if (old_pval != *pval) {
  996. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  997. old_pval, name);
  998. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  999. }
  1000. }
  1001. #define mthca_check_profile_val(name, default) \
  1002. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1003. static void __init mthca_validate_profile(void)
  1004. {
  1005. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1006. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1007. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1008. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1009. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1010. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1011. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1012. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1013. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1014. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1015. hca_profile.fmr_reserved_mtts);
  1016. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1017. hca_profile.num_mtt);
  1018. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1019. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1020. hca_profile.fmr_reserved_mtts);
  1021. }
  1022. if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
  1023. printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n",
  1024. log_mtts_per_seg, ilog2(MTHCA_MTT_SEG_SIZE / 8));
  1025. log_mtts_per_seg = ilog2(MTHCA_MTT_SEG_SIZE / 8);
  1026. }
  1027. }
  1028. static int __init mthca_init(void)
  1029. {
  1030. int ret;
  1031. mthca_validate_profile();
  1032. ret = mthca_catas_init();
  1033. if (ret)
  1034. return ret;
  1035. ret = pci_register_driver(&mthca_driver);
  1036. if (ret < 0) {
  1037. mthca_catas_cleanup();
  1038. return ret;
  1039. }
  1040. return 0;
  1041. }
  1042. static void __exit mthca_cleanup(void)
  1043. {
  1044. pci_unregister_driver(&mthca_driver);
  1045. mthca_catas_cleanup();
  1046. }
  1047. module_init(mthca_init);
  1048. module_exit(mthca_cleanup);