i40iw_verbs.c 78 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/random.h>
  37. #include <linux/highmem.h>
  38. #include <linux/time.h>
  39. #include <linux/hugetlb.h>
  40. #include <asm/byteorder.h>
  41. #include <net/ip.h>
  42. #include <rdma/ib_verbs.h>
  43. #include <rdma/iw_cm.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/ib_umem.h>
  46. #include "i40iw.h"
  47. /**
  48. * i40iw_query_device - get device attributes
  49. * @ibdev: device pointer from stack
  50. * @props: returning device attributes
  51. * @udata: user data
  52. */
  53. static int i40iw_query_device(struct ib_device *ibdev,
  54. struct ib_device_attr *props,
  55. struct ib_udata *udata)
  56. {
  57. struct i40iw_device *iwdev = to_iwdev(ibdev);
  58. if (udata->inlen || udata->outlen)
  59. return -EINVAL;
  60. memset(props, 0, sizeof(*props));
  61. ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
  62. props->fw_ver = I40IW_FW_VERSION;
  63. props->device_cap_flags = iwdev->device_cap_flags;
  64. props->vendor_id = iwdev->ldev->pcidev->vendor;
  65. props->vendor_part_id = iwdev->ldev->pcidev->device;
  66. props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
  67. props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  68. props->max_qp = iwdev->max_qp - iwdev->used_qps;
  69. props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1;
  70. props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  71. props->max_cq = iwdev->max_cq - iwdev->used_cqs;
  72. props->max_cqe = iwdev->max_cqe;
  73. props->max_mr = iwdev->max_mr - iwdev->used_mrs;
  74. props->max_pd = iwdev->max_pd - iwdev->used_pds;
  75. props->max_sge_rd = I40IW_MAX_SGE_RD;
  76. props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
  77. props->max_qp_init_rd_atom = props->max_qp_rd_atom;
  78. props->atomic_cap = IB_ATOMIC_NONE;
  79. props->max_map_per_fmr = 1;
  80. props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
  81. return 0;
  82. }
  83. /**
  84. * i40iw_query_port - get port attrubutes
  85. * @ibdev: device pointer from stack
  86. * @port: port number for query
  87. * @props: returning device attributes
  88. */
  89. static int i40iw_query_port(struct ib_device *ibdev,
  90. u8 port,
  91. struct ib_port_attr *props)
  92. {
  93. struct i40iw_device *iwdev = to_iwdev(ibdev);
  94. struct net_device *netdev = iwdev->netdev;
  95. /* props being zeroed by the caller, avoid zeroing it here */
  96. props->max_mtu = IB_MTU_4096;
  97. props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
  98. props->lid = 1;
  99. if (netif_carrier_ok(iwdev->netdev))
  100. props->state = IB_PORT_ACTIVE;
  101. else
  102. props->state = IB_PORT_DOWN;
  103. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  104. IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
  105. props->gid_tbl_len = 1;
  106. props->pkey_tbl_len = 1;
  107. props->active_width = IB_WIDTH_4X;
  108. props->active_speed = 1;
  109. props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  110. return 0;
  111. }
  112. /**
  113. * i40iw_alloc_ucontext - Allocate the user context data structure
  114. * @ibdev: device pointer from stack
  115. * @udata: user data
  116. *
  117. * This keeps track of all objects associated with a particular
  118. * user-mode client.
  119. */
  120. static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
  121. struct ib_udata *udata)
  122. {
  123. struct i40iw_device *iwdev = to_iwdev(ibdev);
  124. struct i40iw_alloc_ucontext_req req;
  125. struct i40iw_alloc_ucontext_resp uresp;
  126. struct i40iw_ucontext *ucontext;
  127. if (ib_copy_from_udata(&req, udata, sizeof(req)))
  128. return ERR_PTR(-EINVAL);
  129. if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) {
  130. i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver);
  131. return ERR_PTR(-EINVAL);
  132. }
  133. memset(&uresp, 0, sizeof(uresp));
  134. uresp.max_qps = iwdev->max_qp;
  135. uresp.max_pds = iwdev->max_pd;
  136. uresp.wq_size = iwdev->max_qp_wr * 2;
  137. uresp.kernel_ver = req.userspace_ver;
  138. ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
  139. if (!ucontext)
  140. return ERR_PTR(-ENOMEM);
  141. ucontext->iwdev = iwdev;
  142. ucontext->abi_ver = req.userspace_ver;
  143. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  144. kfree(ucontext);
  145. return ERR_PTR(-EFAULT);
  146. }
  147. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  148. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  149. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  150. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  151. return &ucontext->ibucontext;
  152. }
  153. /**
  154. * i40iw_dealloc_ucontext - deallocate the user context data structure
  155. * @context: user context created during alloc
  156. */
  157. static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
  158. {
  159. struct i40iw_ucontext *ucontext = to_ucontext(context);
  160. unsigned long flags;
  161. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  162. if (!list_empty(&ucontext->cq_reg_mem_list)) {
  163. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  164. return -EBUSY;
  165. }
  166. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  167. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  168. if (!list_empty(&ucontext->qp_reg_mem_list)) {
  169. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  170. return -EBUSY;
  171. }
  172. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  173. kfree(ucontext);
  174. return 0;
  175. }
  176. /**
  177. * i40iw_mmap - user memory map
  178. * @context: context created during alloc
  179. * @vma: kernel info for user memory map
  180. */
  181. static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  182. {
  183. struct i40iw_ucontext *ucontext = to_ucontext(context);
  184. u64 dbaddr;
  185. if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
  186. return -EINVAL;
  187. dbaddr = I40IW_DB_ADDR_OFFSET + pci_resource_start(ucontext->iwdev->ldev->pcidev, 0);
  188. if (io_remap_pfn_range(vma, vma->vm_start, dbaddr >> PAGE_SHIFT, PAGE_SIZE,
  189. pgprot_noncached(vma->vm_page_prot)))
  190. return -EAGAIN;
  191. return 0;
  192. }
  193. /**
  194. * i40iw_alloc_push_page - allocate a push page for qp
  195. * @iwdev: iwarp device
  196. * @qp: hardware control qp
  197. */
  198. static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  199. {
  200. struct i40iw_cqp_request *cqp_request;
  201. struct cqp_commands_info *cqp_info;
  202. enum i40iw_status_code status;
  203. if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
  204. return;
  205. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  206. if (!cqp_request)
  207. return;
  208. atomic_inc(&cqp_request->refcount);
  209. cqp_info = &cqp_request->info;
  210. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  211. cqp_info->post_sq = 1;
  212. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  213. cqp_info->in.u.manage_push_page.info.free_page = 0;
  214. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  215. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  216. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  217. if (!status)
  218. qp->push_idx = cqp_request->compl_info.op_ret_val;
  219. else
  220. i40iw_pr_err("CQP-OP Push page fail");
  221. i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
  222. }
  223. /**
  224. * i40iw_dealloc_push_page - free a push page for qp
  225. * @iwdev: iwarp device
  226. * @qp: hardware control qp
  227. */
  228. static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  229. {
  230. struct i40iw_cqp_request *cqp_request;
  231. struct cqp_commands_info *cqp_info;
  232. enum i40iw_status_code status;
  233. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
  234. return;
  235. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
  236. if (!cqp_request)
  237. return;
  238. cqp_info = &cqp_request->info;
  239. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  240. cqp_info->post_sq = 1;
  241. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  242. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  243. cqp_info->in.u.manage_push_page.info.free_page = 1;
  244. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  245. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  246. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  247. if (!status)
  248. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  249. else
  250. i40iw_pr_err("CQP-OP Push page fail");
  251. }
  252. /**
  253. * i40iw_alloc_pd - allocate protection domain
  254. * @ibdev: device pointer from stack
  255. * @context: user context created during alloc
  256. * @udata: user data
  257. */
  258. static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
  259. struct ib_ucontext *context,
  260. struct ib_udata *udata)
  261. {
  262. struct i40iw_pd *iwpd;
  263. struct i40iw_device *iwdev = to_iwdev(ibdev);
  264. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  265. struct i40iw_alloc_pd_resp uresp;
  266. struct i40iw_sc_pd *sc_pd;
  267. struct i40iw_ucontext *ucontext;
  268. u32 pd_id = 0;
  269. int err;
  270. if (iwdev->closing)
  271. return ERR_PTR(-ENODEV);
  272. err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
  273. iwdev->max_pd, &pd_id, &iwdev->next_pd);
  274. if (err) {
  275. i40iw_pr_err("alloc resource failed\n");
  276. return ERR_PTR(err);
  277. }
  278. iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
  279. if (!iwpd) {
  280. err = -ENOMEM;
  281. goto free_res;
  282. }
  283. sc_pd = &iwpd->sc_pd;
  284. if (context) {
  285. ucontext = to_ucontext(context);
  286. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
  287. memset(&uresp, 0, sizeof(uresp));
  288. uresp.pd_id = pd_id;
  289. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  290. err = -EFAULT;
  291. goto error;
  292. }
  293. } else {
  294. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1);
  295. }
  296. i40iw_add_pdusecount(iwpd);
  297. return &iwpd->ibpd;
  298. error:
  299. kfree(iwpd);
  300. free_res:
  301. i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
  302. return ERR_PTR(err);
  303. }
  304. /**
  305. * i40iw_dealloc_pd - deallocate pd
  306. * @ibpd: ptr of pd to be deallocated
  307. */
  308. static int i40iw_dealloc_pd(struct ib_pd *ibpd)
  309. {
  310. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  311. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  312. i40iw_rem_pdusecount(iwpd, iwdev);
  313. return 0;
  314. }
  315. /**
  316. * i40iw_qp_roundup - return round up qp ring size
  317. * @wr_ring_size: ring size to round up
  318. */
  319. static int i40iw_qp_roundup(u32 wr_ring_size)
  320. {
  321. int scount = 1;
  322. if (wr_ring_size < I40IWQP_SW_MIN_WQSIZE)
  323. wr_ring_size = I40IWQP_SW_MIN_WQSIZE;
  324. for (wr_ring_size--; scount <= 16; scount *= 2)
  325. wr_ring_size |= wr_ring_size >> scount;
  326. return ++wr_ring_size;
  327. }
  328. /**
  329. * i40iw_get_pbl - Retrieve pbl from a list given a virtual
  330. * address
  331. * @va: user virtual address
  332. * @pbl_list: pbl list to search in (QP's or CQ's)
  333. */
  334. static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
  335. struct list_head *pbl_list)
  336. {
  337. struct i40iw_pbl *iwpbl;
  338. list_for_each_entry(iwpbl, pbl_list, list) {
  339. if (iwpbl->user_base == va) {
  340. list_del(&iwpbl->list);
  341. return iwpbl;
  342. }
  343. }
  344. return NULL;
  345. }
  346. /**
  347. * i40iw_free_qp_resources - free up memory resources for qp
  348. * @iwdev: iwarp device
  349. * @iwqp: qp ptr (user or kernel)
  350. * @qp_num: qp number assigned
  351. */
  352. void i40iw_free_qp_resources(struct i40iw_device *iwdev,
  353. struct i40iw_qp *iwqp,
  354. u32 qp_num)
  355. {
  356. struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
  357. i40iw_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
  358. i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
  359. if (qp_num)
  360. i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
  361. if (iwpbl->pbl_allocated)
  362. i40iw_free_pble(iwdev->pble_rsrc, &iwpbl->pble_alloc);
  363. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
  364. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
  365. kfree(iwqp->kqp.wrid_mem);
  366. iwqp->kqp.wrid_mem = NULL;
  367. kfree(iwqp->allocated_buffer);
  368. }
  369. /**
  370. * i40iw_clean_cqes - clean cq entries for qp
  371. * @iwqp: qp ptr (user or kernel)
  372. * @iwcq: cq ptr
  373. */
  374. static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
  375. {
  376. struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  377. ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
  378. }
  379. /**
  380. * i40iw_destroy_qp - destroy qp
  381. * @ibqp: qp's ib pointer also to get to device's qp address
  382. */
  383. static int i40iw_destroy_qp(struct ib_qp *ibqp)
  384. {
  385. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  386. iwqp->destroyed = 1;
  387. if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
  388. i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
  389. if (!iwqp->user_mode) {
  390. if (iwqp->iwscq) {
  391. i40iw_clean_cqes(iwqp, iwqp->iwscq);
  392. if (iwqp->iwrcq != iwqp->iwscq)
  393. i40iw_clean_cqes(iwqp, iwqp->iwrcq);
  394. }
  395. }
  396. i40iw_rem_ref(&iwqp->ibqp);
  397. return 0;
  398. }
  399. /**
  400. * i40iw_setup_virt_qp - setup for allocation of virtual qp
  401. * @dev: iwarp device
  402. * @qp: qp ptr
  403. * @init_info: initialize info to return
  404. */
  405. static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
  406. struct i40iw_qp *iwqp,
  407. struct i40iw_qp_init_info *init_info)
  408. {
  409. struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
  410. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  411. iwqp->page = qpmr->sq_page;
  412. init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
  413. if (iwpbl->pbl_allocated) {
  414. init_info->virtual_map = true;
  415. init_info->sq_pa = qpmr->sq_pbl.idx;
  416. init_info->rq_pa = qpmr->rq_pbl.idx;
  417. } else {
  418. init_info->sq_pa = qpmr->sq_pbl.addr;
  419. init_info->rq_pa = qpmr->rq_pbl.addr;
  420. }
  421. return 0;
  422. }
  423. /**
  424. * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
  425. * @iwdev: iwarp device
  426. * @iwqp: qp ptr (user or kernel)
  427. * @info: initialize info to return
  428. */
  429. static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
  430. struct i40iw_qp *iwqp,
  431. struct i40iw_qp_init_info *info)
  432. {
  433. struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
  434. u32 sqdepth, rqdepth;
  435. u32 sq_size, rq_size;
  436. u8 sqshift;
  437. u32 size;
  438. enum i40iw_status_code status;
  439. struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  440. sq_size = i40iw_qp_roundup(ukinfo->sq_size + 1);
  441. rq_size = i40iw_qp_roundup(ukinfo->rq_size + 1);
  442. status = i40iw_get_wqe_shift(sq_size, ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
  443. if (status)
  444. return -ENOMEM;
  445. sqdepth = sq_size << sqshift;
  446. rqdepth = rq_size << I40IW_MAX_RQ_WQE_SHIFT;
  447. size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
  448. iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
  449. ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
  450. if (!ukinfo->sq_wrtrk_array)
  451. return -ENOMEM;
  452. ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
  453. size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
  454. size += (I40IW_SHADOW_AREA_SIZE << 3);
  455. status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
  456. if (status) {
  457. kfree(ukinfo->sq_wrtrk_array);
  458. ukinfo->sq_wrtrk_array = NULL;
  459. return -ENOMEM;
  460. }
  461. ukinfo->sq = mem->va;
  462. info->sq_pa = mem->pa;
  463. ukinfo->rq = &ukinfo->sq[sqdepth];
  464. info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
  465. ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
  466. info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
  467. ukinfo->sq_size = sq_size;
  468. ukinfo->rq_size = rq_size;
  469. ukinfo->qp_id = iwqp->ibqp.qp_num;
  470. return 0;
  471. }
  472. /**
  473. * i40iw_create_qp - create qp
  474. * @ibpd: ptr of pd
  475. * @init_attr: attributes for qp
  476. * @udata: user data for create qp
  477. */
  478. static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
  479. struct ib_qp_init_attr *init_attr,
  480. struct ib_udata *udata)
  481. {
  482. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  483. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  484. struct i40iw_cqp *iwcqp = &iwdev->cqp;
  485. struct i40iw_qp *iwqp;
  486. struct i40iw_ucontext *ucontext;
  487. struct i40iw_create_qp_req req;
  488. struct i40iw_create_qp_resp uresp;
  489. u32 qp_num = 0;
  490. void *mem;
  491. enum i40iw_status_code ret;
  492. int err_code;
  493. int sq_size;
  494. int rq_size;
  495. struct i40iw_sc_qp *qp;
  496. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  497. struct i40iw_qp_init_info init_info;
  498. struct i40iw_create_qp_info *qp_info;
  499. struct i40iw_cqp_request *cqp_request;
  500. struct cqp_commands_info *cqp_info;
  501. struct i40iw_qp_host_ctx_info *ctx_info;
  502. struct i40iwarp_offload_info *iwarp_info;
  503. unsigned long flags;
  504. if (iwdev->closing)
  505. return ERR_PTR(-ENODEV);
  506. if (init_attr->create_flags)
  507. return ERR_PTR(-EINVAL);
  508. if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
  509. init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  510. if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  511. init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  512. if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  513. init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  514. memset(&init_info, 0, sizeof(init_info));
  515. sq_size = init_attr->cap.max_send_wr;
  516. rq_size = init_attr->cap.max_recv_wr;
  517. init_info.vsi = &iwdev->vsi;
  518. init_info.qp_uk_init_info.sq_size = sq_size;
  519. init_info.qp_uk_init_info.rq_size = rq_size;
  520. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  521. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  522. init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
  523. mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
  524. if (!mem)
  525. return ERR_PTR(-ENOMEM);
  526. iwqp = (struct i40iw_qp *)mem;
  527. iwqp->allocated_buffer = mem;
  528. qp = &iwqp->sc_qp;
  529. qp->back_qp = (void *)iwqp;
  530. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  531. iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
  532. if (i40iw_allocate_dma_mem(dev->hw,
  533. &iwqp->q2_ctx_mem,
  534. I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
  535. 256)) {
  536. i40iw_pr_err("dma_mem failed\n");
  537. err_code = -ENOMEM;
  538. goto error;
  539. }
  540. init_info.q2 = iwqp->q2_ctx_mem.va;
  541. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  542. init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
  543. init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
  544. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
  545. &qp_num, &iwdev->next_qp);
  546. if (err_code) {
  547. i40iw_pr_err("qp resource\n");
  548. goto error;
  549. }
  550. iwqp->iwdev = iwdev;
  551. iwqp->iwpd = iwpd;
  552. iwqp->ibqp.qp_num = qp_num;
  553. qp = &iwqp->sc_qp;
  554. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  555. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  556. iwqp->host_ctx.va = init_info.host_ctx;
  557. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  558. iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
  559. init_info.pd = &iwpd->sc_pd;
  560. init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
  561. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  562. if (init_attr->qp_type != IB_QPT_RC) {
  563. err_code = -EINVAL;
  564. goto error;
  565. }
  566. if (iwdev->push_mode)
  567. i40iw_alloc_push_page(iwdev, qp);
  568. if (udata) {
  569. err_code = ib_copy_from_udata(&req, udata, sizeof(req));
  570. if (err_code) {
  571. i40iw_pr_err("ib_copy_from_data\n");
  572. goto error;
  573. }
  574. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  575. if (ibpd->uobject && ibpd->uobject->context) {
  576. iwqp->user_mode = 1;
  577. ucontext = to_ucontext(ibpd->uobject->context);
  578. if (req.user_wqe_buffers) {
  579. struct i40iw_pbl *iwpbl;
  580. spin_lock_irqsave(
  581. &ucontext->qp_reg_mem_list_lock, flags);
  582. iwpbl = i40iw_get_pbl(
  583. (unsigned long)req.user_wqe_buffers,
  584. &ucontext->qp_reg_mem_list);
  585. spin_unlock_irqrestore(
  586. &ucontext->qp_reg_mem_list_lock, flags);
  587. if (!iwpbl) {
  588. err_code = -ENODATA;
  589. i40iw_pr_err("no pbl info\n");
  590. goto error;
  591. }
  592. memcpy(&iwqp->iwpbl, iwpbl, sizeof(iwqp->iwpbl));
  593. }
  594. }
  595. err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
  596. } else {
  597. err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
  598. }
  599. if (err_code) {
  600. i40iw_pr_err("setup qp failed\n");
  601. goto error;
  602. }
  603. init_info.type = I40IW_QP_TYPE_IWARP;
  604. ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
  605. if (ret) {
  606. err_code = -EPROTO;
  607. i40iw_pr_err("qp_init fail\n");
  608. goto error;
  609. }
  610. ctx_info = &iwqp->ctx_info;
  611. iwarp_info = &iwqp->iwarp_info;
  612. iwarp_info->rd_enable = true;
  613. iwarp_info->wr_rdresp_en = true;
  614. if (!iwqp->user_mode) {
  615. iwarp_info->fast_reg_en = true;
  616. iwarp_info->priv_mode_en = true;
  617. }
  618. iwarp_info->ddp_ver = 1;
  619. iwarp_info->rdmap_ver = 1;
  620. ctx_info->iwarp_info_valid = true;
  621. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  622. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  623. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
  624. ctx_info->push_mode_en = false;
  625. } else {
  626. ctx_info->push_mode_en = true;
  627. ctx_info->push_idx = qp->push_idx;
  628. }
  629. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  630. (u64 *)iwqp->host_ctx.va,
  631. ctx_info);
  632. ctx_info->iwarp_info_valid = false;
  633. cqp_request = i40iw_get_cqp_request(iwcqp, true);
  634. if (!cqp_request) {
  635. err_code = -ENOMEM;
  636. goto error;
  637. }
  638. cqp_info = &cqp_request->info;
  639. qp_info = &cqp_request->info.in.u.qp_create.info;
  640. memset(qp_info, 0, sizeof(*qp_info));
  641. qp_info->cq_num_valid = true;
  642. qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
  643. cqp_info->cqp_cmd = OP_QP_CREATE;
  644. cqp_info->post_sq = 1;
  645. cqp_info->in.u.qp_create.qp = qp;
  646. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  647. ret = i40iw_handle_cqp_op(iwdev, cqp_request);
  648. if (ret) {
  649. i40iw_pr_err("CQP-OP QP create fail");
  650. err_code = -EACCES;
  651. goto error;
  652. }
  653. i40iw_add_ref(&iwqp->ibqp);
  654. spin_lock_init(&iwqp->lock);
  655. iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
  656. iwdev->qp_table[qp_num] = iwqp;
  657. i40iw_add_pdusecount(iwqp->iwpd);
  658. i40iw_add_devusecount(iwdev);
  659. if (ibpd->uobject && udata) {
  660. memset(&uresp, 0, sizeof(uresp));
  661. uresp.actual_sq_size = sq_size;
  662. uresp.actual_rq_size = rq_size;
  663. uresp.qp_id = qp_num;
  664. uresp.push_idx = qp->push_idx;
  665. err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  666. if (err_code) {
  667. i40iw_pr_err("copy_to_udata failed\n");
  668. i40iw_destroy_qp(&iwqp->ibqp);
  669. /* let the completion of the qp destroy free the qp */
  670. return ERR_PTR(err_code);
  671. }
  672. }
  673. init_completion(&iwqp->sq_drained);
  674. init_completion(&iwqp->rq_drained);
  675. return &iwqp->ibqp;
  676. error:
  677. i40iw_free_qp_resources(iwdev, iwqp, qp_num);
  678. return ERR_PTR(err_code);
  679. }
  680. /**
  681. * i40iw_query - query qp attributes
  682. * @ibqp: qp pointer
  683. * @attr: attributes pointer
  684. * @attr_mask: Not used
  685. * @init_attr: qp attributes to return
  686. */
  687. static int i40iw_query_qp(struct ib_qp *ibqp,
  688. struct ib_qp_attr *attr,
  689. int attr_mask,
  690. struct ib_qp_init_attr *init_attr)
  691. {
  692. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  693. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  694. attr->qp_state = iwqp->ibqp_state;
  695. attr->cur_qp_state = attr->qp_state;
  696. attr->qp_access_flags = 0;
  697. attr->cap.max_send_wr = qp->qp_uk.sq_size;
  698. attr->cap.max_recv_wr = qp->qp_uk.rq_size;
  699. attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  700. attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  701. attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  702. attr->port_num = 1;
  703. init_attr->event_handler = iwqp->ibqp.event_handler;
  704. init_attr->qp_context = iwqp->ibqp.qp_context;
  705. init_attr->send_cq = iwqp->ibqp.send_cq;
  706. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  707. init_attr->srq = iwqp->ibqp.srq;
  708. init_attr->cap = attr->cap;
  709. init_attr->port_num = 1;
  710. return 0;
  711. }
  712. /**
  713. * i40iw_hw_modify_qp - setup cqp for modify qp
  714. * @iwdev: iwarp device
  715. * @iwqp: qp ptr (user or kernel)
  716. * @info: info for modify qp
  717. * @wait: flag to wait or not for modify qp completion
  718. */
  719. void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
  720. struct i40iw_modify_qp_info *info, bool wait)
  721. {
  722. enum i40iw_status_code status;
  723. struct i40iw_cqp_request *cqp_request;
  724. struct cqp_commands_info *cqp_info;
  725. struct i40iw_modify_qp_info *m_info;
  726. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
  727. if (!cqp_request)
  728. return;
  729. cqp_info = &cqp_request->info;
  730. m_info = &cqp_info->in.u.qp_modify.info;
  731. memcpy(m_info, info, sizeof(*m_info));
  732. cqp_info->cqp_cmd = OP_QP_MODIFY;
  733. cqp_info->post_sq = 1;
  734. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  735. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  736. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  737. if (status)
  738. i40iw_pr_err("CQP-OP Modify QP fail");
  739. }
  740. /**
  741. * i40iw_modify_qp - modify qp request
  742. * @ibqp: qp's pointer for modify
  743. * @attr: access attributes
  744. * @attr_mask: state mask
  745. * @udata: user data
  746. */
  747. int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  748. int attr_mask, struct ib_udata *udata)
  749. {
  750. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  751. struct i40iw_device *iwdev = iwqp->iwdev;
  752. struct i40iw_qp_host_ctx_info *ctx_info;
  753. struct i40iwarp_offload_info *iwarp_info;
  754. struct i40iw_modify_qp_info info;
  755. u8 issue_modify_qp = 0;
  756. u8 dont_wait = 0;
  757. u32 err;
  758. unsigned long flags;
  759. memset(&info, 0, sizeof(info));
  760. ctx_info = &iwqp->ctx_info;
  761. iwarp_info = &iwqp->iwarp_info;
  762. spin_lock_irqsave(&iwqp->lock, flags);
  763. if (attr_mask & IB_QP_STATE) {
  764. if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
  765. err = -EINVAL;
  766. goto exit;
  767. }
  768. switch (attr->qp_state) {
  769. case IB_QPS_INIT:
  770. case IB_QPS_RTR:
  771. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
  772. err = -EINVAL;
  773. goto exit;
  774. }
  775. if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
  776. info.next_iwarp_state = I40IW_QP_STATE_IDLE;
  777. issue_modify_qp = 1;
  778. }
  779. break;
  780. case IB_QPS_RTS:
  781. if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
  782. (!iwqp->cm_id)) {
  783. err = -EINVAL;
  784. goto exit;
  785. }
  786. issue_modify_qp = 1;
  787. iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
  788. iwqp->hte_added = 1;
  789. info.next_iwarp_state = I40IW_QP_STATE_RTS;
  790. info.tcp_ctx_valid = true;
  791. info.ord_valid = true;
  792. info.arp_cache_idx_valid = true;
  793. info.cq_num_valid = true;
  794. break;
  795. case IB_QPS_SQD:
  796. if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
  797. err = 0;
  798. goto exit;
  799. }
  800. if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
  801. (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
  802. err = 0;
  803. goto exit;
  804. }
  805. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
  806. err = -EINVAL;
  807. goto exit;
  808. }
  809. info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
  810. issue_modify_qp = 1;
  811. break;
  812. case IB_QPS_SQE:
  813. if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
  814. err = -EINVAL;
  815. goto exit;
  816. }
  817. info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
  818. issue_modify_qp = 1;
  819. break;
  820. case IB_QPS_ERR:
  821. case IB_QPS_RESET:
  822. if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
  823. err = -EINVAL;
  824. goto exit;
  825. }
  826. if (iwqp->sc_qp.term_flags)
  827. i40iw_terminate_del_timer(&iwqp->sc_qp);
  828. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  829. if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
  830. iwdev->iw_status &&
  831. (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
  832. info.reset_tcp_conn = true;
  833. else
  834. dont_wait = 1;
  835. issue_modify_qp = 1;
  836. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  837. break;
  838. default:
  839. err = -EINVAL;
  840. goto exit;
  841. }
  842. iwqp->ibqp_state = attr->qp_state;
  843. if (issue_modify_qp)
  844. iwqp->iwarp_state = info.next_iwarp_state;
  845. else
  846. info.next_iwarp_state = iwqp->iwarp_state;
  847. }
  848. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  849. ctx_info->iwarp_info_valid = true;
  850. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  851. iwarp_info->wr_rdresp_en = true;
  852. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  853. iwarp_info->wr_rdresp_en = true;
  854. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  855. iwarp_info->rd_enable = true;
  856. if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
  857. iwarp_info->bind_en = true;
  858. if (iwqp->user_mode) {
  859. iwarp_info->rd_enable = true;
  860. iwarp_info->wr_rdresp_en = true;
  861. iwarp_info->priv_mode_en = false;
  862. }
  863. }
  864. if (ctx_info->iwarp_info_valid) {
  865. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  866. int ret;
  867. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  868. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  869. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  870. (u64 *)iwqp->host_ctx.va,
  871. ctx_info);
  872. if (ret) {
  873. i40iw_pr_err("setting QP context\n");
  874. err = -EINVAL;
  875. goto exit;
  876. }
  877. }
  878. spin_unlock_irqrestore(&iwqp->lock, flags);
  879. if (issue_modify_qp)
  880. i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
  881. if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
  882. if (dont_wait) {
  883. if (iwqp->cm_id && iwqp->hw_tcp_state) {
  884. spin_lock_irqsave(&iwqp->lock, flags);
  885. iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
  886. iwqp->last_aeq = I40IW_AE_RESET_SENT;
  887. spin_unlock_irqrestore(&iwqp->lock, flags);
  888. i40iw_cm_disconn(iwqp);
  889. }
  890. } else {
  891. spin_lock_irqsave(&iwqp->lock, flags);
  892. if (iwqp->cm_id) {
  893. if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
  894. iwqp->cm_id->add_ref(iwqp->cm_id);
  895. i40iw_schedule_cm_timer(iwqp->cm_node,
  896. (struct i40iw_puda_buf *)iwqp,
  897. I40IW_TIMER_TYPE_CLOSE, 1, 0);
  898. }
  899. }
  900. spin_unlock_irqrestore(&iwqp->lock, flags);
  901. }
  902. }
  903. return 0;
  904. exit:
  905. spin_unlock_irqrestore(&iwqp->lock, flags);
  906. return err;
  907. }
  908. /**
  909. * cq_free_resources - free up recources for cq
  910. * @iwdev: iwarp device
  911. * @iwcq: cq ptr
  912. */
  913. static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
  914. {
  915. struct i40iw_sc_cq *cq = &iwcq->sc_cq;
  916. if (!iwcq->user_mode)
  917. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
  918. i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
  919. }
  920. /**
  921. * i40iw_cq_wq_destroy - send cq destroy cqp
  922. * @iwdev: iwarp device
  923. * @cq: hardware control cq
  924. */
  925. void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
  926. {
  927. enum i40iw_status_code status;
  928. struct i40iw_cqp_request *cqp_request;
  929. struct cqp_commands_info *cqp_info;
  930. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  931. if (!cqp_request)
  932. return;
  933. cqp_info = &cqp_request->info;
  934. cqp_info->cqp_cmd = OP_CQ_DESTROY;
  935. cqp_info->post_sq = 1;
  936. cqp_info->in.u.cq_destroy.cq = cq;
  937. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  938. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  939. if (status)
  940. i40iw_pr_err("CQP-OP Destroy QP fail");
  941. }
  942. /**
  943. * i40iw_destroy_cq - destroy cq
  944. * @ib_cq: cq pointer
  945. */
  946. static int i40iw_destroy_cq(struct ib_cq *ib_cq)
  947. {
  948. struct i40iw_cq *iwcq;
  949. struct i40iw_device *iwdev;
  950. struct i40iw_sc_cq *cq;
  951. if (!ib_cq) {
  952. i40iw_pr_err("ib_cq == NULL\n");
  953. return 0;
  954. }
  955. iwcq = to_iwcq(ib_cq);
  956. iwdev = to_iwdev(ib_cq->device);
  957. cq = &iwcq->sc_cq;
  958. i40iw_cq_wq_destroy(iwdev, cq);
  959. cq_free_resources(iwdev, iwcq);
  960. kfree(iwcq);
  961. i40iw_rem_devusecount(iwdev);
  962. return 0;
  963. }
  964. /**
  965. * i40iw_create_cq - create cq
  966. * @ibdev: device pointer from stack
  967. * @attr: attributes for cq
  968. * @context: user context created during alloc
  969. * @udata: user data
  970. */
  971. static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
  972. const struct ib_cq_init_attr *attr,
  973. struct ib_ucontext *context,
  974. struct ib_udata *udata)
  975. {
  976. struct i40iw_device *iwdev = to_iwdev(ibdev);
  977. struct i40iw_cq *iwcq;
  978. struct i40iw_pbl *iwpbl;
  979. u32 cq_num = 0;
  980. struct i40iw_sc_cq *cq;
  981. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  982. struct i40iw_cq_init_info info;
  983. enum i40iw_status_code status;
  984. struct i40iw_cqp_request *cqp_request;
  985. struct cqp_commands_info *cqp_info;
  986. struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  987. unsigned long flags;
  988. int err_code;
  989. int entries = attr->cqe;
  990. if (iwdev->closing)
  991. return ERR_PTR(-ENODEV);
  992. if (entries > iwdev->max_cqe)
  993. return ERR_PTR(-EINVAL);
  994. iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
  995. if (!iwcq)
  996. return ERR_PTR(-ENOMEM);
  997. memset(&info, 0, sizeof(info));
  998. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
  999. iwdev->max_cq, &cq_num,
  1000. &iwdev->next_cq);
  1001. if (err_code)
  1002. goto error;
  1003. cq = &iwcq->sc_cq;
  1004. cq->back_cq = (void *)iwcq;
  1005. spin_lock_init(&iwcq->lock);
  1006. info.dev = dev;
  1007. ukinfo->cq_size = max(entries, 4);
  1008. ukinfo->cq_id = cq_num;
  1009. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  1010. info.ceqe_mask = 0;
  1011. if (attr->comp_vector < iwdev->ceqs_count)
  1012. info.ceq_id = attr->comp_vector;
  1013. info.ceq_id_valid = true;
  1014. info.ceqe_mask = 1;
  1015. info.type = I40IW_CQ_TYPE_IWARP;
  1016. if (context) {
  1017. struct i40iw_ucontext *ucontext;
  1018. struct i40iw_create_cq_req req;
  1019. struct i40iw_cq_mr *cqmr;
  1020. memset(&req, 0, sizeof(req));
  1021. iwcq->user_mode = true;
  1022. ucontext = to_ucontext(context);
  1023. if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req))) {
  1024. err_code = -EFAULT;
  1025. goto cq_free_resources;
  1026. }
  1027. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1028. iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
  1029. &ucontext->cq_reg_mem_list);
  1030. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1031. if (!iwpbl) {
  1032. err_code = -EPROTO;
  1033. goto cq_free_resources;
  1034. }
  1035. iwcq->iwpbl = iwpbl;
  1036. iwcq->cq_mem_size = 0;
  1037. cqmr = &iwpbl->cq_mr;
  1038. info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
  1039. if (iwpbl->pbl_allocated) {
  1040. info.virtual_map = true;
  1041. info.pbl_chunk_size = 1;
  1042. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1043. } else {
  1044. info.cq_base_pa = cqmr->cq_pbl.addr;
  1045. }
  1046. } else {
  1047. /* Kmode allocations */
  1048. int rsize;
  1049. int shadow;
  1050. rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
  1051. rsize = round_up(rsize, 256);
  1052. shadow = I40IW_SHADOW_AREA_SIZE << 3;
  1053. status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
  1054. rsize + shadow, 256);
  1055. if (status) {
  1056. err_code = -ENOMEM;
  1057. goto cq_free_resources;
  1058. }
  1059. ukinfo->cq_base = iwcq->kmem.va;
  1060. info.cq_base_pa = iwcq->kmem.pa;
  1061. info.shadow_area_pa = info.cq_base_pa + rsize;
  1062. ukinfo->shadow_area = iwcq->kmem.va + rsize;
  1063. }
  1064. if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
  1065. i40iw_pr_err("init cq fail\n");
  1066. err_code = -EPROTO;
  1067. goto cq_free_resources;
  1068. }
  1069. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1070. if (!cqp_request) {
  1071. err_code = -ENOMEM;
  1072. goto cq_free_resources;
  1073. }
  1074. cqp_info = &cqp_request->info;
  1075. cqp_info->cqp_cmd = OP_CQ_CREATE;
  1076. cqp_info->post_sq = 1;
  1077. cqp_info->in.u.cq_create.cq = cq;
  1078. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1079. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1080. if (status) {
  1081. i40iw_pr_err("CQP-OP Create QP fail");
  1082. err_code = -EPROTO;
  1083. goto cq_free_resources;
  1084. }
  1085. if (context) {
  1086. struct i40iw_create_cq_resp resp;
  1087. memset(&resp, 0, sizeof(resp));
  1088. resp.cq_id = info.cq_uk_init_info.cq_id;
  1089. resp.cq_size = info.cq_uk_init_info.cq_size;
  1090. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  1091. i40iw_pr_err("copy to user data\n");
  1092. err_code = -EPROTO;
  1093. goto cq_destroy;
  1094. }
  1095. }
  1096. i40iw_add_devusecount(iwdev);
  1097. return (struct ib_cq *)iwcq;
  1098. cq_destroy:
  1099. i40iw_cq_wq_destroy(iwdev, cq);
  1100. cq_free_resources:
  1101. cq_free_resources(iwdev, iwcq);
  1102. error:
  1103. kfree(iwcq);
  1104. return ERR_PTR(err_code);
  1105. }
  1106. /**
  1107. * i40iw_get_user_access - get hw access from IB access
  1108. * @acc: IB access to return hw access
  1109. */
  1110. static inline u16 i40iw_get_user_access(int acc)
  1111. {
  1112. u16 access = 0;
  1113. access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
  1114. access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
  1115. access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
  1116. access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
  1117. return access;
  1118. }
  1119. /**
  1120. * i40iw_free_stag - free stag resource
  1121. * @iwdev: iwarp device
  1122. * @stag: stag to free
  1123. */
  1124. static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
  1125. {
  1126. u32 stag_idx;
  1127. stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1128. i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
  1129. i40iw_rem_devusecount(iwdev);
  1130. }
  1131. /**
  1132. * i40iw_create_stag - create random stag
  1133. * @iwdev: iwarp device
  1134. */
  1135. static u32 i40iw_create_stag(struct i40iw_device *iwdev)
  1136. {
  1137. u32 stag = 0;
  1138. u32 stag_index = 0;
  1139. u32 next_stag_index;
  1140. u32 driver_key;
  1141. u32 random;
  1142. u8 consumer_key;
  1143. int ret;
  1144. get_random_bytes(&random, sizeof(random));
  1145. consumer_key = (u8)random;
  1146. driver_key = random & ~iwdev->mr_stagmask;
  1147. next_stag_index = (random & iwdev->mr_stagmask) >> 8;
  1148. next_stag_index %= iwdev->max_mr;
  1149. ret = i40iw_alloc_resource(iwdev,
  1150. iwdev->allocated_mrs, iwdev->max_mr,
  1151. &stag_index, &next_stag_index);
  1152. if (!ret) {
  1153. stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
  1154. stag |= driver_key;
  1155. stag += (u32)consumer_key;
  1156. i40iw_add_devusecount(iwdev);
  1157. }
  1158. return stag;
  1159. }
  1160. /**
  1161. * i40iw_next_pbl_addr - Get next pbl address
  1162. * @pbl: pointer to a pble
  1163. * @pinfo: info pointer
  1164. * @idx: index
  1165. */
  1166. static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
  1167. struct i40iw_pble_info **pinfo,
  1168. u32 *idx)
  1169. {
  1170. *idx += 1;
  1171. if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
  1172. return ++pbl;
  1173. *idx = 0;
  1174. (*pinfo)++;
  1175. return (u64 *)(*pinfo)->addr;
  1176. }
  1177. /**
  1178. * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
  1179. * @iwmr: iwmr for IB's user page addresses
  1180. * @pbl: ple pointer to save 1 level or 0 level pble
  1181. * @level: indicated level 0, 1 or 2
  1182. */
  1183. static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
  1184. u64 *pbl,
  1185. enum i40iw_pble_level level)
  1186. {
  1187. struct ib_umem *region = iwmr->region;
  1188. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1189. int chunk_pages, entry, i;
  1190. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1191. struct i40iw_pble_info *pinfo;
  1192. struct scatterlist *sg;
  1193. u64 pg_addr = 0;
  1194. u32 idx = 0;
  1195. pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
  1196. for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
  1197. chunk_pages = sg_dma_len(sg) >> region->page_shift;
  1198. if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
  1199. !iwpbl->qp_mr.sq_page)
  1200. iwpbl->qp_mr.sq_page = sg_page(sg);
  1201. for (i = 0; i < chunk_pages; i++) {
  1202. pg_addr = sg_dma_address(sg) +
  1203. (i << region->page_shift);
  1204. if ((entry + i) == 0)
  1205. *pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
  1206. else if (!(pg_addr & ~iwmr->page_msk))
  1207. *pbl = cpu_to_le64(pg_addr);
  1208. else
  1209. continue;
  1210. pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
  1211. }
  1212. }
  1213. }
  1214. /**
  1215. * i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values.
  1216. * @addr: virtual address
  1217. * @iwmr: mr pointer for this memory registration
  1218. */
  1219. static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
  1220. {
  1221. struct vm_area_struct *vma;
  1222. struct hstate *h;
  1223. down_read(&current->mm->mmap_sem);
  1224. vma = find_vma(current->mm, addr);
  1225. if (vma && is_vm_hugetlb_page(vma)) {
  1226. h = hstate_vma(vma);
  1227. if (huge_page_size(h) == 0x200000) {
  1228. iwmr->page_size = huge_page_size(h);
  1229. iwmr->page_msk = huge_page_mask(h);
  1230. }
  1231. }
  1232. up_read(&current->mm->mmap_sem);
  1233. }
  1234. /**
  1235. * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
  1236. * @arr: lvl1 pbl array
  1237. * @npages: page count
  1238. * pg_size: page size
  1239. *
  1240. */
  1241. static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
  1242. {
  1243. u32 pg_idx;
  1244. for (pg_idx = 0; pg_idx < npages; pg_idx++) {
  1245. if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
  1246. return false;
  1247. }
  1248. return true;
  1249. }
  1250. /**
  1251. * i40iw_check_mr_contiguous - check if MR is physically contiguous
  1252. * @palloc: pbl allocation struct
  1253. * pg_size: page size
  1254. */
  1255. static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
  1256. {
  1257. struct i40iw_pble_level2 *lvl2 = &palloc->level2;
  1258. struct i40iw_pble_info *leaf = lvl2->leaf;
  1259. u64 *arr = NULL;
  1260. u64 *start_addr = NULL;
  1261. int i;
  1262. bool ret;
  1263. if (palloc->level == I40IW_LEVEL_1) {
  1264. arr = (u64 *)palloc->level1.addr;
  1265. ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
  1266. return ret;
  1267. }
  1268. start_addr = (u64 *)leaf->addr;
  1269. for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
  1270. arr = (u64 *)leaf->addr;
  1271. if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
  1272. return false;
  1273. ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
  1274. if (!ret)
  1275. return false;
  1276. }
  1277. return true;
  1278. }
  1279. /**
  1280. * i40iw_setup_pbles - copy user pg address to pble's
  1281. * @iwdev: iwarp device
  1282. * @iwmr: mr pointer for this memory registration
  1283. * @use_pbles: flag if to use pble's
  1284. */
  1285. static int i40iw_setup_pbles(struct i40iw_device *iwdev,
  1286. struct i40iw_mr *iwmr,
  1287. bool use_pbles)
  1288. {
  1289. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1290. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1291. struct i40iw_pble_info *pinfo;
  1292. u64 *pbl;
  1293. enum i40iw_status_code status;
  1294. enum i40iw_pble_level level = I40IW_LEVEL_1;
  1295. if (use_pbles) {
  1296. mutex_lock(&iwdev->pbl_mutex);
  1297. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1298. mutex_unlock(&iwdev->pbl_mutex);
  1299. if (status)
  1300. return -ENOMEM;
  1301. iwpbl->pbl_allocated = true;
  1302. level = palloc->level;
  1303. pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
  1304. pbl = (u64 *)pinfo->addr;
  1305. } else {
  1306. pbl = iwmr->pgaddrmem;
  1307. }
  1308. i40iw_copy_user_pgaddrs(iwmr, pbl, level);
  1309. if (use_pbles)
  1310. iwmr->pgaddrmem[0] = *pbl;
  1311. return 0;
  1312. }
  1313. /**
  1314. * i40iw_handle_q_mem - handle memory for qp and cq
  1315. * @iwdev: iwarp device
  1316. * @req: information for q memory management
  1317. * @iwpbl: pble struct
  1318. * @use_pbles: flag to use pble
  1319. */
  1320. static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
  1321. struct i40iw_mem_reg_req *req,
  1322. struct i40iw_pbl *iwpbl,
  1323. bool use_pbles)
  1324. {
  1325. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1326. struct i40iw_mr *iwmr = iwpbl->iwmr;
  1327. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  1328. struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
  1329. struct i40iw_hmc_pble *hmc_p;
  1330. u64 *arr = iwmr->pgaddrmem;
  1331. u32 pg_size;
  1332. int err;
  1333. int total;
  1334. bool ret = true;
  1335. total = req->sq_pages + req->rq_pages + req->cq_pages;
  1336. pg_size = iwmr->page_size;
  1337. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1338. if (err)
  1339. return err;
  1340. if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
  1341. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1342. iwpbl->pbl_allocated = false;
  1343. return -ENOMEM;
  1344. }
  1345. if (use_pbles)
  1346. arr = (u64 *)palloc->level1.addr;
  1347. if (iwmr->type == IW_MEMREG_TYPE_QP) {
  1348. hmc_p = &qpmr->sq_pbl;
  1349. qpmr->shadow = (dma_addr_t)arr[total];
  1350. if (use_pbles) {
  1351. ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
  1352. if (ret)
  1353. ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
  1354. }
  1355. if (!ret) {
  1356. hmc_p->idx = palloc->level1.idx;
  1357. hmc_p = &qpmr->rq_pbl;
  1358. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  1359. } else {
  1360. hmc_p->addr = arr[0];
  1361. hmc_p = &qpmr->rq_pbl;
  1362. hmc_p->addr = arr[req->sq_pages];
  1363. }
  1364. } else { /* CQ */
  1365. hmc_p = &cqmr->cq_pbl;
  1366. cqmr->shadow = (dma_addr_t)arr[total];
  1367. if (use_pbles)
  1368. ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
  1369. if (!ret)
  1370. hmc_p->idx = palloc->level1.idx;
  1371. else
  1372. hmc_p->addr = arr[0];
  1373. }
  1374. if (use_pbles && ret) {
  1375. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1376. iwpbl->pbl_allocated = false;
  1377. }
  1378. return err;
  1379. }
  1380. /**
  1381. * i40iw_hw_alloc_stag - cqp command to allocate stag
  1382. * @iwdev: iwarp device
  1383. * @iwmr: iwarp mr pointer
  1384. */
  1385. static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
  1386. {
  1387. struct i40iw_allocate_stag_info *info;
  1388. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1389. enum i40iw_status_code status;
  1390. int err = 0;
  1391. struct i40iw_cqp_request *cqp_request;
  1392. struct cqp_commands_info *cqp_info;
  1393. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1394. if (!cqp_request)
  1395. return -ENOMEM;
  1396. cqp_info = &cqp_request->info;
  1397. info = &cqp_info->in.u.alloc_stag.info;
  1398. memset(info, 0, sizeof(*info));
  1399. info->page_size = PAGE_SIZE;
  1400. info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1401. info->pd_id = iwpd->sc_pd.pd_id;
  1402. info->total_len = iwmr->length;
  1403. info->remote_access = true;
  1404. cqp_info->cqp_cmd = OP_ALLOC_STAG;
  1405. cqp_info->post_sq = 1;
  1406. cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
  1407. cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
  1408. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1409. if (status) {
  1410. err = -ENOMEM;
  1411. i40iw_pr_err("CQP-OP MR Reg fail");
  1412. }
  1413. return err;
  1414. }
  1415. /**
  1416. * i40iw_alloc_mr - register stag for fast memory registration
  1417. * @pd: ibpd pointer
  1418. * @mr_type: memory for stag registrion
  1419. * @max_num_sg: man number of pages
  1420. */
  1421. static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
  1422. enum ib_mr_type mr_type,
  1423. u32 max_num_sg)
  1424. {
  1425. struct i40iw_pd *iwpd = to_iwpd(pd);
  1426. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1427. struct i40iw_pble_alloc *palloc;
  1428. struct i40iw_pbl *iwpbl;
  1429. struct i40iw_mr *iwmr;
  1430. enum i40iw_status_code status;
  1431. u32 stag;
  1432. int err_code = -ENOMEM;
  1433. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1434. if (!iwmr)
  1435. return ERR_PTR(-ENOMEM);
  1436. stag = i40iw_create_stag(iwdev);
  1437. if (!stag) {
  1438. err_code = -EOVERFLOW;
  1439. goto err;
  1440. }
  1441. stag &= ~I40IW_CQPSQ_STAG_KEY_MASK;
  1442. iwmr->stag = stag;
  1443. iwmr->ibmr.rkey = stag;
  1444. iwmr->ibmr.lkey = stag;
  1445. iwmr->ibmr.pd = pd;
  1446. iwmr->ibmr.device = pd->device;
  1447. iwpbl = &iwmr->iwpbl;
  1448. iwpbl->iwmr = iwmr;
  1449. iwmr->type = IW_MEMREG_TYPE_MEM;
  1450. palloc = &iwpbl->pble_alloc;
  1451. iwmr->page_cnt = max_num_sg;
  1452. mutex_lock(&iwdev->pbl_mutex);
  1453. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1454. mutex_unlock(&iwdev->pbl_mutex);
  1455. if (status)
  1456. goto err1;
  1457. if (palloc->level != I40IW_LEVEL_1)
  1458. goto err2;
  1459. err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
  1460. if (err_code)
  1461. goto err2;
  1462. iwpbl->pbl_allocated = true;
  1463. i40iw_add_pdusecount(iwpd);
  1464. return &iwmr->ibmr;
  1465. err2:
  1466. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1467. err1:
  1468. i40iw_free_stag(iwdev, stag);
  1469. err:
  1470. kfree(iwmr);
  1471. return ERR_PTR(err_code);
  1472. }
  1473. /**
  1474. * i40iw_set_page - populate pbl list for fmr
  1475. * @ibmr: ib mem to access iwarp mr pointer
  1476. * @addr: page dma address fro pbl list
  1477. */
  1478. static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
  1479. {
  1480. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1481. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1482. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1483. u64 *pbl;
  1484. if (unlikely(iwmr->npages == iwmr->page_cnt))
  1485. return -ENOMEM;
  1486. pbl = (u64 *)palloc->level1.addr;
  1487. pbl[iwmr->npages++] = cpu_to_le64(addr);
  1488. return 0;
  1489. }
  1490. /**
  1491. * i40iw_map_mr_sg - map of sg list for fmr
  1492. * @ibmr: ib mem to access iwarp mr pointer
  1493. * @sg: scatter gather list for fmr
  1494. * @sg_nents: number of sg pages
  1495. */
  1496. static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
  1497. int sg_nents, unsigned int *sg_offset)
  1498. {
  1499. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1500. iwmr->npages = 0;
  1501. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
  1502. }
  1503. /**
  1504. * i40iw_drain_sq - drain the send queue
  1505. * @ibqp: ib qp pointer
  1506. */
  1507. static void i40iw_drain_sq(struct ib_qp *ibqp)
  1508. {
  1509. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1510. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1511. if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  1512. wait_for_completion(&iwqp->sq_drained);
  1513. }
  1514. /**
  1515. * i40iw_drain_rq - drain the receive queue
  1516. * @ibqp: ib qp pointer
  1517. */
  1518. static void i40iw_drain_rq(struct ib_qp *ibqp)
  1519. {
  1520. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1521. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1522. if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  1523. wait_for_completion(&iwqp->rq_drained);
  1524. }
  1525. /**
  1526. * i40iw_hwreg_mr - send cqp command for memory registration
  1527. * @iwdev: iwarp device
  1528. * @iwmr: iwarp mr pointer
  1529. * @access: access for MR
  1530. */
  1531. static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
  1532. struct i40iw_mr *iwmr,
  1533. u16 access)
  1534. {
  1535. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1536. struct i40iw_reg_ns_stag_info *stag_info;
  1537. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1538. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1539. enum i40iw_status_code status;
  1540. int err = 0;
  1541. struct i40iw_cqp_request *cqp_request;
  1542. struct cqp_commands_info *cqp_info;
  1543. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1544. if (!cqp_request)
  1545. return -ENOMEM;
  1546. cqp_info = &cqp_request->info;
  1547. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  1548. memset(stag_info, 0, sizeof(*stag_info));
  1549. stag_info->va = (void *)(unsigned long)iwpbl->user_base;
  1550. stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1551. stag_info->stag_key = (u8)iwmr->stag;
  1552. stag_info->total_len = iwmr->length;
  1553. stag_info->access_rights = access;
  1554. stag_info->pd_id = iwpd->sc_pd.pd_id;
  1555. stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
  1556. stag_info->page_size = iwmr->page_size;
  1557. if (iwpbl->pbl_allocated) {
  1558. if (palloc->level == I40IW_LEVEL_1) {
  1559. stag_info->first_pm_pbl_index = palloc->level1.idx;
  1560. stag_info->chunk_size = 1;
  1561. } else {
  1562. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  1563. stag_info->chunk_size = 3;
  1564. }
  1565. } else {
  1566. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  1567. }
  1568. cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
  1569. cqp_info->post_sq = 1;
  1570. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
  1571. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  1572. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1573. if (status) {
  1574. err = -ENOMEM;
  1575. i40iw_pr_err("CQP-OP MR Reg fail");
  1576. }
  1577. return err;
  1578. }
  1579. /**
  1580. * i40iw_reg_user_mr - Register a user memory region
  1581. * @pd: ptr of pd
  1582. * @start: virtual start address
  1583. * @length: length of mr
  1584. * @virt: virtual address
  1585. * @acc: access of mr
  1586. * @udata: user data
  1587. */
  1588. static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
  1589. u64 start,
  1590. u64 length,
  1591. u64 virt,
  1592. int acc,
  1593. struct ib_udata *udata)
  1594. {
  1595. struct i40iw_pd *iwpd = to_iwpd(pd);
  1596. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1597. struct i40iw_ucontext *ucontext;
  1598. struct i40iw_pble_alloc *palloc;
  1599. struct i40iw_pbl *iwpbl;
  1600. struct i40iw_mr *iwmr;
  1601. struct ib_umem *region;
  1602. struct i40iw_mem_reg_req req;
  1603. u64 pbl_depth = 0;
  1604. u32 stag = 0;
  1605. u16 access;
  1606. u64 region_length;
  1607. bool use_pbles = false;
  1608. unsigned long flags;
  1609. int err = -ENOSYS;
  1610. int ret;
  1611. int pg_shift;
  1612. if (iwdev->closing)
  1613. return ERR_PTR(-ENODEV);
  1614. if (length > I40IW_MAX_MR_SIZE)
  1615. return ERR_PTR(-EINVAL);
  1616. region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
  1617. if (IS_ERR(region))
  1618. return (struct ib_mr *)region;
  1619. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  1620. ib_umem_release(region);
  1621. return ERR_PTR(-EFAULT);
  1622. }
  1623. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1624. if (!iwmr) {
  1625. ib_umem_release(region);
  1626. return ERR_PTR(-ENOMEM);
  1627. }
  1628. iwpbl = &iwmr->iwpbl;
  1629. iwpbl->iwmr = iwmr;
  1630. iwmr->region = region;
  1631. iwmr->ibmr.pd = pd;
  1632. iwmr->ibmr.device = pd->device;
  1633. ucontext = to_ucontext(pd->uobject->context);
  1634. iwmr->page_size = PAGE_SIZE;
  1635. iwmr->page_msk = PAGE_MASK;
  1636. if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
  1637. i40iw_set_hugetlb_values(start, iwmr);
  1638. region_length = region->length + (start & (iwmr->page_size - 1));
  1639. pg_shift = ffs(iwmr->page_size) - 1;
  1640. pbl_depth = region_length >> pg_shift;
  1641. pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0;
  1642. iwmr->length = region->length;
  1643. iwpbl->user_base = virt;
  1644. palloc = &iwpbl->pble_alloc;
  1645. iwmr->type = req.reg_type;
  1646. iwmr->page_cnt = (u32)pbl_depth;
  1647. switch (req.reg_type) {
  1648. case IW_MEMREG_TYPE_QP:
  1649. use_pbles = ((req.sq_pages + req.rq_pages) > 2);
  1650. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1651. if (err)
  1652. goto error;
  1653. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1654. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  1655. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1656. break;
  1657. case IW_MEMREG_TYPE_CQ:
  1658. use_pbles = (req.cq_pages > 1);
  1659. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1660. if (err)
  1661. goto error;
  1662. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1663. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  1664. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1665. break;
  1666. case IW_MEMREG_TYPE_MEM:
  1667. use_pbles = (iwmr->page_cnt != 1);
  1668. access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1669. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1670. if (err)
  1671. goto error;
  1672. if (use_pbles) {
  1673. ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
  1674. if (ret) {
  1675. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1676. iwpbl->pbl_allocated = false;
  1677. }
  1678. }
  1679. access |= i40iw_get_user_access(acc);
  1680. stag = i40iw_create_stag(iwdev);
  1681. if (!stag) {
  1682. err = -ENOMEM;
  1683. goto error;
  1684. }
  1685. iwmr->stag = stag;
  1686. iwmr->ibmr.rkey = stag;
  1687. iwmr->ibmr.lkey = stag;
  1688. err = i40iw_hwreg_mr(iwdev, iwmr, access);
  1689. if (err) {
  1690. i40iw_free_stag(iwdev, stag);
  1691. goto error;
  1692. }
  1693. break;
  1694. default:
  1695. goto error;
  1696. }
  1697. iwmr->type = req.reg_type;
  1698. if (req.reg_type == IW_MEMREG_TYPE_MEM)
  1699. i40iw_add_pdusecount(iwpd);
  1700. return &iwmr->ibmr;
  1701. error:
  1702. if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
  1703. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1704. ib_umem_release(region);
  1705. kfree(iwmr);
  1706. return ERR_PTR(err);
  1707. }
  1708. /**
  1709. * i40iw_reg_phys_mr - register kernel physical memory
  1710. * @pd: ibpd pointer
  1711. * @addr: physical address of memory to register
  1712. * @size: size of memory to register
  1713. * @acc: Access rights
  1714. * @iova_start: start of virtual address for physical buffers
  1715. */
  1716. struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
  1717. u64 addr,
  1718. u64 size,
  1719. int acc,
  1720. u64 *iova_start)
  1721. {
  1722. struct i40iw_pd *iwpd = to_iwpd(pd);
  1723. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1724. struct i40iw_pbl *iwpbl;
  1725. struct i40iw_mr *iwmr;
  1726. enum i40iw_status_code status;
  1727. u32 stag;
  1728. u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1729. int ret;
  1730. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1731. if (!iwmr)
  1732. return ERR_PTR(-ENOMEM);
  1733. iwmr->ibmr.pd = pd;
  1734. iwmr->ibmr.device = pd->device;
  1735. iwpbl = &iwmr->iwpbl;
  1736. iwpbl->iwmr = iwmr;
  1737. iwmr->type = IW_MEMREG_TYPE_MEM;
  1738. iwpbl->user_base = *iova_start;
  1739. stag = i40iw_create_stag(iwdev);
  1740. if (!stag) {
  1741. ret = -EOVERFLOW;
  1742. goto err;
  1743. }
  1744. access |= i40iw_get_user_access(acc);
  1745. iwmr->stag = stag;
  1746. iwmr->ibmr.rkey = stag;
  1747. iwmr->ibmr.lkey = stag;
  1748. iwmr->page_cnt = 1;
  1749. iwmr->pgaddrmem[0] = addr;
  1750. iwmr->length = size;
  1751. status = i40iw_hwreg_mr(iwdev, iwmr, access);
  1752. if (status) {
  1753. i40iw_free_stag(iwdev, stag);
  1754. ret = -ENOMEM;
  1755. goto err;
  1756. }
  1757. i40iw_add_pdusecount(iwpd);
  1758. return &iwmr->ibmr;
  1759. err:
  1760. kfree(iwmr);
  1761. return ERR_PTR(ret);
  1762. }
  1763. /**
  1764. * i40iw_get_dma_mr - register physical mem
  1765. * @pd: ptr of pd
  1766. * @acc: access for memory
  1767. */
  1768. static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
  1769. {
  1770. u64 kva = 0;
  1771. return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
  1772. }
  1773. /**
  1774. * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
  1775. * @iwmr: iwmr for IB's user page addresses
  1776. * @ucontext: ptr to user context
  1777. */
  1778. static void i40iw_del_memlist(struct i40iw_mr *iwmr,
  1779. struct i40iw_ucontext *ucontext)
  1780. {
  1781. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1782. unsigned long flags;
  1783. switch (iwmr->type) {
  1784. case IW_MEMREG_TYPE_CQ:
  1785. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1786. if (!list_empty(&ucontext->cq_reg_mem_list))
  1787. list_del(&iwpbl->list);
  1788. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1789. break;
  1790. case IW_MEMREG_TYPE_QP:
  1791. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1792. if (!list_empty(&ucontext->qp_reg_mem_list))
  1793. list_del(&iwpbl->list);
  1794. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1795. break;
  1796. default:
  1797. break;
  1798. }
  1799. }
  1800. /**
  1801. * i40iw_dereg_mr - deregister mr
  1802. * @ib_mr: mr ptr for dereg
  1803. */
  1804. static int i40iw_dereg_mr(struct ib_mr *ib_mr)
  1805. {
  1806. struct ib_pd *ibpd = ib_mr->pd;
  1807. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  1808. struct i40iw_mr *iwmr = to_iwmr(ib_mr);
  1809. struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
  1810. enum i40iw_status_code status;
  1811. struct i40iw_dealloc_stag_info *info;
  1812. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1813. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1814. struct i40iw_cqp_request *cqp_request;
  1815. struct cqp_commands_info *cqp_info;
  1816. u32 stag_idx;
  1817. if (iwmr->region)
  1818. ib_umem_release(iwmr->region);
  1819. if (iwmr->type != IW_MEMREG_TYPE_MEM) {
  1820. if (ibpd->uobject) {
  1821. struct i40iw_ucontext *ucontext;
  1822. ucontext = to_ucontext(ibpd->uobject->context);
  1823. i40iw_del_memlist(iwmr, ucontext);
  1824. }
  1825. if (iwpbl->pbl_allocated && iwmr->type != IW_MEMREG_TYPE_QP)
  1826. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1827. kfree(iwmr);
  1828. return 0;
  1829. }
  1830. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1831. if (!cqp_request)
  1832. return -ENOMEM;
  1833. cqp_info = &cqp_request->info;
  1834. info = &cqp_info->in.u.dealloc_stag.info;
  1835. memset(info, 0, sizeof(*info));
  1836. info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
  1837. info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
  1838. stag_idx = info->stag_idx;
  1839. info->mr = true;
  1840. if (iwpbl->pbl_allocated)
  1841. info->dealloc_pbl = true;
  1842. cqp_info->cqp_cmd = OP_DEALLOC_STAG;
  1843. cqp_info->post_sq = 1;
  1844. cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
  1845. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  1846. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1847. if (status)
  1848. i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
  1849. i40iw_rem_pdusecount(iwpd, iwdev);
  1850. i40iw_free_stag(iwdev, iwmr->stag);
  1851. if (iwpbl->pbl_allocated)
  1852. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1853. kfree(iwmr);
  1854. return 0;
  1855. }
  1856. /**
  1857. * i40iw_show_rev
  1858. */
  1859. static ssize_t i40iw_show_rev(struct device *dev,
  1860. struct device_attribute *attr, char *buf)
  1861. {
  1862. struct i40iw_ib_device *iwibdev = container_of(dev,
  1863. struct i40iw_ib_device,
  1864. ibdev.dev);
  1865. u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
  1866. return sprintf(buf, "%x\n", hw_rev);
  1867. }
  1868. /**
  1869. * i40iw_show_hca
  1870. */
  1871. static ssize_t i40iw_show_hca(struct device *dev,
  1872. struct device_attribute *attr, char *buf)
  1873. {
  1874. return sprintf(buf, "I40IW\n");
  1875. }
  1876. /**
  1877. * i40iw_show_board
  1878. */
  1879. static ssize_t i40iw_show_board(struct device *dev,
  1880. struct device_attribute *attr,
  1881. char *buf)
  1882. {
  1883. return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
  1884. }
  1885. static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
  1886. static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
  1887. static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
  1888. static struct device_attribute *i40iw_dev_attributes[] = {
  1889. &dev_attr_hw_rev,
  1890. &dev_attr_hca_type,
  1891. &dev_attr_board_id
  1892. };
  1893. /**
  1894. * i40iw_copy_sg_list - copy sg list for qp
  1895. * @sg_list: copied into sg_list
  1896. * @sgl: copy from sgl
  1897. * @num_sges: count of sg entries
  1898. */
  1899. static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
  1900. {
  1901. unsigned int i;
  1902. for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
  1903. sg_list[i].tag_off = sgl[i].addr;
  1904. sg_list[i].len = sgl[i].length;
  1905. sg_list[i].stag = sgl[i].lkey;
  1906. }
  1907. }
  1908. /**
  1909. * i40iw_post_send - kernel application wr
  1910. * @ibqp: qp ptr for wr
  1911. * @ib_wr: work request ptr
  1912. * @bad_wr: return of bad wr if err
  1913. */
  1914. static int i40iw_post_send(struct ib_qp *ibqp,
  1915. struct ib_send_wr *ib_wr,
  1916. struct ib_send_wr **bad_wr)
  1917. {
  1918. struct i40iw_qp *iwqp;
  1919. struct i40iw_qp_uk *ukqp;
  1920. struct i40iw_post_sq_info info;
  1921. enum i40iw_status_code ret;
  1922. int err = 0;
  1923. unsigned long flags;
  1924. bool inv_stag;
  1925. iwqp = (struct i40iw_qp *)ibqp;
  1926. ukqp = &iwqp->sc_qp.qp_uk;
  1927. spin_lock_irqsave(&iwqp->lock, flags);
  1928. while (ib_wr) {
  1929. inv_stag = false;
  1930. memset(&info, 0, sizeof(info));
  1931. info.wr_id = (u64)(ib_wr->wr_id);
  1932. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  1933. info.signaled = true;
  1934. if (ib_wr->send_flags & IB_SEND_FENCE)
  1935. info.read_fence = true;
  1936. switch (ib_wr->opcode) {
  1937. case IB_WR_SEND:
  1938. /* fall-through */
  1939. case IB_WR_SEND_WITH_INV:
  1940. if (ib_wr->opcode == IB_WR_SEND) {
  1941. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1942. info.op_type = I40IW_OP_TYPE_SEND_SOL;
  1943. else
  1944. info.op_type = I40IW_OP_TYPE_SEND;
  1945. } else {
  1946. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1947. info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
  1948. else
  1949. info.op_type = I40IW_OP_TYPE_SEND_INV;
  1950. }
  1951. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1952. info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1953. info.op.inline_send.len = ib_wr->sg_list[0].length;
  1954. ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1955. } else {
  1956. info.op.send.num_sges = ib_wr->num_sge;
  1957. info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
  1958. ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1959. }
  1960. if (ret) {
  1961. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1962. err = -ENOMEM;
  1963. else
  1964. err = -EINVAL;
  1965. }
  1966. break;
  1967. case IB_WR_RDMA_WRITE:
  1968. info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
  1969. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1970. info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1971. info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
  1972. info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1973. info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1974. info.op.inline_rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1975. ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
  1976. } else {
  1977. info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
  1978. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  1979. info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1980. info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1981. info.op.rdma_write.rem_addr.len = ib_wr->sg_list->length;
  1982. ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
  1983. }
  1984. if (ret) {
  1985. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1986. err = -ENOMEM;
  1987. else
  1988. err = -EINVAL;
  1989. }
  1990. break;
  1991. case IB_WR_RDMA_READ_WITH_INV:
  1992. inv_stag = true;
  1993. /* fall-through*/
  1994. case IB_WR_RDMA_READ:
  1995. if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
  1996. err = -EINVAL;
  1997. break;
  1998. }
  1999. info.op_type = I40IW_OP_TYPE_RDMA_READ;
  2000. info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  2001. info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  2002. info.op.rdma_read.rem_addr.len = ib_wr->sg_list->length;
  2003. info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
  2004. info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
  2005. info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
  2006. ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
  2007. if (ret) {
  2008. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  2009. err = -ENOMEM;
  2010. else
  2011. err = -EINVAL;
  2012. }
  2013. break;
  2014. case IB_WR_LOCAL_INV:
  2015. info.op_type = I40IW_OP_TYPE_INV_STAG;
  2016. info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
  2017. ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
  2018. if (ret)
  2019. err = -ENOMEM;
  2020. break;
  2021. case IB_WR_REG_MR:
  2022. {
  2023. struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
  2024. int flags = reg_wr(ib_wr)->access;
  2025. struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
  2026. struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
  2027. struct i40iw_fast_reg_stag_info info;
  2028. memset(&info, 0, sizeof(info));
  2029. info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
  2030. info.access_rights |= i40iw_get_user_access(flags);
  2031. info.stag_key = reg_wr(ib_wr)->key & 0xff;
  2032. info.stag_idx = reg_wr(ib_wr)->key >> 8;
  2033. info.page_size = reg_wr(ib_wr)->mr->page_size;
  2034. info.wr_id = ib_wr->wr_id;
  2035. info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
  2036. info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
  2037. info.total_len = iwmr->ibmr.length;
  2038. info.reg_addr_pa = *(u64 *)palloc->level1.addr;
  2039. info.first_pm_pbl_index = palloc->level1.idx;
  2040. info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
  2041. info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
  2042. if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
  2043. info.chunk_size = 1;
  2044. ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
  2045. if (ret)
  2046. err = -ENOMEM;
  2047. break;
  2048. }
  2049. default:
  2050. err = -EINVAL;
  2051. i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
  2052. ib_wr->opcode);
  2053. break;
  2054. }
  2055. if (err)
  2056. break;
  2057. ib_wr = ib_wr->next;
  2058. }
  2059. if (err)
  2060. *bad_wr = ib_wr;
  2061. else
  2062. ukqp->ops.iw_qp_post_wr(ukqp);
  2063. spin_unlock_irqrestore(&iwqp->lock, flags);
  2064. return err;
  2065. }
  2066. /**
  2067. * i40iw_post_recv - post receive wr for kernel application
  2068. * @ibqp: ib qp pointer
  2069. * @ib_wr: work request for receive
  2070. * @bad_wr: bad wr caused an error
  2071. */
  2072. static int i40iw_post_recv(struct ib_qp *ibqp,
  2073. struct ib_recv_wr *ib_wr,
  2074. struct ib_recv_wr **bad_wr)
  2075. {
  2076. struct i40iw_qp *iwqp;
  2077. struct i40iw_qp_uk *ukqp;
  2078. struct i40iw_post_rq_info post_recv;
  2079. struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
  2080. enum i40iw_status_code ret = 0;
  2081. unsigned long flags;
  2082. int err = 0;
  2083. iwqp = (struct i40iw_qp *)ibqp;
  2084. ukqp = &iwqp->sc_qp.qp_uk;
  2085. memset(&post_recv, 0, sizeof(post_recv));
  2086. spin_lock_irqsave(&iwqp->lock, flags);
  2087. while (ib_wr) {
  2088. post_recv.num_sges = ib_wr->num_sge;
  2089. post_recv.wr_id = ib_wr->wr_id;
  2090. i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
  2091. post_recv.sg_list = sg_list;
  2092. ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
  2093. if (ret) {
  2094. i40iw_pr_err(" post_recv err %d\n", ret);
  2095. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  2096. err = -ENOMEM;
  2097. else
  2098. err = -EINVAL;
  2099. *bad_wr = ib_wr;
  2100. goto out;
  2101. }
  2102. ib_wr = ib_wr->next;
  2103. }
  2104. out:
  2105. spin_unlock_irqrestore(&iwqp->lock, flags);
  2106. return err;
  2107. }
  2108. /**
  2109. * i40iw_poll_cq - poll cq for completion (kernel apps)
  2110. * @ibcq: cq to poll
  2111. * @num_entries: number of entries to poll
  2112. * @entry: wr of entry completed
  2113. */
  2114. static int i40iw_poll_cq(struct ib_cq *ibcq,
  2115. int num_entries,
  2116. struct ib_wc *entry)
  2117. {
  2118. struct i40iw_cq *iwcq;
  2119. int cqe_count = 0;
  2120. struct i40iw_cq_poll_info cq_poll_info;
  2121. enum i40iw_status_code ret;
  2122. struct i40iw_cq_uk *ukcq;
  2123. struct i40iw_sc_qp *qp;
  2124. struct i40iw_qp *iwqp;
  2125. unsigned long flags;
  2126. iwcq = (struct i40iw_cq *)ibcq;
  2127. ukcq = &iwcq->sc_cq.cq_uk;
  2128. spin_lock_irqsave(&iwcq->lock, flags);
  2129. while (cqe_count < num_entries) {
  2130. ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
  2131. if (ret == I40IW_ERR_QUEUE_EMPTY) {
  2132. break;
  2133. } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
  2134. continue;
  2135. } else if (ret) {
  2136. if (!cqe_count)
  2137. cqe_count = -1;
  2138. break;
  2139. }
  2140. entry->wc_flags = 0;
  2141. entry->wr_id = cq_poll_info.wr_id;
  2142. if (cq_poll_info.error) {
  2143. entry->status = IB_WC_WR_FLUSH_ERR;
  2144. entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
  2145. } else {
  2146. entry->status = IB_WC_SUCCESS;
  2147. }
  2148. switch (cq_poll_info.op_type) {
  2149. case I40IW_OP_TYPE_RDMA_WRITE:
  2150. entry->opcode = IB_WC_RDMA_WRITE;
  2151. break;
  2152. case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
  2153. case I40IW_OP_TYPE_RDMA_READ:
  2154. entry->opcode = IB_WC_RDMA_READ;
  2155. break;
  2156. case I40IW_OP_TYPE_SEND_SOL:
  2157. case I40IW_OP_TYPE_SEND_SOL_INV:
  2158. case I40IW_OP_TYPE_SEND_INV:
  2159. case I40IW_OP_TYPE_SEND:
  2160. entry->opcode = IB_WC_SEND;
  2161. break;
  2162. case I40IW_OP_TYPE_REC:
  2163. entry->opcode = IB_WC_RECV;
  2164. break;
  2165. default:
  2166. entry->opcode = IB_WC_RECV;
  2167. break;
  2168. }
  2169. entry->ex.imm_data = 0;
  2170. qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
  2171. entry->qp = (struct ib_qp *)qp->back_qp;
  2172. entry->src_qp = cq_poll_info.qp_id;
  2173. iwqp = (struct i40iw_qp *)qp->back_qp;
  2174. if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
  2175. if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  2176. complete(&iwqp->sq_drained);
  2177. if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  2178. complete(&iwqp->rq_drained);
  2179. }
  2180. entry->byte_len = cq_poll_info.bytes_xfered;
  2181. entry++;
  2182. cqe_count++;
  2183. }
  2184. spin_unlock_irqrestore(&iwcq->lock, flags);
  2185. return cqe_count;
  2186. }
  2187. /**
  2188. * i40iw_req_notify_cq - arm cq kernel application
  2189. * @ibcq: cq to arm
  2190. * @notify_flags: notofication flags
  2191. */
  2192. static int i40iw_req_notify_cq(struct ib_cq *ibcq,
  2193. enum ib_cq_notify_flags notify_flags)
  2194. {
  2195. struct i40iw_cq *iwcq;
  2196. struct i40iw_cq_uk *ukcq;
  2197. unsigned long flags;
  2198. enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
  2199. iwcq = (struct i40iw_cq *)ibcq;
  2200. ukcq = &iwcq->sc_cq.cq_uk;
  2201. if (notify_flags == IB_CQ_SOLICITED)
  2202. cq_notify = IW_CQ_COMPL_SOLICITED;
  2203. spin_lock_irqsave(&iwcq->lock, flags);
  2204. ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
  2205. spin_unlock_irqrestore(&iwcq->lock, flags);
  2206. return 0;
  2207. }
  2208. /**
  2209. * i40iw_port_immutable - return port's immutable data
  2210. * @ibdev: ib dev struct
  2211. * @port_num: port number
  2212. * @immutable: immutable data for the port return
  2213. */
  2214. static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
  2215. struct ib_port_immutable *immutable)
  2216. {
  2217. struct ib_port_attr attr;
  2218. int err;
  2219. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  2220. err = ib_query_port(ibdev, port_num, &attr);
  2221. if (err)
  2222. return err;
  2223. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2224. immutable->gid_tbl_len = attr.gid_tbl_len;
  2225. return 0;
  2226. }
  2227. static const char * const i40iw_hw_stat_names[] = {
  2228. // 32bit names
  2229. [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
  2230. [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
  2231. [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
  2232. [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
  2233. [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
  2234. [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
  2235. [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
  2236. [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
  2237. [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
  2238. // 64bit names
  2239. [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2240. "ip4InOctets",
  2241. [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2242. "ip4InPkts",
  2243. [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2244. "ip4InReasmRqd",
  2245. [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2246. "ip4InMcastPkts",
  2247. [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2248. "ip4OutOctets",
  2249. [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2250. "ip4OutPkts",
  2251. [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2252. "ip4OutSegRqd",
  2253. [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2254. "ip4OutMcastPkts",
  2255. [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2256. "ip6InOctets",
  2257. [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2258. "ip6InPkts",
  2259. [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2260. "ip6InReasmRqd",
  2261. [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2262. "ip6InMcastPkts",
  2263. [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2264. "ip6OutOctets",
  2265. [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2266. "ip6OutPkts",
  2267. [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2268. "ip6OutSegRqd",
  2269. [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2270. "ip6OutMcastPkts",
  2271. [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2272. "tcpInSegs",
  2273. [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
  2274. "tcpOutSegs",
  2275. [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2276. "iwInRdmaReads",
  2277. [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2278. "iwInRdmaSends",
  2279. [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2280. "iwInRdmaWrites",
  2281. [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2282. "iwOutRdmaReads",
  2283. [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2284. "iwOutRdmaSends",
  2285. [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2286. "iwOutRdmaWrites",
  2287. [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
  2288. "iwRdmaBnd",
  2289. [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
  2290. "iwRdmaInv"
  2291. };
  2292. static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str)
  2293. {
  2294. u32 firmware_version = I40IW_FW_VERSION;
  2295. snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u", firmware_version,
  2296. (firmware_version & 0x000000ff));
  2297. }
  2298. /**
  2299. * i40iw_alloc_hw_stats - Allocate a hw stats structure
  2300. * @ibdev: device pointer from stack
  2301. * @port_num: port number
  2302. */
  2303. static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
  2304. u8 port_num)
  2305. {
  2306. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2307. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2308. int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
  2309. I40IW_HW_STAT_INDEX_MAX_64;
  2310. unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
  2311. BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
  2312. (I40IW_HW_STAT_INDEX_MAX_32 +
  2313. I40IW_HW_STAT_INDEX_MAX_64));
  2314. /*
  2315. * PFs get the default update lifespan, but VFs only update once
  2316. * per second
  2317. */
  2318. if (!dev->is_pf)
  2319. lifespan = 1000;
  2320. return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
  2321. lifespan);
  2322. }
  2323. /**
  2324. * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
  2325. * @ibdev: device pointer from stack
  2326. * @stats: stats pointer from stack
  2327. * @port_num: port number
  2328. * @index: which hw counter the stack is requesting we update
  2329. */
  2330. static int i40iw_get_hw_stats(struct ib_device *ibdev,
  2331. struct rdma_hw_stats *stats,
  2332. u8 port_num, int index)
  2333. {
  2334. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2335. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2336. struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
  2337. struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
  2338. if (dev->is_pf) {
  2339. i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
  2340. } else {
  2341. if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
  2342. return -ENOSYS;
  2343. }
  2344. memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
  2345. return stats->num_counters;
  2346. }
  2347. /**
  2348. * i40iw_query_gid - Query port GID
  2349. * @ibdev: device pointer from stack
  2350. * @port: port number
  2351. * @index: Entry index
  2352. * @gid: Global ID
  2353. */
  2354. static int i40iw_query_gid(struct ib_device *ibdev,
  2355. u8 port,
  2356. int index,
  2357. union ib_gid *gid)
  2358. {
  2359. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2360. memset(gid->raw, 0, sizeof(gid->raw));
  2361. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  2362. return 0;
  2363. }
  2364. /**
  2365. * i40iw_modify_port Modify port properties
  2366. * @ibdev: device pointer from stack
  2367. * @port: port number
  2368. * @port_modify_mask: mask for port modifications
  2369. * @props: port properties
  2370. */
  2371. static int i40iw_modify_port(struct ib_device *ibdev,
  2372. u8 port,
  2373. int port_modify_mask,
  2374. struct ib_port_modify *props)
  2375. {
  2376. return -ENOSYS;
  2377. }
  2378. /**
  2379. * i40iw_query_pkey - Query partition key
  2380. * @ibdev: device pointer from stack
  2381. * @port: port number
  2382. * @index: index of pkey
  2383. * @pkey: pointer to store the pkey
  2384. */
  2385. static int i40iw_query_pkey(struct ib_device *ibdev,
  2386. u8 port,
  2387. u16 index,
  2388. u16 *pkey)
  2389. {
  2390. *pkey = 0;
  2391. return 0;
  2392. }
  2393. /**
  2394. * i40iw_create_ah - create address handle
  2395. * @ibpd: ptr of pd
  2396. * @ah_attr: address handle attributes
  2397. */
  2398. static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
  2399. struct rdma_ah_attr *attr,
  2400. struct ib_udata *udata)
  2401. {
  2402. return ERR_PTR(-ENOSYS);
  2403. }
  2404. /**
  2405. * i40iw_destroy_ah - Destroy address handle
  2406. * @ah: pointer to address handle
  2407. */
  2408. static int i40iw_destroy_ah(struct ib_ah *ah)
  2409. {
  2410. return -ENOSYS;
  2411. }
  2412. /**
  2413. * i40iw_init_rdma_device - initialization of iwarp device
  2414. * @iwdev: iwarp device
  2415. */
  2416. static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
  2417. {
  2418. struct i40iw_ib_device *iwibdev;
  2419. struct net_device *netdev = iwdev->netdev;
  2420. struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
  2421. iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
  2422. if (!iwibdev) {
  2423. i40iw_pr_err("iwdev == NULL\n");
  2424. return NULL;
  2425. }
  2426. strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
  2427. iwibdev->ibdev.owner = THIS_MODULE;
  2428. iwdev->iwibdev = iwibdev;
  2429. iwibdev->iwdev = iwdev;
  2430. iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
  2431. ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
  2432. iwibdev->ibdev.uverbs_cmd_mask =
  2433. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2434. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2435. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2436. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2437. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2438. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2439. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2440. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2441. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2442. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2443. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  2444. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2445. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2446. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2447. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  2448. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  2449. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  2450. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2451. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  2452. (1ull << IB_USER_VERBS_CMD_POST_SEND);
  2453. iwibdev->ibdev.phys_port_cnt = 1;
  2454. iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
  2455. iwibdev->ibdev.dev.parent = &pcidev->dev;
  2456. iwibdev->ibdev.query_port = i40iw_query_port;
  2457. iwibdev->ibdev.modify_port = i40iw_modify_port;
  2458. iwibdev->ibdev.query_pkey = i40iw_query_pkey;
  2459. iwibdev->ibdev.query_gid = i40iw_query_gid;
  2460. iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
  2461. iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
  2462. iwibdev->ibdev.mmap = i40iw_mmap;
  2463. iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
  2464. iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
  2465. iwibdev->ibdev.create_qp = i40iw_create_qp;
  2466. iwibdev->ibdev.modify_qp = i40iw_modify_qp;
  2467. iwibdev->ibdev.query_qp = i40iw_query_qp;
  2468. iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
  2469. iwibdev->ibdev.create_cq = i40iw_create_cq;
  2470. iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
  2471. iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
  2472. iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
  2473. iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
  2474. iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
  2475. iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
  2476. iwibdev->ibdev.query_device = i40iw_query_device;
  2477. iwibdev->ibdev.create_ah = i40iw_create_ah;
  2478. iwibdev->ibdev.destroy_ah = i40iw_destroy_ah;
  2479. iwibdev->ibdev.drain_sq = i40iw_drain_sq;
  2480. iwibdev->ibdev.drain_rq = i40iw_drain_rq;
  2481. iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
  2482. iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
  2483. iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
  2484. if (!iwibdev->ibdev.iwcm) {
  2485. ib_dealloc_device(&iwibdev->ibdev);
  2486. return NULL;
  2487. }
  2488. iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
  2489. iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
  2490. iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
  2491. iwibdev->ibdev.iwcm->connect = i40iw_connect;
  2492. iwibdev->ibdev.iwcm->accept = i40iw_accept;
  2493. iwibdev->ibdev.iwcm->reject = i40iw_reject;
  2494. iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
  2495. iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
  2496. memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
  2497. sizeof(iwibdev->ibdev.iwcm->ifname));
  2498. iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
  2499. iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
  2500. iwibdev->ibdev.poll_cq = i40iw_poll_cq;
  2501. iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
  2502. iwibdev->ibdev.post_send = i40iw_post_send;
  2503. iwibdev->ibdev.post_recv = i40iw_post_recv;
  2504. return iwibdev;
  2505. }
  2506. /**
  2507. * i40iw_port_ibevent - indicate port event
  2508. * @iwdev: iwarp device
  2509. */
  2510. void i40iw_port_ibevent(struct i40iw_device *iwdev)
  2511. {
  2512. struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
  2513. struct ib_event event;
  2514. event.device = &iwibdev->ibdev;
  2515. event.element.port_num = 1;
  2516. event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2517. ib_dispatch_event(&event);
  2518. }
  2519. /**
  2520. * i40iw_unregister_rdma_device - unregister of iwarp from IB
  2521. * @iwibdev: rdma device ptr
  2522. */
  2523. static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
  2524. {
  2525. int i;
  2526. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
  2527. device_remove_file(&iwibdev->ibdev.dev,
  2528. i40iw_dev_attributes[i]);
  2529. ib_unregister_device(&iwibdev->ibdev);
  2530. }
  2531. /**
  2532. * i40iw_destroy_rdma_device - destroy rdma device and free resources
  2533. * @iwibdev: IB device ptr
  2534. */
  2535. void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
  2536. {
  2537. if (!iwibdev)
  2538. return;
  2539. i40iw_unregister_rdma_device(iwibdev);
  2540. kfree(iwibdev->ibdev.iwcm);
  2541. iwibdev->ibdev.iwcm = NULL;
  2542. wait_event_timeout(iwibdev->iwdev->close_wq,
  2543. !atomic64_read(&iwibdev->iwdev->use_count),
  2544. I40IW_EVENT_TIMEOUT);
  2545. ib_dealloc_device(&iwibdev->ibdev);
  2546. }
  2547. /**
  2548. * i40iw_register_rdma_device - register iwarp device to IB
  2549. * @iwdev: iwarp device
  2550. */
  2551. int i40iw_register_rdma_device(struct i40iw_device *iwdev)
  2552. {
  2553. int i, ret;
  2554. struct i40iw_ib_device *iwibdev;
  2555. iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
  2556. if (!iwdev->iwibdev)
  2557. return -ENOMEM;
  2558. iwibdev = iwdev->iwibdev;
  2559. ret = ib_register_device(&iwibdev->ibdev, NULL);
  2560. if (ret)
  2561. goto error;
  2562. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
  2563. ret =
  2564. device_create_file(&iwibdev->ibdev.dev,
  2565. i40iw_dev_attributes[i]);
  2566. if (ret) {
  2567. while (i > 0) {
  2568. i--;
  2569. device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
  2570. }
  2571. ib_unregister_device(&iwibdev->ibdev);
  2572. goto error;
  2573. }
  2574. }
  2575. return 0;
  2576. error:
  2577. kfree(iwdev->iwibdev->ibdev.iwcm);
  2578. iwdev->iwibdev->ibdev.iwcm = NULL;
  2579. ib_dealloc_device(&iwdev->iwibdev->ibdev);
  2580. return ret;
  2581. }