kernel_xiaomi_lancelot/drivers/infiniband/hw/i40iw/i40iw_pble.h

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#ifndef I40IW_PBLE_H
#define I40IW_PBLE_H

#define POOL_SHIFT      6
#define PBLE_PER_PAGE   512
#define I40IW_HMC_PAGED_BP_SHIFT 12
#define PBLE_512_SHIFT  9

enum i40iw_pble_level {
	I40IW_LEVEL_0 = 0,
	I40IW_LEVEL_1 = 1,
	I40IW_LEVEL_2 = 2
};

enum i40iw_alloc_type {
	I40IW_NO_ALLOC = 0,
	I40IW_DMA_COHERENT = 1,
	I40IW_VMALLOC = 2
};

struct i40iw_pble_info {
	unsigned long addr;
	u32 idx;
	u32 cnt;
};

struct i40iw_pble_level2 {
	struct i40iw_pble_info root;
	struct i40iw_pble_info *leaf;
	u32 leaf_cnt;
};

struct i40iw_pble_alloc {
	u32 total_cnt;
	enum i40iw_pble_level level;
	union {
		struct i40iw_pble_info level1;
		struct i40iw_pble_level2 level2;
	};
};

struct sd_pd_idx {
	u32 sd_idx;
	u32 pd_idx;
	u32 rel_pd_idx;
};

struct i40iw_add_page_info {
	struct i40iw_chunk *chunk;
	struct i40iw_hmc_sd_entry *sd_entry;
	struct i40iw_hmc_info *hmc_info;
	struct sd_pd_idx idx;
	u32 pages;
};

struct i40iw_chunk {
	struct list_head list;
	u32 size;
	void *vaddr;
	u64 fpm_addr;
	u32 pg_cnt;
	dma_addr_t *dmaaddrs;
	enum i40iw_alloc_type type;
};

struct i40iw_pble_pool {
	struct gen_pool *pool;
	struct list_head clist;
	u32 total_pble_alloc;
	u32 free_pble_cnt;
	u32 pool_shift;
};

struct i40iw_hmc_pble_rsrc {
	u32 unallocated_pble;
	u64 fpm_base_addr;
	u64 next_fpm_addr;
	struct i40iw_pble_pool pinfo;

	u32 stats_direct_sds;
	u32 stats_paged_sds;
	u64 stats_alloc_ok;
	u64 stats_alloc_fail;
	u64 stats_alloc_freed;
	u64 stats_lvl1;
	u64 stats_lvl2;
};

void i40iw_destroy_pble_pool(struct i40iw_sc_dev *dev, struct i40iw_hmc_pble_rsrc *pble_rsrc);
enum i40iw_status_code i40iw_hmc_init_pble(struct i40iw_sc_dev *dev,
					   struct i40iw_hmc_pble_rsrc *pble_rsrc);
void i40iw_free_pble(struct i40iw_hmc_pble_rsrc *pble_rsrc, struct i40iw_pble_alloc *palloc);
enum i40iw_status_code i40iw_get_pble(struct i40iw_sc_dev *dev,
				      struct i40iw_hmc_pble_rsrc *pble_rsrc,
				      struct i40iw_pble_alloc *palloc,
				      u32 pble_cnt);
#endif