device.c 42 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. static int allow_db_fc_on_t5;
  44. module_param(allow_db_fc_on_t5, int, 0644);
  45. MODULE_PARM_DESC(allow_db_fc_on_t5,
  46. "Allow DB Flow Control on T5 (default = 0)");
  47. static int allow_db_coalescing_on_t5;
  48. module_param(allow_db_coalescing_on_t5, int, 0644);
  49. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  50. "Allow DB Coalescing on T5 (default = 0)");
  51. int c4iw_wr_log = 0;
  52. module_param(c4iw_wr_log, int, 0444);
  53. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  54. static int c4iw_wr_log_size_order = 12;
  55. module_param(c4iw_wr_log_size_order, int, 0444);
  56. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  57. "Number of entries (log2) in the work request timing log.");
  58. struct uld_ctx {
  59. struct list_head entry;
  60. struct cxgb4_lld_info lldi;
  61. struct c4iw_dev *dev;
  62. };
  63. static LIST_HEAD(uld_ctx_list);
  64. static DEFINE_MUTEX(dev_mutex);
  65. #define DB_FC_RESUME_SIZE 64
  66. #define DB_FC_RESUME_DELAY 1
  67. #define DB_FC_DRAIN_THRESH 0
  68. static struct dentry *c4iw_debugfs_root;
  69. struct c4iw_debugfs_data {
  70. struct c4iw_dev *devp;
  71. char *buf;
  72. int bufsize;
  73. int pos;
  74. };
  75. static int count_idrs(int id, void *p, void *data)
  76. {
  77. int *countp = data;
  78. *countp = *countp + 1;
  79. return 0;
  80. }
  81. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  82. loff_t *ppos)
  83. {
  84. struct c4iw_debugfs_data *d = file->private_data;
  85. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  86. }
  87. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  88. {
  89. struct wr_log_entry le;
  90. int idx;
  91. if (!wq->rdev->wr_log)
  92. return;
  93. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  94. (wq->rdev->wr_log_size - 1);
  95. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  96. getnstimeofday(&le.poll_host_ts);
  97. le.valid = 1;
  98. le.cqe_sge_ts = CQE_TS(cqe);
  99. if (SQ_TYPE(cqe)) {
  100. le.qid = wq->sq.qid;
  101. le.opcode = CQE_OPCODE(cqe);
  102. le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts;
  103. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  104. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  105. } else {
  106. le.qid = wq->rq.qid;
  107. le.opcode = FW_RI_RECEIVE;
  108. le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts;
  109. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  110. le.wr_id = CQE_WRID_MSN(cqe);
  111. }
  112. wq->rdev->wr_log[idx] = le;
  113. }
  114. static int wr_log_show(struct seq_file *seq, void *v)
  115. {
  116. struct c4iw_dev *dev = seq->private;
  117. struct timespec prev_ts = {0, 0};
  118. struct wr_log_entry *lep;
  119. int prev_ts_set = 0;
  120. int idx, end;
  121. #define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
  122. idx = atomic_read(&dev->rdev.wr_log_idx) &
  123. (dev->rdev.wr_log_size - 1);
  124. end = idx - 1;
  125. if (end < 0)
  126. end = dev->rdev.wr_log_size - 1;
  127. lep = &dev->rdev.wr_log[idx];
  128. while (idx != end) {
  129. if (lep->valid) {
  130. if (!prev_ts_set) {
  131. prev_ts_set = 1;
  132. prev_ts = lep->poll_host_ts;
  133. }
  134. seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode "
  135. "%u %s 0x%x host_wr_delta sec %lu nsec %lu "
  136. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  137. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  138. "cqe_poll_delta_ns %llu\n",
  139. idx,
  140. timespec_sub(lep->poll_host_ts,
  141. prev_ts).tv_sec,
  142. timespec_sub(lep->poll_host_ts,
  143. prev_ts).tv_nsec,
  144. lep->qid, lep->opcode,
  145. lep->opcode == FW_RI_RECEIVE ?
  146. "msn" : "wrid",
  147. lep->wr_id,
  148. timespec_sub(lep->poll_host_ts,
  149. lep->post_host_ts).tv_sec,
  150. timespec_sub(lep->poll_host_ts,
  151. lep->post_host_ts).tv_nsec,
  152. lep->post_sge_ts, lep->cqe_sge_ts,
  153. lep->poll_sge_ts,
  154. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  155. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  156. prev_ts = lep->poll_host_ts;
  157. }
  158. idx++;
  159. if (idx > (dev->rdev.wr_log_size - 1))
  160. idx = 0;
  161. lep = &dev->rdev.wr_log[idx];
  162. }
  163. #undef ts2ns
  164. return 0;
  165. }
  166. static int wr_log_open(struct inode *inode, struct file *file)
  167. {
  168. return single_open(file, wr_log_show, inode->i_private);
  169. }
  170. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  171. size_t count, loff_t *pos)
  172. {
  173. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  174. int i;
  175. if (dev->rdev.wr_log)
  176. for (i = 0; i < dev->rdev.wr_log_size; i++)
  177. dev->rdev.wr_log[i].valid = 0;
  178. return count;
  179. }
  180. static const struct file_operations wr_log_debugfs_fops = {
  181. .owner = THIS_MODULE,
  182. .open = wr_log_open,
  183. .release = single_release,
  184. .read = seq_read,
  185. .llseek = seq_lseek,
  186. .write = wr_log_clear,
  187. };
  188. static struct sockaddr_in zero_sin = {
  189. .sin_family = AF_INET,
  190. };
  191. static struct sockaddr_in6 zero_sin6 = {
  192. .sin6_family = AF_INET6,
  193. };
  194. static void set_ep_sin_addrs(struct c4iw_ep *ep,
  195. struct sockaddr_in **lsin,
  196. struct sockaddr_in **rsin,
  197. struct sockaddr_in **m_lsin,
  198. struct sockaddr_in **m_rsin)
  199. {
  200. struct iw_cm_id *id = ep->com.cm_id;
  201. *lsin = (struct sockaddr_in *)&ep->com.local_addr;
  202. *rsin = (struct sockaddr_in *)&ep->com.remote_addr;
  203. if (id) {
  204. *m_lsin = (struct sockaddr_in *)&id->m_local_addr;
  205. *m_rsin = (struct sockaddr_in *)&id->m_remote_addr;
  206. } else {
  207. *m_lsin = &zero_sin;
  208. *m_rsin = &zero_sin;
  209. }
  210. }
  211. static void set_ep_sin6_addrs(struct c4iw_ep *ep,
  212. struct sockaddr_in6 **lsin6,
  213. struct sockaddr_in6 **rsin6,
  214. struct sockaddr_in6 **m_lsin6,
  215. struct sockaddr_in6 **m_rsin6)
  216. {
  217. struct iw_cm_id *id = ep->com.cm_id;
  218. *lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
  219. *rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
  220. if (id) {
  221. *m_lsin6 = (struct sockaddr_in6 *)&id->m_local_addr;
  222. *m_rsin6 = (struct sockaddr_in6 *)&id->m_remote_addr;
  223. } else {
  224. *m_lsin6 = &zero_sin6;
  225. *m_rsin6 = &zero_sin6;
  226. }
  227. }
  228. static int dump_qp(int id, void *p, void *data)
  229. {
  230. struct c4iw_qp *qp = p;
  231. struct c4iw_debugfs_data *qpd = data;
  232. int space;
  233. int cc;
  234. if (id != qp->wq.sq.qid)
  235. return 0;
  236. space = qpd->bufsize - qpd->pos - 1;
  237. if (space == 0)
  238. return 1;
  239. if (qp->ep) {
  240. struct c4iw_ep *ep = qp->ep;
  241. if (ep->com.local_addr.ss_family == AF_INET) {
  242. struct sockaddr_in *lsin;
  243. struct sockaddr_in *rsin;
  244. struct sockaddr_in *m_lsin;
  245. struct sockaddr_in *m_rsin;
  246. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  247. cc = snprintf(qpd->buf + qpd->pos, space,
  248. "rc qp sq id %u rq id %u state %u "
  249. "onchip %u ep tid %u state %u "
  250. "%pI4:%u/%u->%pI4:%u/%u\n",
  251. qp->wq.sq.qid, qp->wq.rq.qid,
  252. (int)qp->attr.state,
  253. qp->wq.sq.flags & T4_SQ_ONCHIP,
  254. ep->hwtid, (int)ep->com.state,
  255. &lsin->sin_addr, ntohs(lsin->sin_port),
  256. ntohs(m_lsin->sin_port),
  257. &rsin->sin_addr, ntohs(rsin->sin_port),
  258. ntohs(m_rsin->sin_port));
  259. } else {
  260. struct sockaddr_in6 *lsin6;
  261. struct sockaddr_in6 *rsin6;
  262. struct sockaddr_in6 *m_lsin6;
  263. struct sockaddr_in6 *m_rsin6;
  264. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
  265. &m_rsin6);
  266. cc = snprintf(qpd->buf + qpd->pos, space,
  267. "rc qp sq id %u rq id %u state %u "
  268. "onchip %u ep tid %u state %u "
  269. "%pI6:%u/%u->%pI6:%u/%u\n",
  270. qp->wq.sq.qid, qp->wq.rq.qid,
  271. (int)qp->attr.state,
  272. qp->wq.sq.flags & T4_SQ_ONCHIP,
  273. ep->hwtid, (int)ep->com.state,
  274. &lsin6->sin6_addr,
  275. ntohs(lsin6->sin6_port),
  276. ntohs(m_lsin6->sin6_port),
  277. &rsin6->sin6_addr,
  278. ntohs(rsin6->sin6_port),
  279. ntohs(m_rsin6->sin6_port));
  280. }
  281. } else
  282. cc = snprintf(qpd->buf + qpd->pos, space,
  283. "qp sq id %u rq id %u state %u onchip %u\n",
  284. qp->wq.sq.qid, qp->wq.rq.qid,
  285. (int)qp->attr.state,
  286. qp->wq.sq.flags & T4_SQ_ONCHIP);
  287. if (cc < space)
  288. qpd->pos += cc;
  289. return 0;
  290. }
  291. static int qp_release(struct inode *inode, struct file *file)
  292. {
  293. struct c4iw_debugfs_data *qpd = file->private_data;
  294. if (!qpd) {
  295. pr_info("%s null qpd?\n", __func__);
  296. return 0;
  297. }
  298. vfree(qpd->buf);
  299. kfree(qpd);
  300. return 0;
  301. }
  302. static int qp_open(struct inode *inode, struct file *file)
  303. {
  304. struct c4iw_debugfs_data *qpd;
  305. int count = 1;
  306. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  307. if (!qpd)
  308. return -ENOMEM;
  309. qpd->devp = inode->i_private;
  310. qpd->pos = 0;
  311. spin_lock_irq(&qpd->devp->lock);
  312. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  313. spin_unlock_irq(&qpd->devp->lock);
  314. qpd->bufsize = count * 180;
  315. qpd->buf = vmalloc(qpd->bufsize);
  316. if (!qpd->buf) {
  317. kfree(qpd);
  318. return -ENOMEM;
  319. }
  320. spin_lock_irq(&qpd->devp->lock);
  321. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  322. spin_unlock_irq(&qpd->devp->lock);
  323. qpd->buf[qpd->pos++] = 0;
  324. file->private_data = qpd;
  325. return 0;
  326. }
  327. static const struct file_operations qp_debugfs_fops = {
  328. .owner = THIS_MODULE,
  329. .open = qp_open,
  330. .release = qp_release,
  331. .read = debugfs_read,
  332. .llseek = default_llseek,
  333. };
  334. static int dump_stag(int id, void *p, void *data)
  335. {
  336. struct c4iw_debugfs_data *stagd = data;
  337. int space;
  338. int cc;
  339. struct fw_ri_tpte tpte;
  340. int ret;
  341. space = stagd->bufsize - stagd->pos - 1;
  342. if (space == 0)
  343. return 1;
  344. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  345. (__be32 *)&tpte);
  346. if (ret) {
  347. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  348. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  349. return ret;
  350. }
  351. cc = snprintf(stagd->buf + stagd->pos, space,
  352. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  353. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  354. (u32)id<<8,
  355. FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
  356. FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
  357. FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
  358. FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
  359. FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
  360. FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
  361. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  362. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  363. if (cc < space)
  364. stagd->pos += cc;
  365. return 0;
  366. }
  367. static int stag_release(struct inode *inode, struct file *file)
  368. {
  369. struct c4iw_debugfs_data *stagd = file->private_data;
  370. if (!stagd) {
  371. pr_info("%s null stagd?\n", __func__);
  372. return 0;
  373. }
  374. vfree(stagd->buf);
  375. kfree(stagd);
  376. return 0;
  377. }
  378. static int stag_open(struct inode *inode, struct file *file)
  379. {
  380. struct c4iw_debugfs_data *stagd;
  381. int ret = 0;
  382. int count = 1;
  383. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  384. if (!stagd) {
  385. ret = -ENOMEM;
  386. goto out;
  387. }
  388. stagd->devp = inode->i_private;
  389. stagd->pos = 0;
  390. spin_lock_irq(&stagd->devp->lock);
  391. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  392. spin_unlock_irq(&stagd->devp->lock);
  393. stagd->bufsize = count * 256;
  394. stagd->buf = vmalloc(stagd->bufsize);
  395. if (!stagd->buf) {
  396. ret = -ENOMEM;
  397. goto err1;
  398. }
  399. spin_lock_irq(&stagd->devp->lock);
  400. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  401. spin_unlock_irq(&stagd->devp->lock);
  402. stagd->buf[stagd->pos++] = 0;
  403. file->private_data = stagd;
  404. goto out;
  405. err1:
  406. kfree(stagd);
  407. out:
  408. return ret;
  409. }
  410. static const struct file_operations stag_debugfs_fops = {
  411. .owner = THIS_MODULE,
  412. .open = stag_open,
  413. .release = stag_release,
  414. .read = debugfs_read,
  415. .llseek = default_llseek,
  416. };
  417. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  418. static int stats_show(struct seq_file *seq, void *v)
  419. {
  420. struct c4iw_dev *dev = seq->private;
  421. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  422. "Max", "Fail");
  423. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  424. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  425. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  426. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  427. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  428. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  429. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  430. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  431. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  432. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  433. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  434. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  435. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  436. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  437. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  438. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  439. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  440. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  441. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  442. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  443. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  444. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  445. db_state_str[dev->db_state],
  446. dev->rdev.stats.db_state_transitions,
  447. dev->rdev.stats.db_fc_interruptions);
  448. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  449. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  450. dev->rdev.stats.act_ofld_conn_fails);
  451. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  452. dev->rdev.stats.pas_ofld_conn_fails);
  453. seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
  454. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  455. return 0;
  456. }
  457. static int stats_open(struct inode *inode, struct file *file)
  458. {
  459. return single_open(file, stats_show, inode->i_private);
  460. }
  461. static ssize_t stats_clear(struct file *file, const char __user *buf,
  462. size_t count, loff_t *pos)
  463. {
  464. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  465. mutex_lock(&dev->rdev.stats.lock);
  466. dev->rdev.stats.pd.max = 0;
  467. dev->rdev.stats.pd.fail = 0;
  468. dev->rdev.stats.qid.max = 0;
  469. dev->rdev.stats.qid.fail = 0;
  470. dev->rdev.stats.stag.max = 0;
  471. dev->rdev.stats.stag.fail = 0;
  472. dev->rdev.stats.pbl.max = 0;
  473. dev->rdev.stats.pbl.fail = 0;
  474. dev->rdev.stats.rqt.max = 0;
  475. dev->rdev.stats.rqt.fail = 0;
  476. dev->rdev.stats.ocqp.max = 0;
  477. dev->rdev.stats.ocqp.fail = 0;
  478. dev->rdev.stats.db_full = 0;
  479. dev->rdev.stats.db_empty = 0;
  480. dev->rdev.stats.db_drop = 0;
  481. dev->rdev.stats.db_state_transitions = 0;
  482. dev->rdev.stats.tcam_full = 0;
  483. dev->rdev.stats.act_ofld_conn_fails = 0;
  484. dev->rdev.stats.pas_ofld_conn_fails = 0;
  485. mutex_unlock(&dev->rdev.stats.lock);
  486. return count;
  487. }
  488. static const struct file_operations stats_debugfs_fops = {
  489. .owner = THIS_MODULE,
  490. .open = stats_open,
  491. .release = single_release,
  492. .read = seq_read,
  493. .llseek = seq_lseek,
  494. .write = stats_clear,
  495. };
  496. static int dump_ep(int id, void *p, void *data)
  497. {
  498. struct c4iw_ep *ep = p;
  499. struct c4iw_debugfs_data *epd = data;
  500. int space;
  501. int cc;
  502. space = epd->bufsize - epd->pos - 1;
  503. if (space == 0)
  504. return 1;
  505. if (ep->com.local_addr.ss_family == AF_INET) {
  506. struct sockaddr_in *lsin;
  507. struct sockaddr_in *rsin;
  508. struct sockaddr_in *m_lsin;
  509. struct sockaddr_in *m_rsin;
  510. set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
  511. cc = snprintf(epd->buf + epd->pos, space,
  512. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  513. "history 0x%lx hwtid %d atid %d "
  514. "conn_na %u abort_na %u "
  515. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  516. ep, ep->com.cm_id, ep->com.qp,
  517. (int)ep->com.state, ep->com.flags,
  518. ep->com.history, ep->hwtid, ep->atid,
  519. ep->stats.connect_neg_adv,
  520. ep->stats.abort_neg_adv,
  521. &lsin->sin_addr, ntohs(lsin->sin_port),
  522. ntohs(m_lsin->sin_port),
  523. &rsin->sin_addr, ntohs(rsin->sin_port),
  524. ntohs(m_rsin->sin_port));
  525. } else {
  526. struct sockaddr_in6 *lsin6;
  527. struct sockaddr_in6 *rsin6;
  528. struct sockaddr_in6 *m_lsin6;
  529. struct sockaddr_in6 *m_rsin6;
  530. set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
  531. cc = snprintf(epd->buf + epd->pos, space,
  532. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  533. "history 0x%lx hwtid %d atid %d "
  534. "conn_na %u abort_na %u "
  535. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  536. ep, ep->com.cm_id, ep->com.qp,
  537. (int)ep->com.state, ep->com.flags,
  538. ep->com.history, ep->hwtid, ep->atid,
  539. ep->stats.connect_neg_adv,
  540. ep->stats.abort_neg_adv,
  541. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  542. ntohs(m_lsin6->sin6_port),
  543. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  544. ntohs(m_rsin6->sin6_port));
  545. }
  546. if (cc < space)
  547. epd->pos += cc;
  548. return 0;
  549. }
  550. static int dump_listen_ep(int id, void *p, void *data)
  551. {
  552. struct c4iw_listen_ep *ep = p;
  553. struct c4iw_debugfs_data *epd = data;
  554. int space;
  555. int cc;
  556. space = epd->bufsize - epd->pos - 1;
  557. if (space == 0)
  558. return 1;
  559. if (ep->com.local_addr.ss_family == AF_INET) {
  560. struct sockaddr_in *lsin = (struct sockaddr_in *)
  561. &ep->com.cm_id->local_addr;
  562. struct sockaddr_in *m_lsin = (struct sockaddr_in *)
  563. &ep->com.cm_id->m_local_addr;
  564. cc = snprintf(epd->buf + epd->pos, space,
  565. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  566. "backlog %d %pI4:%d/%d\n",
  567. ep, ep->com.cm_id, (int)ep->com.state,
  568. ep->com.flags, ep->stid, ep->backlog,
  569. &lsin->sin_addr, ntohs(lsin->sin_port),
  570. ntohs(m_lsin->sin_port));
  571. } else {
  572. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  573. &ep->com.cm_id->local_addr;
  574. struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
  575. &ep->com.cm_id->m_local_addr;
  576. cc = snprintf(epd->buf + epd->pos, space,
  577. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  578. "backlog %d %pI6:%d/%d\n",
  579. ep, ep->com.cm_id, (int)ep->com.state,
  580. ep->com.flags, ep->stid, ep->backlog,
  581. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  582. ntohs(m_lsin6->sin6_port));
  583. }
  584. if (cc < space)
  585. epd->pos += cc;
  586. return 0;
  587. }
  588. static int ep_release(struct inode *inode, struct file *file)
  589. {
  590. struct c4iw_debugfs_data *epd = file->private_data;
  591. if (!epd) {
  592. pr_info("%s null qpd?\n", __func__);
  593. return 0;
  594. }
  595. vfree(epd->buf);
  596. kfree(epd);
  597. return 0;
  598. }
  599. static int ep_open(struct inode *inode, struct file *file)
  600. {
  601. struct c4iw_debugfs_data *epd;
  602. int ret = 0;
  603. int count = 1;
  604. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  605. if (!epd) {
  606. ret = -ENOMEM;
  607. goto out;
  608. }
  609. epd->devp = inode->i_private;
  610. epd->pos = 0;
  611. spin_lock_irq(&epd->devp->lock);
  612. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  613. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  614. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  615. spin_unlock_irq(&epd->devp->lock);
  616. epd->bufsize = count * 240;
  617. epd->buf = vmalloc(epd->bufsize);
  618. if (!epd->buf) {
  619. ret = -ENOMEM;
  620. goto err1;
  621. }
  622. spin_lock_irq(&epd->devp->lock);
  623. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  624. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  625. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  626. spin_unlock_irq(&epd->devp->lock);
  627. file->private_data = epd;
  628. goto out;
  629. err1:
  630. kfree(epd);
  631. out:
  632. return ret;
  633. }
  634. static const struct file_operations ep_debugfs_fops = {
  635. .owner = THIS_MODULE,
  636. .open = ep_open,
  637. .release = ep_release,
  638. .read = debugfs_read,
  639. };
  640. static int setup_debugfs(struct c4iw_dev *devp)
  641. {
  642. if (!devp->debugfs_root)
  643. return -1;
  644. debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
  645. (void *)devp, &qp_debugfs_fops, 4096);
  646. debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
  647. (void *)devp, &stag_debugfs_fops, 4096);
  648. debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
  649. (void *)devp, &stats_debugfs_fops, 4096);
  650. debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
  651. (void *)devp, &ep_debugfs_fops, 4096);
  652. if (c4iw_wr_log)
  653. debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
  654. (void *)devp, &wr_log_debugfs_fops, 4096);
  655. return 0;
  656. }
  657. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  658. struct c4iw_dev_ucontext *uctx)
  659. {
  660. struct list_head *pos, *nxt;
  661. struct c4iw_qid_list *entry;
  662. mutex_lock(&uctx->lock);
  663. list_for_each_safe(pos, nxt, &uctx->qpids) {
  664. entry = list_entry(pos, struct c4iw_qid_list, entry);
  665. list_del_init(&entry->entry);
  666. if (!(entry->qid & rdev->qpmask)) {
  667. c4iw_put_resource(&rdev->resource.qid_table,
  668. entry->qid);
  669. mutex_lock(&rdev->stats.lock);
  670. rdev->stats.qid.cur -= rdev->qpmask + 1;
  671. mutex_unlock(&rdev->stats.lock);
  672. }
  673. kfree(entry);
  674. }
  675. list_for_each_safe(pos, nxt, &uctx->cqids) {
  676. entry = list_entry(pos, struct c4iw_qid_list, entry);
  677. list_del_init(&entry->entry);
  678. kfree(entry);
  679. }
  680. mutex_unlock(&uctx->lock);
  681. }
  682. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  683. struct c4iw_dev_ucontext *uctx)
  684. {
  685. INIT_LIST_HEAD(&uctx->qpids);
  686. INIT_LIST_HEAD(&uctx->cqids);
  687. mutex_init(&uctx->lock);
  688. }
  689. /* Caller takes care of locking if needed */
  690. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  691. {
  692. int err;
  693. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  694. /*
  695. * This implementation assumes udb_density == ucq_density! Eventually
  696. * we might need to support this but for now fail the open. Also the
  697. * cqid and qpid range must match for now.
  698. */
  699. if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
  700. pr_err("%s: unsupported udb/ucq densities %u/%u\n",
  701. pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
  702. rdev->lldi.ucq_density);
  703. return -EINVAL;
  704. }
  705. if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
  706. rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
  707. pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
  708. pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
  709. rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
  710. rdev->lldi.vr->cq.size);
  711. return -EINVAL;
  712. }
  713. rdev->qpmask = rdev->lldi.udb_density - 1;
  714. rdev->cqmask = rdev->lldi.ucq_density - 1;
  715. pr_debug("%s dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n",
  716. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  717. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  718. rdev->lldi.vr->pbl.start,
  719. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  720. rdev->lldi.vr->rq.size,
  721. rdev->lldi.vr->qp.start,
  722. rdev->lldi.vr->qp.size,
  723. rdev->lldi.vr->cq.start,
  724. rdev->lldi.vr->cq.size);
  725. pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
  726. &rdev->lldi.pdev->resource[2],
  727. rdev->lldi.db_reg, rdev->lldi.gts_reg,
  728. rdev->qpmask, rdev->cqmask);
  729. if (c4iw_num_stags(rdev) == 0)
  730. return -EINVAL;
  731. rdev->stats.pd.total = T4_MAX_NUM_PD;
  732. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  733. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  734. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  735. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  736. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  737. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  738. if (err) {
  739. pr_err("error %d initializing resources\n", err);
  740. return err;
  741. }
  742. err = c4iw_pblpool_create(rdev);
  743. if (err) {
  744. pr_err("error %d initializing pbl pool\n", err);
  745. goto destroy_resource;
  746. }
  747. err = c4iw_rqtpool_create(rdev);
  748. if (err) {
  749. pr_err("error %d initializing rqt pool\n", err);
  750. goto destroy_pblpool;
  751. }
  752. err = c4iw_ocqp_pool_create(rdev);
  753. if (err) {
  754. pr_err("error %d initializing ocqp pool\n", err);
  755. goto destroy_rqtpool;
  756. }
  757. rdev->status_page = (struct t4_dev_status_page *)
  758. __get_free_page(GFP_KERNEL);
  759. if (!rdev->status_page) {
  760. err = -ENOMEM;
  761. goto destroy_ocqp_pool;
  762. }
  763. rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
  764. rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
  765. rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
  766. rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
  767. if (c4iw_wr_log) {
  768. rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
  769. sizeof(*rdev->wr_log), GFP_KERNEL);
  770. if (rdev->wr_log) {
  771. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  772. atomic_set(&rdev->wr_log_idx, 0);
  773. }
  774. }
  775. rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
  776. if (!rdev->free_workq) {
  777. err = -ENOMEM;
  778. goto err_free_status_page_and_wr_log;
  779. }
  780. rdev->status_page->db_off = 0;
  781. init_completion(&rdev->rqt_compl);
  782. init_completion(&rdev->pbl_compl);
  783. kref_init(&rdev->rqt_kref);
  784. kref_init(&rdev->pbl_kref);
  785. return 0;
  786. err_free_status_page_and_wr_log:
  787. if (c4iw_wr_log && rdev->wr_log)
  788. kfree(rdev->wr_log);
  789. free_page((unsigned long)rdev->status_page);
  790. destroy_ocqp_pool:
  791. c4iw_ocqp_pool_destroy(rdev);
  792. destroy_rqtpool:
  793. c4iw_rqtpool_destroy(rdev);
  794. destroy_pblpool:
  795. c4iw_pblpool_destroy(rdev);
  796. destroy_resource:
  797. c4iw_destroy_resource(&rdev->resource);
  798. return err;
  799. }
  800. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  801. {
  802. kfree(rdev->wr_log);
  803. c4iw_release_dev_ucontext(rdev, &rdev->uctx);
  804. free_page((unsigned long)rdev->status_page);
  805. c4iw_pblpool_destroy(rdev);
  806. c4iw_rqtpool_destroy(rdev);
  807. wait_for_completion(&rdev->pbl_compl);
  808. wait_for_completion(&rdev->rqt_compl);
  809. c4iw_ocqp_pool_destroy(rdev);
  810. destroy_workqueue(rdev->free_workq);
  811. c4iw_destroy_resource(&rdev->resource);
  812. }
  813. static void c4iw_dealloc(struct uld_ctx *ctx)
  814. {
  815. c4iw_rdev_close(&ctx->dev->rdev);
  816. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
  817. idr_destroy(&ctx->dev->cqidr);
  818. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
  819. idr_destroy(&ctx->dev->qpidr);
  820. WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
  821. idr_destroy(&ctx->dev->mmidr);
  822. wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
  823. idr_destroy(&ctx->dev->hwtid_idr);
  824. idr_destroy(&ctx->dev->stid_idr);
  825. idr_destroy(&ctx->dev->atid_idr);
  826. if (ctx->dev->rdev.bar2_kva)
  827. iounmap(ctx->dev->rdev.bar2_kva);
  828. if (ctx->dev->rdev.oc_mw_kva)
  829. iounmap(ctx->dev->rdev.oc_mw_kva);
  830. ib_dealloc_device(&ctx->dev->ibdev);
  831. ctx->dev = NULL;
  832. }
  833. static void c4iw_remove(struct uld_ctx *ctx)
  834. {
  835. pr_debug("%s c4iw_dev %p\n", __func__, ctx->dev);
  836. c4iw_unregister_device(ctx->dev);
  837. c4iw_dealloc(ctx);
  838. }
  839. static int rdma_supported(const struct cxgb4_lld_info *infop)
  840. {
  841. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  842. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  843. infop->vr->cq.size > 0;
  844. }
  845. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  846. {
  847. struct c4iw_dev *devp;
  848. int ret;
  849. if (!rdma_supported(infop)) {
  850. pr_info("%s: RDMA not supported on this device\n",
  851. pci_name(infop->pdev));
  852. return ERR_PTR(-ENOSYS);
  853. }
  854. if (!ocqp_supported(infop))
  855. pr_info("%s: On-Chip Queues not supported on this device\n",
  856. pci_name(infop->pdev));
  857. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  858. if (!devp) {
  859. pr_err("Cannot allocate ib device\n");
  860. return ERR_PTR(-ENOMEM);
  861. }
  862. devp->rdev.lldi = *infop;
  863. /* init various hw-queue params based on lld info */
  864. pr_debug("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  865. __func__, devp->rdev.lldi.sge_ingpadboundary,
  866. devp->rdev.lldi.sge_egrstatuspagesize);
  867. devp->rdev.hw_queue.t4_eq_status_entries =
  868. devp->rdev.lldi.sge_egrstatuspagesize / 64;
  869. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  870. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  871. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  872. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  873. devp->rdev.hw_queue.t4_max_sq_size =
  874. devp->rdev.hw_queue.t4_max_eq_size -
  875. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  876. devp->rdev.hw_queue.t4_max_qp_depth =
  877. devp->rdev.hw_queue.t4_max_rq_size;
  878. devp->rdev.hw_queue.t4_max_cq_depth =
  879. devp->rdev.hw_queue.t4_max_iq_size - 2;
  880. devp->rdev.hw_queue.t4_stat_len =
  881. devp->rdev.lldi.sge_egrstatuspagesize;
  882. /*
  883. * For T5/T6 devices, we map all of BAR2 with WC.
  884. * For T4 devices with onchip qp mem, we map only that part
  885. * of BAR2 with WC.
  886. */
  887. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  888. if (!is_t4(devp->rdev.lldi.adapter_type)) {
  889. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  890. pci_resource_len(devp->rdev.lldi.pdev, 2));
  891. if (!devp->rdev.bar2_kva) {
  892. pr_err("Unable to ioremap BAR2\n");
  893. ib_dealloc_device(&devp->ibdev);
  894. return ERR_PTR(-EINVAL);
  895. }
  896. } else if (ocqp_supported(infop)) {
  897. devp->rdev.oc_mw_pa =
  898. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  899. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  900. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  901. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  902. devp->rdev.lldi.vr->ocq.size);
  903. if (!devp->rdev.oc_mw_kva) {
  904. pr_err("Unable to ioremap onchip mem\n");
  905. ib_dealloc_device(&devp->ibdev);
  906. return ERR_PTR(-EINVAL);
  907. }
  908. }
  909. pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  910. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  911. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  912. ret = c4iw_rdev_open(&devp->rdev);
  913. if (ret) {
  914. pr_err("Unable to open CXIO rdev err %d\n", ret);
  915. ib_dealloc_device(&devp->ibdev);
  916. return ERR_PTR(ret);
  917. }
  918. idr_init(&devp->cqidr);
  919. idr_init(&devp->qpidr);
  920. idr_init(&devp->mmidr);
  921. idr_init(&devp->hwtid_idr);
  922. idr_init(&devp->stid_idr);
  923. idr_init(&devp->atid_idr);
  924. spin_lock_init(&devp->lock);
  925. mutex_init(&devp->rdev.stats.lock);
  926. mutex_init(&devp->db_mutex);
  927. INIT_LIST_HEAD(&devp->db_fc_list);
  928. init_waitqueue_head(&devp->wait);
  929. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  930. if (c4iw_debugfs_root) {
  931. devp->debugfs_root = debugfs_create_dir(
  932. pci_name(devp->rdev.lldi.pdev),
  933. c4iw_debugfs_root);
  934. setup_debugfs(devp);
  935. }
  936. return devp;
  937. }
  938. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  939. {
  940. struct uld_ctx *ctx;
  941. static int vers_printed;
  942. int i;
  943. if (!vers_printed++)
  944. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  945. DRV_VERSION);
  946. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  947. if (!ctx) {
  948. ctx = ERR_PTR(-ENOMEM);
  949. goto out;
  950. }
  951. ctx->lldi = *infop;
  952. pr_debug("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  953. __func__, pci_name(ctx->lldi.pdev),
  954. ctx->lldi.nchan, ctx->lldi.nrxq,
  955. ctx->lldi.ntxq, ctx->lldi.nports);
  956. mutex_lock(&dev_mutex);
  957. list_add_tail(&ctx->entry, &uld_ctx_list);
  958. mutex_unlock(&dev_mutex);
  959. for (i = 0; i < ctx->lldi.nrxq; i++)
  960. pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  961. out:
  962. return ctx;
  963. }
  964. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  965. const __be64 *rsp,
  966. u32 pktshift)
  967. {
  968. struct sk_buff *skb;
  969. /*
  970. * Allocate space for cpl_pass_accept_req which will be synthesized by
  971. * driver. Once the driver synthesizes the request the skb will go
  972. * through the regular cpl_pass_accept_req processing.
  973. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  974. * cpl_rx_pkt.
  975. */
  976. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  977. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  978. if (unlikely(!skb))
  979. return NULL;
  980. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  981. sizeof(struct rss_header) - pktshift);
  982. /*
  983. * This skb will contain:
  984. * rss_header from the rspq descriptor (1 flit)
  985. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  986. * space for the difference between the size of an
  987. * rx_pkt and pass_accept_req cpl (1 flit)
  988. * the packet data from the gl
  989. */
  990. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  991. sizeof(struct rss_header));
  992. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  993. sizeof(struct cpl_pass_accept_req),
  994. gl->va + pktshift,
  995. gl->tot_len - pktshift);
  996. return skb;
  997. }
  998. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  999. const __be64 *rsp)
  1000. {
  1001. unsigned int opcode = *(u8 *)rsp;
  1002. struct sk_buff *skb;
  1003. if (opcode != CPL_RX_PKT)
  1004. goto out;
  1005. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  1006. if (skb == NULL)
  1007. goto out;
  1008. if (c4iw_handlers[opcode] == NULL) {
  1009. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1010. kfree_skb(skb);
  1011. goto out;
  1012. }
  1013. c4iw_handlers[opcode](dev, skb);
  1014. return 1;
  1015. out:
  1016. return 0;
  1017. }
  1018. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  1019. const struct pkt_gl *gl)
  1020. {
  1021. struct uld_ctx *ctx = handle;
  1022. struct c4iw_dev *dev = ctx->dev;
  1023. struct sk_buff *skb;
  1024. u8 opcode;
  1025. if (gl == NULL) {
  1026. /* omit RSS and rsp_ctrl at end of descriptor */
  1027. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  1028. skb = alloc_skb(256, GFP_ATOMIC);
  1029. if (!skb)
  1030. goto nomem;
  1031. __skb_put(skb, len);
  1032. skb_copy_to_linear_data(skb, &rsp[1], len);
  1033. } else if (gl == CXGB4_MSG_AN) {
  1034. const struct rsp_ctrl *rc = (void *)rsp;
  1035. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1036. c4iw_ev_handler(dev, qid);
  1037. return 0;
  1038. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1039. if (recv_rx_pkt(dev, gl, rsp))
  1040. return 0;
  1041. pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
  1042. pci_name(ctx->lldi.pdev), gl->va,
  1043. be64_to_cpu(*rsp),
  1044. be64_to_cpu(*(__force __be64 *)gl->va),
  1045. gl->tot_len);
  1046. return 0;
  1047. } else {
  1048. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1049. if (unlikely(!skb))
  1050. goto nomem;
  1051. }
  1052. opcode = *(u8 *)rsp;
  1053. if (c4iw_handlers[opcode]) {
  1054. c4iw_handlers[opcode](dev, skb);
  1055. } else {
  1056. pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
  1057. kfree_skb(skb);
  1058. }
  1059. return 0;
  1060. nomem:
  1061. return -1;
  1062. }
  1063. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1064. {
  1065. struct uld_ctx *ctx = handle;
  1066. pr_debug("%s new_state %u\n", __func__, new_state);
  1067. switch (new_state) {
  1068. case CXGB4_STATE_UP:
  1069. pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
  1070. if (!ctx->dev) {
  1071. int ret;
  1072. ctx->dev = c4iw_alloc(&ctx->lldi);
  1073. if (IS_ERR(ctx->dev)) {
  1074. pr_err("%s: initialization failed: %ld\n",
  1075. pci_name(ctx->lldi.pdev),
  1076. PTR_ERR(ctx->dev));
  1077. ctx->dev = NULL;
  1078. break;
  1079. }
  1080. ret = c4iw_register_device(ctx->dev);
  1081. if (ret) {
  1082. pr_err("%s: RDMA registration failed: %d\n",
  1083. pci_name(ctx->lldi.pdev), ret);
  1084. c4iw_dealloc(ctx);
  1085. }
  1086. }
  1087. break;
  1088. case CXGB4_STATE_DOWN:
  1089. pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
  1090. if (ctx->dev)
  1091. c4iw_remove(ctx);
  1092. break;
  1093. case CXGB4_STATE_START_RECOVERY:
  1094. pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
  1095. if (ctx->dev) {
  1096. struct ib_event event;
  1097. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1098. memset(&event, 0, sizeof event);
  1099. event.event = IB_EVENT_DEVICE_FATAL;
  1100. event.device = &ctx->dev->ibdev;
  1101. ib_dispatch_event(&event);
  1102. c4iw_remove(ctx);
  1103. }
  1104. break;
  1105. case CXGB4_STATE_DETACH:
  1106. pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
  1107. if (ctx->dev)
  1108. c4iw_remove(ctx);
  1109. break;
  1110. }
  1111. return 0;
  1112. }
  1113. static int disable_qp_db(int id, void *p, void *data)
  1114. {
  1115. struct c4iw_qp *qp = p;
  1116. t4_disable_wq_db(&qp->wq);
  1117. return 0;
  1118. }
  1119. static void stop_queues(struct uld_ctx *ctx)
  1120. {
  1121. unsigned long flags;
  1122. spin_lock_irqsave(&ctx->dev->lock, flags);
  1123. ctx->dev->rdev.stats.db_state_transitions++;
  1124. ctx->dev->db_state = STOPPED;
  1125. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1126. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1127. else
  1128. ctx->dev->rdev.status_page->db_off = 1;
  1129. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1130. }
  1131. static int enable_qp_db(int id, void *p, void *data)
  1132. {
  1133. struct c4iw_qp *qp = p;
  1134. t4_enable_wq_db(&qp->wq);
  1135. return 0;
  1136. }
  1137. static void resume_rc_qp(struct c4iw_qp *qp)
  1138. {
  1139. spin_lock(&qp->lock);
  1140. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
  1141. qp->wq.sq.wq_pidx_inc = 0;
  1142. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
  1143. qp->wq.rq.wq_pidx_inc = 0;
  1144. spin_unlock(&qp->lock);
  1145. }
  1146. static void resume_a_chunk(struct uld_ctx *ctx)
  1147. {
  1148. int i;
  1149. struct c4iw_qp *qp;
  1150. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1151. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1152. db_fc_entry);
  1153. list_del_init(&qp->db_fc_entry);
  1154. resume_rc_qp(qp);
  1155. if (list_empty(&ctx->dev->db_fc_list))
  1156. break;
  1157. }
  1158. }
  1159. static void resume_queues(struct uld_ctx *ctx)
  1160. {
  1161. spin_lock_irq(&ctx->dev->lock);
  1162. if (ctx->dev->db_state != STOPPED)
  1163. goto out;
  1164. ctx->dev->db_state = FLOW_CONTROL;
  1165. while (1) {
  1166. if (list_empty(&ctx->dev->db_fc_list)) {
  1167. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1168. ctx->dev->db_state = NORMAL;
  1169. ctx->dev->rdev.stats.db_state_transitions++;
  1170. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1171. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1172. NULL);
  1173. } else {
  1174. ctx->dev->rdev.status_page->db_off = 0;
  1175. }
  1176. break;
  1177. } else {
  1178. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1179. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1180. DB_FC_DRAIN_THRESH)) {
  1181. resume_a_chunk(ctx);
  1182. }
  1183. if (!list_empty(&ctx->dev->db_fc_list)) {
  1184. spin_unlock_irq(&ctx->dev->lock);
  1185. if (DB_FC_RESUME_DELAY) {
  1186. set_current_state(TASK_UNINTERRUPTIBLE);
  1187. schedule_timeout(DB_FC_RESUME_DELAY);
  1188. }
  1189. spin_lock_irq(&ctx->dev->lock);
  1190. if (ctx->dev->db_state != FLOW_CONTROL)
  1191. break;
  1192. }
  1193. }
  1194. }
  1195. out:
  1196. if (ctx->dev->db_state != NORMAL)
  1197. ctx->dev->rdev.stats.db_fc_interruptions++;
  1198. spin_unlock_irq(&ctx->dev->lock);
  1199. }
  1200. struct qp_list {
  1201. unsigned idx;
  1202. struct c4iw_qp **qps;
  1203. };
  1204. static int add_and_ref_qp(int id, void *p, void *data)
  1205. {
  1206. struct qp_list *qp_listp = data;
  1207. struct c4iw_qp *qp = p;
  1208. c4iw_qp_add_ref(&qp->ibqp);
  1209. qp_listp->qps[qp_listp->idx++] = qp;
  1210. return 0;
  1211. }
  1212. static int count_qps(int id, void *p, void *data)
  1213. {
  1214. unsigned *countp = data;
  1215. (*countp)++;
  1216. return 0;
  1217. }
  1218. static void deref_qps(struct qp_list *qp_list)
  1219. {
  1220. int idx;
  1221. for (idx = 0; idx < qp_list->idx; idx++)
  1222. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1223. }
  1224. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1225. {
  1226. int idx;
  1227. int ret;
  1228. for (idx = 0; idx < qp_list->idx; idx++) {
  1229. struct c4iw_qp *qp = qp_list->qps[idx];
  1230. spin_lock_irq(&qp->rhp->lock);
  1231. spin_lock(&qp->lock);
  1232. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1233. qp->wq.sq.qid,
  1234. t4_sq_host_wq_pidx(&qp->wq),
  1235. t4_sq_wq_size(&qp->wq));
  1236. if (ret) {
  1237. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
  1238. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1239. spin_unlock(&qp->lock);
  1240. spin_unlock_irq(&qp->rhp->lock);
  1241. return;
  1242. }
  1243. qp->wq.sq.wq_pidx_inc = 0;
  1244. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1245. qp->wq.rq.qid,
  1246. t4_rq_host_wq_pidx(&qp->wq),
  1247. t4_rq_wq_size(&qp->wq));
  1248. if (ret) {
  1249. pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
  1250. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1251. spin_unlock(&qp->lock);
  1252. spin_unlock_irq(&qp->rhp->lock);
  1253. return;
  1254. }
  1255. qp->wq.rq.wq_pidx_inc = 0;
  1256. spin_unlock(&qp->lock);
  1257. spin_unlock_irq(&qp->rhp->lock);
  1258. /* Wait for the dbfifo to drain */
  1259. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1260. set_current_state(TASK_UNINTERRUPTIBLE);
  1261. schedule_timeout(usecs_to_jiffies(10));
  1262. }
  1263. }
  1264. }
  1265. static void recover_queues(struct uld_ctx *ctx)
  1266. {
  1267. int count = 0;
  1268. struct qp_list qp_list;
  1269. int ret;
  1270. /* slow everybody down */
  1271. set_current_state(TASK_UNINTERRUPTIBLE);
  1272. schedule_timeout(usecs_to_jiffies(1000));
  1273. /* flush the SGE contexts */
  1274. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1275. if (ret) {
  1276. pr_err("%s: Fatal error - DB overflow recovery failed\n",
  1277. pci_name(ctx->lldi.pdev));
  1278. return;
  1279. }
  1280. /* Count active queues so we can build a list of queues to recover */
  1281. spin_lock_irq(&ctx->dev->lock);
  1282. WARN_ON(ctx->dev->db_state != STOPPED);
  1283. ctx->dev->db_state = RECOVERY;
  1284. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1285. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1286. if (!qp_list.qps) {
  1287. spin_unlock_irq(&ctx->dev->lock);
  1288. return;
  1289. }
  1290. qp_list.idx = 0;
  1291. /* add and ref each qp so it doesn't get freed */
  1292. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1293. spin_unlock_irq(&ctx->dev->lock);
  1294. /* now traverse the list in a safe context to recover the db state*/
  1295. recover_lost_dbs(ctx, &qp_list);
  1296. /* we're almost done! deref the qps and clean up */
  1297. deref_qps(&qp_list);
  1298. kfree(qp_list.qps);
  1299. spin_lock_irq(&ctx->dev->lock);
  1300. WARN_ON(ctx->dev->db_state != RECOVERY);
  1301. ctx->dev->db_state = STOPPED;
  1302. spin_unlock_irq(&ctx->dev->lock);
  1303. }
  1304. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1305. {
  1306. struct uld_ctx *ctx = handle;
  1307. switch (control) {
  1308. case CXGB4_CONTROL_DB_FULL:
  1309. stop_queues(ctx);
  1310. ctx->dev->rdev.stats.db_full++;
  1311. break;
  1312. case CXGB4_CONTROL_DB_EMPTY:
  1313. resume_queues(ctx);
  1314. mutex_lock(&ctx->dev->rdev.stats.lock);
  1315. ctx->dev->rdev.stats.db_empty++;
  1316. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1317. break;
  1318. case CXGB4_CONTROL_DB_DROP:
  1319. recover_queues(ctx);
  1320. mutex_lock(&ctx->dev->rdev.stats.lock);
  1321. ctx->dev->rdev.stats.db_drop++;
  1322. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1323. break;
  1324. default:
  1325. pr_warn("%s: unknown control cmd %u\n",
  1326. pci_name(ctx->lldi.pdev), control);
  1327. break;
  1328. }
  1329. return 0;
  1330. }
  1331. static struct cxgb4_uld_info c4iw_uld_info = {
  1332. .name = DRV_NAME,
  1333. .nrxq = MAX_ULD_QSETS,
  1334. .ntxq = MAX_ULD_QSETS,
  1335. .rxq_size = 511,
  1336. .ciq = true,
  1337. .lro = false,
  1338. .add = c4iw_uld_add,
  1339. .rx_handler = c4iw_uld_rx_handler,
  1340. .state_change = c4iw_uld_state_change,
  1341. .control = c4iw_uld_control,
  1342. };
  1343. static int __init c4iw_init_module(void)
  1344. {
  1345. int err;
  1346. err = c4iw_cm_init();
  1347. if (err)
  1348. return err;
  1349. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1350. if (!c4iw_debugfs_root)
  1351. pr_warn("could not create debugfs entry, continuing\n");
  1352. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1353. return 0;
  1354. }
  1355. static void __exit c4iw_exit_module(void)
  1356. {
  1357. struct uld_ctx *ctx, *tmp;
  1358. mutex_lock(&dev_mutex);
  1359. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1360. if (ctx->dev)
  1361. c4iw_remove(ctx);
  1362. kfree(ctx);
  1363. }
  1364. mutex_unlock(&dev_mutex);
  1365. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1366. c4iw_cm_term();
  1367. debugfs_remove_recursive(c4iw_debugfs_root);
  1368. }
  1369. module_init(c4iw_init_module);
  1370. module_exit(c4iw_exit_module);