afe4403.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635
  1. /*
  2. * AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters
  3. *
  4. * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
  5. * Andrew F. Davis <afd@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. */
  16. #include <linux/device.h>
  17. #include <linux/err.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/regmap.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/sysfs.h>
  24. #include <linux/regulator/consumer.h>
  25. #include <linux/iio/iio.h>
  26. #include <linux/iio/sysfs.h>
  27. #include <linux/iio/buffer.h>
  28. #include <linux/iio/trigger.h>
  29. #include <linux/iio/triggered_buffer.h>
  30. #include <linux/iio/trigger_consumer.h>
  31. #include "afe440x.h"
  32. #define AFE4403_DRIVER_NAME "afe4403"
  33. /* AFE4403 Registers */
  34. #define AFE4403_TIAGAIN 0x20
  35. #define AFE4403_TIA_AMB_GAIN 0x21
  36. enum afe4403_fields {
  37. /* Gains */
  38. F_RF_LED1, F_CF_LED1,
  39. F_RF_LED, F_CF_LED,
  40. /* LED Current */
  41. F_ILED1, F_ILED2,
  42. /* sentinel */
  43. F_MAX_FIELDS
  44. };
  45. static const struct reg_field afe4403_reg_fields[] = {
  46. /* Gains */
  47. [F_RF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 0, 2),
  48. [F_CF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 3, 7),
  49. [F_RF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
  50. [F_CF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
  51. /* LED Current */
  52. [F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
  53. [F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
  54. };
  55. /**
  56. * struct afe4403_data - AFE4403 device instance data
  57. * @dev: Device structure
  58. * @spi: SPI device handle
  59. * @regmap: Register map of the device
  60. * @fields: Register fields of the device
  61. * @regulator: Pointer to the regulator for the IC
  62. * @trig: IIO trigger for this device
  63. * @irq: ADC_RDY line interrupt number
  64. * @buffer: Used to construct data layout to push into IIO buffer.
  65. */
  66. struct afe4403_data {
  67. struct device *dev;
  68. struct spi_device *spi;
  69. struct regmap *regmap;
  70. struct regmap_field *fields[F_MAX_FIELDS];
  71. struct regulator *regulator;
  72. struct iio_trigger *trig;
  73. int irq;
  74. /* Ensure suitable alignment for timestamp */
  75. s32 buffer[8] __aligned(8);
  76. };
  77. enum afe4403_chan_id {
  78. LED2 = 1,
  79. ALED2,
  80. LED1,
  81. ALED1,
  82. LED2_ALED2,
  83. LED1_ALED1,
  84. };
  85. static const unsigned int afe4403_channel_values[] = {
  86. [LED2] = AFE440X_LED2VAL,
  87. [ALED2] = AFE440X_ALED2VAL,
  88. [LED1] = AFE440X_LED1VAL,
  89. [ALED1] = AFE440X_ALED1VAL,
  90. [LED2_ALED2] = AFE440X_LED2_ALED2VAL,
  91. [LED1_ALED1] = AFE440X_LED1_ALED1VAL,
  92. };
  93. static const unsigned int afe4403_channel_leds[] = {
  94. [LED2] = F_ILED2,
  95. [LED1] = F_ILED1,
  96. };
  97. static const struct iio_chan_spec afe4403_channels[] = {
  98. /* ADC values */
  99. AFE440X_INTENSITY_CHAN(LED2, 0),
  100. AFE440X_INTENSITY_CHAN(ALED2, 0),
  101. AFE440X_INTENSITY_CHAN(LED1, 0),
  102. AFE440X_INTENSITY_CHAN(ALED1, 0),
  103. AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
  104. AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
  105. /* LED current */
  106. AFE440X_CURRENT_CHAN(LED2),
  107. AFE440X_CURRENT_CHAN(LED1),
  108. };
  109. static const struct afe440x_val_table afe4403_res_table[] = {
  110. { 500000 }, { 250000 }, { 100000 }, { 50000 },
  111. { 25000 }, { 10000 }, { 1000000 }, { 0 },
  112. };
  113. AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
  114. static const struct afe440x_val_table afe4403_cap_table[] = {
  115. { 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
  116. { 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
  117. { 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
  118. { 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
  119. { 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
  120. { 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
  121. { 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
  122. { 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
  123. };
  124. AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
  125. static ssize_t afe440x_show_register(struct device *dev,
  126. struct device_attribute *attr,
  127. char *buf)
  128. {
  129. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  130. struct afe4403_data *afe = iio_priv(indio_dev);
  131. struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
  132. unsigned int reg_val;
  133. int vals[2];
  134. int ret;
  135. ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
  136. if (ret)
  137. return ret;
  138. if (reg_val >= afe440x_attr->table_size)
  139. return -EINVAL;
  140. vals[0] = afe440x_attr->val_table[reg_val].integer;
  141. vals[1] = afe440x_attr->val_table[reg_val].fract;
  142. return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
  143. }
  144. static ssize_t afe440x_store_register(struct device *dev,
  145. struct device_attribute *attr,
  146. const char *buf, size_t count)
  147. {
  148. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  149. struct afe4403_data *afe = iio_priv(indio_dev);
  150. struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
  151. int val, integer, fract, ret;
  152. ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
  153. if (ret)
  154. return ret;
  155. for (val = 0; val < afe440x_attr->table_size; val++)
  156. if (afe440x_attr->val_table[val].integer == integer &&
  157. afe440x_attr->val_table[val].fract == fract)
  158. break;
  159. if (val == afe440x_attr->table_size)
  160. return -EINVAL;
  161. ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
  162. if (ret)
  163. return ret;
  164. return count;
  165. }
  166. static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
  167. static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
  168. static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
  169. static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
  170. static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
  171. static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
  172. static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
  173. static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
  174. static struct attribute *afe440x_attributes[] = {
  175. &dev_attr_in_intensity_resistance_available.attr,
  176. &dev_attr_in_intensity_capacitance_available.attr,
  177. &afe440x_attr_in_intensity1_resistance.dev_attr.attr,
  178. &afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
  179. &afe440x_attr_in_intensity2_resistance.dev_attr.attr,
  180. &afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
  181. &afe440x_attr_in_intensity3_resistance.dev_attr.attr,
  182. &afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
  183. &afe440x_attr_in_intensity4_resistance.dev_attr.attr,
  184. &afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
  185. NULL
  186. };
  187. static const struct attribute_group afe440x_attribute_group = {
  188. .attrs = afe440x_attributes
  189. };
  190. static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
  191. {
  192. u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
  193. u8 rx[3];
  194. int ret;
  195. /* Enable reading from the device */
  196. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  197. if (ret)
  198. return ret;
  199. ret = spi_write_then_read(afe->spi, &reg, 1, rx, 3);
  200. if (ret)
  201. return ret;
  202. *val = (rx[0] << 16) |
  203. (rx[1] << 8) |
  204. (rx[2]);
  205. /* Disable reading from the device */
  206. tx[3] = AFE440X_CONTROL0_WRITE;
  207. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  208. if (ret)
  209. return ret;
  210. return 0;
  211. }
  212. static int afe4403_read_raw(struct iio_dev *indio_dev,
  213. struct iio_chan_spec const *chan,
  214. int *val, int *val2, long mask)
  215. {
  216. struct afe4403_data *afe = iio_priv(indio_dev);
  217. unsigned int reg = afe4403_channel_values[chan->address];
  218. unsigned int field = afe4403_channel_leds[chan->address];
  219. int ret;
  220. switch (chan->type) {
  221. case IIO_INTENSITY:
  222. switch (mask) {
  223. case IIO_CHAN_INFO_RAW:
  224. ret = afe4403_read(afe, reg, val);
  225. if (ret)
  226. return ret;
  227. return IIO_VAL_INT;
  228. }
  229. break;
  230. case IIO_CURRENT:
  231. switch (mask) {
  232. case IIO_CHAN_INFO_RAW:
  233. ret = regmap_field_read(afe->fields[field], val);
  234. if (ret)
  235. return ret;
  236. return IIO_VAL_INT;
  237. case IIO_CHAN_INFO_SCALE:
  238. *val = 0;
  239. *val2 = 800000;
  240. return IIO_VAL_INT_PLUS_MICRO;
  241. }
  242. break;
  243. default:
  244. break;
  245. }
  246. return -EINVAL;
  247. }
  248. static int afe4403_write_raw(struct iio_dev *indio_dev,
  249. struct iio_chan_spec const *chan,
  250. int val, int val2, long mask)
  251. {
  252. struct afe4403_data *afe = iio_priv(indio_dev);
  253. unsigned int field = afe4403_channel_leds[chan->address];
  254. switch (chan->type) {
  255. case IIO_CURRENT:
  256. switch (mask) {
  257. case IIO_CHAN_INFO_RAW:
  258. return regmap_field_write(afe->fields[field], val);
  259. }
  260. break;
  261. default:
  262. break;
  263. }
  264. return -EINVAL;
  265. }
  266. static const struct iio_info afe4403_iio_info = {
  267. .attrs = &afe440x_attribute_group,
  268. .read_raw = afe4403_read_raw,
  269. .write_raw = afe4403_write_raw,
  270. .driver_module = THIS_MODULE,
  271. };
  272. static irqreturn_t afe4403_trigger_handler(int irq, void *private)
  273. {
  274. struct iio_poll_func *pf = private;
  275. struct iio_dev *indio_dev = pf->indio_dev;
  276. struct afe4403_data *afe = iio_priv(indio_dev);
  277. int ret, bit, i = 0;
  278. u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
  279. u8 rx[3];
  280. /* Enable reading from the device */
  281. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  282. if (ret)
  283. goto err;
  284. for_each_set_bit(bit, indio_dev->active_scan_mask,
  285. indio_dev->masklength) {
  286. ret = spi_write_then_read(afe->spi,
  287. &afe4403_channel_values[bit], 1,
  288. rx, 3);
  289. if (ret)
  290. goto err;
  291. afe->buffer[i++] = (rx[0] << 16) |
  292. (rx[1] << 8) |
  293. (rx[2]);
  294. }
  295. /* Disable reading from the device */
  296. tx[3] = AFE440X_CONTROL0_WRITE;
  297. ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
  298. if (ret)
  299. goto err;
  300. iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
  301. pf->timestamp);
  302. err:
  303. iio_trigger_notify_done(indio_dev->trig);
  304. return IRQ_HANDLED;
  305. }
  306. static const struct iio_trigger_ops afe4403_trigger_ops = {
  307. .owner = THIS_MODULE,
  308. };
  309. #define AFE4403_TIMING_PAIRS \
  310. { AFE440X_LED2STC, 0x000050 }, \
  311. { AFE440X_LED2ENDC, 0x0003e7 }, \
  312. { AFE440X_LED1LEDSTC, 0x0007d0 }, \
  313. { AFE440X_LED1LEDENDC, 0x000bb7 }, \
  314. { AFE440X_ALED2STC, 0x000438 }, \
  315. { AFE440X_ALED2ENDC, 0x0007cf }, \
  316. { AFE440X_LED1STC, 0x000820 }, \
  317. { AFE440X_LED1ENDC, 0x000bb7 }, \
  318. { AFE440X_LED2LEDSTC, 0x000000 }, \
  319. { AFE440X_LED2LEDENDC, 0x0003e7 }, \
  320. { AFE440X_ALED1STC, 0x000c08 }, \
  321. { AFE440X_ALED1ENDC, 0x000f9f }, \
  322. { AFE440X_LED2CONVST, 0x0003ef }, \
  323. { AFE440X_LED2CONVEND, 0x0007cf }, \
  324. { AFE440X_ALED2CONVST, 0x0007d7 }, \
  325. { AFE440X_ALED2CONVEND, 0x000bb7 }, \
  326. { AFE440X_LED1CONVST, 0x000bbf }, \
  327. { AFE440X_LED1CONVEND, 0x009c3f }, \
  328. { AFE440X_ALED1CONVST, 0x000fa7 }, \
  329. { AFE440X_ALED1CONVEND, 0x001387 }, \
  330. { AFE440X_ADCRSTSTCT0, 0x0003e8 }, \
  331. { AFE440X_ADCRSTENDCT0, 0x0003eb }, \
  332. { AFE440X_ADCRSTSTCT1, 0x0007d0 }, \
  333. { AFE440X_ADCRSTENDCT1, 0x0007d3 }, \
  334. { AFE440X_ADCRSTSTCT2, 0x000bb8 }, \
  335. { AFE440X_ADCRSTENDCT2, 0x000bbb }, \
  336. { AFE440X_ADCRSTSTCT3, 0x000fa0 }, \
  337. { AFE440X_ADCRSTENDCT3, 0x000fa3 }, \
  338. { AFE440X_PRPCOUNT, 0x009c3f }, \
  339. { AFE440X_PDNCYCLESTC, 0x001518 }, \
  340. { AFE440X_PDNCYCLEENDC, 0x00991f }
  341. static const struct reg_sequence afe4403_reg_sequences[] = {
  342. AFE4403_TIMING_PAIRS,
  343. { AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
  344. { AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
  345. };
  346. static const struct regmap_range afe4403_yes_ranges[] = {
  347. regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
  348. };
  349. static const struct regmap_access_table afe4403_volatile_table = {
  350. .yes_ranges = afe4403_yes_ranges,
  351. .n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
  352. };
  353. static const struct regmap_config afe4403_regmap_config = {
  354. .reg_bits = 8,
  355. .val_bits = 24,
  356. .max_register = AFE440X_PDNCYCLEENDC,
  357. .cache_type = REGCACHE_RBTREE,
  358. .volatile_table = &afe4403_volatile_table,
  359. };
  360. static const struct of_device_id afe4403_of_match[] = {
  361. { .compatible = "ti,afe4403", },
  362. { /* sentinel */ }
  363. };
  364. MODULE_DEVICE_TABLE(of, afe4403_of_match);
  365. static int __maybe_unused afe4403_suspend(struct device *dev)
  366. {
  367. struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
  368. struct afe4403_data *afe = iio_priv(indio_dev);
  369. int ret;
  370. ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
  371. AFE440X_CONTROL2_PDN_AFE,
  372. AFE440X_CONTROL2_PDN_AFE);
  373. if (ret)
  374. return ret;
  375. ret = regulator_disable(afe->regulator);
  376. if (ret) {
  377. dev_err(dev, "Unable to disable regulator\n");
  378. return ret;
  379. }
  380. return 0;
  381. }
  382. static int __maybe_unused afe4403_resume(struct device *dev)
  383. {
  384. struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
  385. struct afe4403_data *afe = iio_priv(indio_dev);
  386. int ret;
  387. ret = regulator_enable(afe->regulator);
  388. if (ret) {
  389. dev_err(dev, "Unable to enable regulator\n");
  390. return ret;
  391. }
  392. ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
  393. AFE440X_CONTROL2_PDN_AFE, 0);
  394. if (ret)
  395. return ret;
  396. return 0;
  397. }
  398. static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
  399. static int afe4403_probe(struct spi_device *spi)
  400. {
  401. struct iio_dev *indio_dev;
  402. struct afe4403_data *afe;
  403. int i, ret;
  404. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
  405. if (!indio_dev)
  406. return -ENOMEM;
  407. afe = iio_priv(indio_dev);
  408. spi_set_drvdata(spi, indio_dev);
  409. afe->dev = &spi->dev;
  410. afe->spi = spi;
  411. afe->irq = spi->irq;
  412. afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
  413. if (IS_ERR(afe->regmap)) {
  414. dev_err(afe->dev, "Unable to allocate register map\n");
  415. return PTR_ERR(afe->regmap);
  416. }
  417. for (i = 0; i < F_MAX_FIELDS; i++) {
  418. afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
  419. afe4403_reg_fields[i]);
  420. if (IS_ERR(afe->fields[i])) {
  421. dev_err(afe->dev, "Unable to allocate regmap fields\n");
  422. return PTR_ERR(afe->fields[i]);
  423. }
  424. }
  425. afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
  426. if (IS_ERR(afe->regulator)) {
  427. dev_err(afe->dev, "Unable to get regulator\n");
  428. return PTR_ERR(afe->regulator);
  429. }
  430. ret = regulator_enable(afe->regulator);
  431. if (ret) {
  432. dev_err(afe->dev, "Unable to enable regulator\n");
  433. return ret;
  434. }
  435. ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
  436. AFE440X_CONTROL0_SW_RESET);
  437. if (ret) {
  438. dev_err(afe->dev, "Unable to reset device\n");
  439. goto err_disable_reg;
  440. }
  441. ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
  442. ARRAY_SIZE(afe4403_reg_sequences));
  443. if (ret) {
  444. dev_err(afe->dev, "Unable to set register defaults\n");
  445. goto err_disable_reg;
  446. }
  447. indio_dev->modes = INDIO_DIRECT_MODE;
  448. indio_dev->dev.parent = afe->dev;
  449. indio_dev->channels = afe4403_channels;
  450. indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
  451. indio_dev->name = AFE4403_DRIVER_NAME;
  452. indio_dev->info = &afe4403_iio_info;
  453. if (afe->irq > 0) {
  454. afe->trig = devm_iio_trigger_alloc(afe->dev,
  455. "%s-dev%d",
  456. indio_dev->name,
  457. indio_dev->id);
  458. if (!afe->trig) {
  459. dev_err(afe->dev, "Unable to allocate IIO trigger\n");
  460. ret = -ENOMEM;
  461. goto err_disable_reg;
  462. }
  463. iio_trigger_set_drvdata(afe->trig, indio_dev);
  464. afe->trig->ops = &afe4403_trigger_ops;
  465. afe->trig->dev.parent = afe->dev;
  466. ret = iio_trigger_register(afe->trig);
  467. if (ret) {
  468. dev_err(afe->dev, "Unable to register IIO trigger\n");
  469. goto err_disable_reg;
  470. }
  471. ret = devm_request_threaded_irq(afe->dev, afe->irq,
  472. iio_trigger_generic_data_rdy_poll,
  473. NULL, IRQF_ONESHOT,
  474. AFE4403_DRIVER_NAME,
  475. afe->trig);
  476. if (ret) {
  477. dev_err(afe->dev, "Unable to request IRQ\n");
  478. goto err_trig;
  479. }
  480. }
  481. ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
  482. afe4403_trigger_handler, NULL);
  483. if (ret) {
  484. dev_err(afe->dev, "Unable to setup buffer\n");
  485. goto err_trig;
  486. }
  487. ret = iio_device_register(indio_dev);
  488. if (ret) {
  489. dev_err(afe->dev, "Unable to register IIO device\n");
  490. goto err_buff;
  491. }
  492. return 0;
  493. err_buff:
  494. iio_triggered_buffer_cleanup(indio_dev);
  495. err_trig:
  496. if (afe->irq > 0)
  497. iio_trigger_unregister(afe->trig);
  498. err_disable_reg:
  499. regulator_disable(afe->regulator);
  500. return ret;
  501. }
  502. static int afe4403_remove(struct spi_device *spi)
  503. {
  504. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  505. struct afe4403_data *afe = iio_priv(indio_dev);
  506. int ret;
  507. iio_device_unregister(indio_dev);
  508. iio_triggered_buffer_cleanup(indio_dev);
  509. if (afe->irq > 0)
  510. iio_trigger_unregister(afe->trig);
  511. ret = regulator_disable(afe->regulator);
  512. if (ret) {
  513. dev_err(afe->dev, "Unable to disable regulator\n");
  514. return ret;
  515. }
  516. return 0;
  517. }
  518. static const struct spi_device_id afe4403_ids[] = {
  519. { "afe4403", 0 },
  520. { /* sentinel */ }
  521. };
  522. MODULE_DEVICE_TABLE(spi, afe4403_ids);
  523. static struct spi_driver afe4403_spi_driver = {
  524. .driver = {
  525. .name = AFE4403_DRIVER_NAME,
  526. .of_match_table = afe4403_of_match,
  527. .pm = &afe4403_pm_ops,
  528. },
  529. .probe = afe4403_probe,
  530. .remove = afe4403_remove,
  531. .id_table = afe4403_ids,
  532. };
  533. module_spi_driver(afe4403_spi_driver);
  534. MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
  535. MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
  536. MODULE_LICENSE("GPL v2");