sca3000.c 42 KB

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  1. /*
  2. * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License version 2 as published by
  6. * the Free Software Foundation.
  7. *
  8. * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
  9. *
  10. * See industrialio/accels/sca3000.h for comments.
  11. */
  12. #include <linux/interrupt.h>
  13. #include <linux/fs.h>
  14. #include <linux/device.h>
  15. #include <linux/slab.h>
  16. #include <linux/kernel.h>
  17. #include <linux/spi/spi.h>
  18. #include <linux/sysfs.h>
  19. #include <linux/module.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/iio/iio.h>
  22. #include <linux/iio/sysfs.h>
  23. #include <linux/iio/events.h>
  24. #include <linux/iio/buffer.h>
  25. #include <linux/iio/kfifo_buf.h>
  26. #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
  27. #define SCA3000_READ_REG(a) ((a) << 2)
  28. #define SCA3000_REG_REVID_ADDR 0x00
  29. #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
  30. #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
  31. #define SCA3000_REG_STATUS_ADDR 0x02
  32. #define SCA3000_LOCKED BIT(5)
  33. #define SCA3000_EEPROM_CS_ERROR BIT(1)
  34. #define SCA3000_SPI_FRAME_ERROR BIT(0)
  35. /* All reads done using register decrement so no need to directly access LSBs */
  36. #define SCA3000_REG_X_MSB_ADDR 0x05
  37. #define SCA3000_REG_Y_MSB_ADDR 0x07
  38. #define SCA3000_REG_Z_MSB_ADDR 0x09
  39. #define SCA3000_REG_RING_OUT_ADDR 0x0f
  40. /* Temp read untested - the e05 doesn't have the sensor */
  41. #define SCA3000_REG_TEMP_MSB_ADDR 0x13
  42. #define SCA3000_REG_MODE_ADDR 0x14
  43. #define SCA3000_MODE_PROT_MASK 0x28
  44. #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
  45. #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
  46. /*
  47. * Free fall detection triggers an interrupt if the acceleration
  48. * is below a threshold for equivalent of 25cm drop
  49. */
  50. #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
  51. #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
  52. #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
  53. #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
  54. /*
  55. * In motion detection mode the accelerations are band pass filtered
  56. * (approx 1 - 25Hz) and then a programmable threshold used to trigger
  57. * and interrupt.
  58. */
  59. #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
  60. #define SCA3000_REG_MODE_MODE_MASK 0x03
  61. #define SCA3000_REG_BUF_COUNT_ADDR 0x15
  62. #define SCA3000_REG_INT_STATUS_ADDR 0x16
  63. #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
  64. #define SCA3000_REG_INT_STATUS_HALF BIT(6)
  65. #define SCA3000_INT_STATUS_FREE_FALL BIT(3)
  66. #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
  67. #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
  68. #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
  69. /* Used to allow access to multiplexed registers */
  70. #define SCA3000_REG_CTRL_SEL_ADDR 0x18
  71. /* Only available for SCA3000-D03 and SCA3000-D01 */
  72. #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
  73. #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
  74. #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
  75. #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
  76. #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
  77. /*
  78. * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
  79. * will not function
  80. */
  81. #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
  82. #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
  83. #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
  84. #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
  85. #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
  86. #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
  87. #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
  88. #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
  89. /*
  90. * Control which motion detector interrupts are on.
  91. * For now only OR combinations are supported.
  92. */
  93. #define SCA3000_MD_CTRL_PROT_MASK 0xC0
  94. #define SCA3000_MD_CTRL_OR_Y BIT(0)
  95. #define SCA3000_MD_CTRL_OR_X BIT(1)
  96. #define SCA3000_MD_CTRL_OR_Z BIT(2)
  97. /* Currently unsupported */
  98. #define SCA3000_MD_CTRL_AND_Y BIT(3)
  99. #define SCA3000_MD_CTRL_AND_X BIT(4)
  100. #define SAC3000_MD_CTRL_AND_Z BIT(5)
  101. /*
  102. * Some control registers of complex access methods requiring this register to
  103. * be used to remove a lock.
  104. */
  105. #define SCA3000_REG_UNLOCK_ADDR 0x1e
  106. #define SCA3000_REG_INT_MASK_ADDR 0x21
  107. #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
  108. #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
  109. #define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
  110. #define SCA3000_REG_INT_MASK_ALL_INTS 0x02
  111. #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
  112. #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
  113. /* Values of multiplexed registers (write to ctrl_data after select) */
  114. #define SCA3000_REG_CTRL_DATA_ADDR 0x22
  115. /*
  116. * Measurement modes available on some sca3000 series chips. Code assumes others
  117. * may become available in the future.
  118. *
  119. * Bypass - Bypass the low-pass filter in the signal channel so as to increase
  120. * signal bandwidth.
  121. *
  122. * Narrow - Narrow low-pass filtering of the signal channel and half output
  123. * data rate by decimation.
  124. *
  125. * Wide - Widen low-pass filtering of signal channel to increase bandwidth
  126. */
  127. #define SCA3000_OP_MODE_BYPASS 0x01
  128. #define SCA3000_OP_MODE_NARROW 0x02
  129. #define SCA3000_OP_MODE_WIDE 0x04
  130. #define SCA3000_MAX_TX 6
  131. #define SCA3000_MAX_RX 2
  132. /**
  133. * struct sca3000_state - device instance state information
  134. * @us: the associated spi device
  135. * @info: chip variant information
  136. * @last_timestamp: the timestamp of the last event
  137. * @mo_det_use_count: reference counter for the motion detection unit
  138. * @lock: lock used to protect elements of sca3000_state
  139. * and the underlying device state.
  140. * @tx: dma-able transmit buffer
  141. * @rx: dma-able receive buffer
  142. **/
  143. struct sca3000_state {
  144. struct spi_device *us;
  145. const struct sca3000_chip_info *info;
  146. s64 last_timestamp;
  147. int mo_det_use_count;
  148. struct mutex lock;
  149. /* Can these share a cacheline ? */
  150. u8 rx[384] ____cacheline_aligned;
  151. u8 tx[6] ____cacheline_aligned;
  152. };
  153. /**
  154. * struct sca3000_chip_info - model dependent parameters
  155. * @scale: scale * 10^-6
  156. * @temp_output: some devices have temperature sensors.
  157. * @measurement_mode_freq: normal mode sampling frequency
  158. * @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for
  159. * the normal measurement mode.
  160. * @option_mode_1: first optional mode. Not all models have one
  161. * @option_mode_1_freq: option mode 1 sampling frequency
  162. * @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for
  163. * the first option mode.
  164. * @option_mode_2: second optional mode. Not all chips have one
  165. * @option_mode_2_freq: option mode 2 sampling frequency
  166. * @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for
  167. * the second option mode.
  168. * @mod_det_mult_xz: Bit wise multipliers to calculate the threshold
  169. * for motion detection in the x and z axis.
  170. * @mod_det_mult_y: Bit wise multipliers to calculate the threshold
  171. * for motion detection in the y axis.
  172. *
  173. * This structure is used to hold information about the functionality of a given
  174. * sca3000 variant.
  175. **/
  176. struct sca3000_chip_info {
  177. unsigned int scale;
  178. bool temp_output;
  179. int measurement_mode_freq;
  180. int measurement_mode_3db_freq;
  181. int option_mode_1;
  182. int option_mode_1_freq;
  183. int option_mode_1_3db_freq;
  184. int option_mode_2;
  185. int option_mode_2_freq;
  186. int option_mode_2_3db_freq;
  187. int mot_det_mult_xz[6];
  188. int mot_det_mult_y[7];
  189. };
  190. enum sca3000_variant {
  191. d01,
  192. e02,
  193. e04,
  194. e05,
  195. };
  196. /*
  197. * Note where option modes are not defined, the chip simply does not
  198. * support any.
  199. * Other chips in the sca3000 series use i2c and are not included here.
  200. *
  201. * Some of these devices are only listed in the family data sheet and
  202. * do not actually appear to be available.
  203. */
  204. static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
  205. [d01] = {
  206. .scale = 7357,
  207. .temp_output = true,
  208. .measurement_mode_freq = 250,
  209. .measurement_mode_3db_freq = 45,
  210. .option_mode_1 = SCA3000_OP_MODE_BYPASS,
  211. .option_mode_1_freq = 250,
  212. .option_mode_1_3db_freq = 70,
  213. .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
  214. .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
  215. },
  216. [e02] = {
  217. .scale = 9810,
  218. .measurement_mode_freq = 125,
  219. .measurement_mode_3db_freq = 40,
  220. .option_mode_1 = SCA3000_OP_MODE_NARROW,
  221. .option_mode_1_freq = 63,
  222. .option_mode_1_3db_freq = 11,
  223. .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
  224. .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
  225. },
  226. [e04] = {
  227. .scale = 19620,
  228. .measurement_mode_freq = 100,
  229. .measurement_mode_3db_freq = 38,
  230. .option_mode_1 = SCA3000_OP_MODE_NARROW,
  231. .option_mode_1_freq = 50,
  232. .option_mode_1_3db_freq = 9,
  233. .option_mode_2 = SCA3000_OP_MODE_WIDE,
  234. .option_mode_2_freq = 400,
  235. .option_mode_2_3db_freq = 70,
  236. .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
  237. .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
  238. },
  239. [e05] = {
  240. .scale = 61313,
  241. .measurement_mode_freq = 200,
  242. .measurement_mode_3db_freq = 60,
  243. .option_mode_1 = SCA3000_OP_MODE_NARROW,
  244. .option_mode_1_freq = 50,
  245. .option_mode_1_3db_freq = 9,
  246. .option_mode_2 = SCA3000_OP_MODE_WIDE,
  247. .option_mode_2_freq = 400,
  248. .option_mode_2_3db_freq = 75,
  249. .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
  250. .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
  251. },
  252. };
  253. static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
  254. {
  255. st->tx[0] = SCA3000_WRITE_REG(address);
  256. st->tx[1] = val;
  257. return spi_write(st->us, st->tx, 2);
  258. }
  259. static int sca3000_read_data_short(struct sca3000_state *st,
  260. u8 reg_address_high,
  261. int len)
  262. {
  263. struct spi_transfer xfer[2] = {
  264. {
  265. .len = 1,
  266. .tx_buf = st->tx,
  267. }, {
  268. .len = len,
  269. .rx_buf = st->rx,
  270. }
  271. };
  272. st->tx[0] = SCA3000_READ_REG(reg_address_high);
  273. return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
  274. }
  275. /**
  276. * sca3000_reg_lock_on() - test if the ctrl register lock is on
  277. * @st: Driver specific device instance data.
  278. *
  279. * Lock must be held.
  280. **/
  281. static int sca3000_reg_lock_on(struct sca3000_state *st)
  282. {
  283. int ret;
  284. ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
  285. if (ret < 0)
  286. return ret;
  287. return !(st->rx[0] & SCA3000_LOCKED);
  288. }
  289. /**
  290. * __sca3000_unlock_reg_lock() - unlock the control registers
  291. * @st: Driver specific device instance data.
  292. *
  293. * Note the device does not appear to support doing this in a single transfer.
  294. * This should only ever be used as part of ctrl reg read.
  295. * Lock must be held before calling this
  296. */
  297. static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
  298. {
  299. struct spi_transfer xfer[3] = {
  300. {
  301. .len = 2,
  302. .cs_change = 1,
  303. .tx_buf = st->tx,
  304. }, {
  305. .len = 2,
  306. .cs_change = 1,
  307. .tx_buf = st->tx + 2,
  308. }, {
  309. .len = 2,
  310. .tx_buf = st->tx + 4,
  311. },
  312. };
  313. st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
  314. st->tx[1] = 0x00;
  315. st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
  316. st->tx[3] = 0x50;
  317. st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
  318. st->tx[5] = 0xA0;
  319. return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
  320. }
  321. /**
  322. * sca3000_write_ctrl_reg() write to a lock protect ctrl register
  323. * @st: Driver specific device instance data.
  324. * @sel: selects which registers we wish to write to
  325. * @val: the value to be written
  326. *
  327. * Certain control registers are protected against overwriting by the lock
  328. * register and use a shared write address. This function allows writing of
  329. * these registers.
  330. * Lock must be held.
  331. */
  332. static int sca3000_write_ctrl_reg(struct sca3000_state *st,
  333. u8 sel,
  334. uint8_t val)
  335. {
  336. int ret;
  337. ret = sca3000_reg_lock_on(st);
  338. if (ret < 0)
  339. goto error_ret;
  340. if (ret) {
  341. ret = __sca3000_unlock_reg_lock(st);
  342. if (ret)
  343. goto error_ret;
  344. }
  345. /* Set the control select register */
  346. ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
  347. if (ret)
  348. goto error_ret;
  349. /* Write the actual value into the register */
  350. ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
  351. error_ret:
  352. return ret;
  353. }
  354. /**
  355. * sca3000_read_ctrl_reg() read from lock protected control register.
  356. * @st: Driver specific device instance data.
  357. * @ctrl_reg: Which ctrl register do we want to read.
  358. *
  359. * Lock must be held.
  360. */
  361. static int sca3000_read_ctrl_reg(struct sca3000_state *st,
  362. u8 ctrl_reg)
  363. {
  364. int ret;
  365. ret = sca3000_reg_lock_on(st);
  366. if (ret < 0)
  367. goto error_ret;
  368. if (ret) {
  369. ret = __sca3000_unlock_reg_lock(st);
  370. if (ret)
  371. goto error_ret;
  372. }
  373. /* Set the control select register */
  374. ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
  375. if (ret)
  376. goto error_ret;
  377. ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
  378. if (ret)
  379. goto error_ret;
  380. return st->rx[0];
  381. error_ret:
  382. return ret;
  383. }
  384. /**
  385. * sca3000_show_rev() - sysfs interface to read the chip revision number
  386. * @indio_dev: Device instance specific generic IIO data.
  387. * Driver specific device instance data can be obtained via
  388. * via iio_priv(indio_dev)
  389. */
  390. static int sca3000_print_rev(struct iio_dev *indio_dev)
  391. {
  392. int ret;
  393. struct sca3000_state *st = iio_priv(indio_dev);
  394. mutex_lock(&st->lock);
  395. ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
  396. if (ret < 0)
  397. goto error_ret;
  398. dev_info(&indio_dev->dev,
  399. "sca3000 revision major=%lu, minor=%lu\n",
  400. st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
  401. st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
  402. error_ret:
  403. mutex_unlock(&st->lock);
  404. return ret;
  405. }
  406. static ssize_t
  407. sca3000_show_available_3db_freqs(struct device *dev,
  408. struct device_attribute *attr,
  409. char *buf)
  410. {
  411. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  412. struct sca3000_state *st = iio_priv(indio_dev);
  413. int len;
  414. len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
  415. if (st->info->option_mode_1)
  416. len += sprintf(buf + len, " %d",
  417. st->info->option_mode_1_3db_freq);
  418. if (st->info->option_mode_2)
  419. len += sprintf(buf + len, " %d",
  420. st->info->option_mode_2_3db_freq);
  421. len += sprintf(buf + len, "\n");
  422. return len;
  423. }
  424. static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
  425. S_IRUGO, sca3000_show_available_3db_freqs,
  426. NULL, 0);
  427. static const struct iio_event_spec sca3000_event = {
  428. .type = IIO_EV_TYPE_MAG,
  429. .dir = IIO_EV_DIR_RISING,
  430. .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
  431. };
  432. /*
  433. * Note the hack in the number of bits to pretend we have 2 more than
  434. * we do in the fifo.
  435. */
  436. #define SCA3000_CHAN(index, mod) \
  437. { \
  438. .type = IIO_ACCEL, \
  439. .modified = 1, \
  440. .channel2 = mod, \
  441. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  442. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
  443. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
  444. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
  445. .address = index, \
  446. .scan_index = index, \
  447. .scan_type = { \
  448. .sign = 's', \
  449. .realbits = 13, \
  450. .storagebits = 16, \
  451. .shift = 3, \
  452. .endianness = IIO_BE, \
  453. }, \
  454. .event_spec = &sca3000_event, \
  455. .num_event_specs = 1, \
  456. }
  457. static const struct iio_event_spec sca3000_freefall_event_spec = {
  458. .type = IIO_EV_TYPE_MAG,
  459. .dir = IIO_EV_DIR_FALLING,
  460. .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
  461. BIT(IIO_EV_INFO_PERIOD),
  462. };
  463. static const struct iio_chan_spec sca3000_channels[] = {
  464. SCA3000_CHAN(0, IIO_MOD_X),
  465. SCA3000_CHAN(1, IIO_MOD_Y),
  466. SCA3000_CHAN(2, IIO_MOD_Z),
  467. {
  468. .type = IIO_ACCEL,
  469. .modified = 1,
  470. .channel2 = IIO_MOD_X_AND_Y_AND_Z,
  471. .scan_index = -1, /* Fake channel */
  472. .event_spec = &sca3000_freefall_event_spec,
  473. .num_event_specs = 1,
  474. },
  475. };
  476. static const struct iio_chan_spec sca3000_channels_with_temp[] = {
  477. SCA3000_CHAN(0, IIO_MOD_X),
  478. SCA3000_CHAN(1, IIO_MOD_Y),
  479. SCA3000_CHAN(2, IIO_MOD_Z),
  480. {
  481. .type = IIO_TEMP,
  482. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
  483. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
  484. BIT(IIO_CHAN_INFO_OFFSET),
  485. /* No buffer support */
  486. .scan_index = -1,
  487. },
  488. {
  489. .type = IIO_ACCEL,
  490. .modified = 1,
  491. .channel2 = IIO_MOD_X_AND_Y_AND_Z,
  492. .scan_index = -1, /* Fake channel */
  493. .event_spec = &sca3000_freefall_event_spec,
  494. .num_event_specs = 1,
  495. },
  496. };
  497. static u8 sca3000_addresses[3][3] = {
  498. [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
  499. SCA3000_MD_CTRL_OR_X},
  500. [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
  501. SCA3000_MD_CTRL_OR_Y},
  502. [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
  503. SCA3000_MD_CTRL_OR_Z},
  504. };
  505. /**
  506. * __sca3000_get_base_freq() - obtain mode specific base frequency
  507. * @st: Private driver specific device instance specific state.
  508. * @info: chip type specific information.
  509. * @base_freq: Base frequency for the current measurement mode.
  510. *
  511. * lock must be held
  512. */
  513. static inline int __sca3000_get_base_freq(struct sca3000_state *st,
  514. const struct sca3000_chip_info *info,
  515. int *base_freq)
  516. {
  517. int ret;
  518. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  519. if (ret)
  520. goto error_ret;
  521. switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
  522. case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
  523. *base_freq = info->measurement_mode_freq;
  524. break;
  525. case SCA3000_REG_MODE_MEAS_MODE_OP_1:
  526. *base_freq = info->option_mode_1_freq;
  527. break;
  528. case SCA3000_REG_MODE_MEAS_MODE_OP_2:
  529. *base_freq = info->option_mode_2_freq;
  530. break;
  531. default:
  532. ret = -EINVAL;
  533. }
  534. error_ret:
  535. return ret;
  536. }
  537. /**
  538. * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
  539. * @st: Private driver specific device instance specific state.
  540. * @val: The frequency read back.
  541. *
  542. * lock must be held
  543. **/
  544. static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
  545. {
  546. int ret;
  547. ret = __sca3000_get_base_freq(st, st->info, val);
  548. if (ret)
  549. return ret;
  550. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
  551. if (ret < 0)
  552. return ret;
  553. if (*val > 0) {
  554. ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
  555. switch (ret) {
  556. case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
  557. *val /= 2;
  558. break;
  559. case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
  560. *val /= 4;
  561. break;
  562. }
  563. }
  564. return 0;
  565. }
  566. /**
  567. * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
  568. * @st: Private driver specific device instance specific state.
  569. * @val: The frequency desired.
  570. *
  571. * lock must be held
  572. */
  573. static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
  574. {
  575. int ret, base_freq, ctrlval;
  576. ret = __sca3000_get_base_freq(st, st->info, &base_freq);
  577. if (ret)
  578. return ret;
  579. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
  580. if (ret < 0)
  581. return ret;
  582. ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
  583. if (val == base_freq / 2)
  584. ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
  585. if (val == base_freq / 4)
  586. ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
  587. else if (val != base_freq)
  588. return -EINVAL;
  589. return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
  590. ctrlval);
  591. }
  592. static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
  593. {
  594. int ret;
  595. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  596. if (ret)
  597. return ret;
  598. /* mask bottom 2 bits - only ones that are relevant */
  599. st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
  600. switch (st->rx[0]) {
  601. case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
  602. *val = st->info->measurement_mode_3db_freq;
  603. return IIO_VAL_INT;
  604. case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
  605. return -EBUSY;
  606. case SCA3000_REG_MODE_MEAS_MODE_OP_1:
  607. *val = st->info->option_mode_1_3db_freq;
  608. return IIO_VAL_INT;
  609. case SCA3000_REG_MODE_MEAS_MODE_OP_2:
  610. *val = st->info->option_mode_2_3db_freq;
  611. return IIO_VAL_INT;
  612. default:
  613. return -EINVAL;
  614. }
  615. }
  616. static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
  617. {
  618. int ret;
  619. int mode;
  620. if (val == st->info->measurement_mode_3db_freq)
  621. mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
  622. else if (st->info->option_mode_1 &&
  623. (val == st->info->option_mode_1_3db_freq))
  624. mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
  625. else if (st->info->option_mode_2 &&
  626. (val == st->info->option_mode_2_3db_freq))
  627. mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
  628. else
  629. return -EINVAL;
  630. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  631. if (ret)
  632. return ret;
  633. st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
  634. st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
  635. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
  636. }
  637. static int sca3000_read_raw(struct iio_dev *indio_dev,
  638. struct iio_chan_spec const *chan,
  639. int *val,
  640. int *val2,
  641. long mask)
  642. {
  643. struct sca3000_state *st = iio_priv(indio_dev);
  644. int ret;
  645. u8 address;
  646. switch (mask) {
  647. case IIO_CHAN_INFO_RAW:
  648. mutex_lock(&st->lock);
  649. if (chan->type == IIO_ACCEL) {
  650. if (st->mo_det_use_count) {
  651. mutex_unlock(&st->lock);
  652. return -EBUSY;
  653. }
  654. address = sca3000_addresses[chan->address][0];
  655. ret = sca3000_read_data_short(st, address, 2);
  656. if (ret < 0) {
  657. mutex_unlock(&st->lock);
  658. return ret;
  659. }
  660. *val = (be16_to_cpup((__be16 *)st->rx) >> 3) & 0x1FFF;
  661. *val = ((*val) << (sizeof(*val) * 8 - 13)) >>
  662. (sizeof(*val) * 8 - 13);
  663. } else {
  664. /* get the temperature when available */
  665. ret = sca3000_read_data_short(st,
  666. SCA3000_REG_TEMP_MSB_ADDR,
  667. 2);
  668. if (ret < 0) {
  669. mutex_unlock(&st->lock);
  670. return ret;
  671. }
  672. *val = ((st->rx[0] & 0x3F) << 3) |
  673. ((st->rx[1] & 0xE0) >> 5);
  674. }
  675. mutex_unlock(&st->lock);
  676. return IIO_VAL_INT;
  677. case IIO_CHAN_INFO_SCALE:
  678. *val = 0;
  679. if (chan->type == IIO_ACCEL)
  680. *val2 = st->info->scale;
  681. else /* temperature */
  682. *val2 = 555556;
  683. return IIO_VAL_INT_PLUS_MICRO;
  684. case IIO_CHAN_INFO_OFFSET:
  685. *val = -214;
  686. *val2 = 600000;
  687. return IIO_VAL_INT_PLUS_MICRO;
  688. case IIO_CHAN_INFO_SAMP_FREQ:
  689. mutex_lock(&st->lock);
  690. ret = sca3000_read_raw_samp_freq(st, val);
  691. mutex_unlock(&st->lock);
  692. return ret ? ret : IIO_VAL_INT;
  693. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  694. mutex_lock(&st->lock);
  695. ret = sca3000_read_3db_freq(st, val);
  696. mutex_unlock(&st->lock);
  697. return ret;
  698. default:
  699. return -EINVAL;
  700. }
  701. }
  702. static int sca3000_write_raw(struct iio_dev *indio_dev,
  703. struct iio_chan_spec const *chan,
  704. int val, int val2, long mask)
  705. {
  706. struct sca3000_state *st = iio_priv(indio_dev);
  707. int ret;
  708. switch (mask) {
  709. case IIO_CHAN_INFO_SAMP_FREQ:
  710. if (val2)
  711. return -EINVAL;
  712. mutex_lock(&st->lock);
  713. ret = sca3000_write_raw_samp_freq(st, val);
  714. mutex_unlock(&st->lock);
  715. return ret;
  716. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  717. if (val2)
  718. return -EINVAL;
  719. mutex_lock(&st->lock);
  720. ret = sca3000_write_3db_freq(st, val);
  721. mutex_unlock(&st->lock);
  722. return ret;
  723. default:
  724. return -EINVAL;
  725. }
  726. return ret;
  727. }
  728. /**
  729. * sca3000_read_av_freq() - sysfs function to get available frequencies
  730. * @dev: Device structure for this device.
  731. * @attr: Description of the attribute.
  732. * @buf: Incoming string
  733. *
  734. * The later modes are only relevant to the ring buffer - and depend on current
  735. * mode. Note that data sheet gives rather wide tolerances for these so integer
  736. * division will give good enough answer and not all chips have them specified
  737. * at all.
  738. **/
  739. static ssize_t sca3000_read_av_freq(struct device *dev,
  740. struct device_attribute *attr,
  741. char *buf)
  742. {
  743. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  744. struct sca3000_state *st = iio_priv(indio_dev);
  745. int len = 0, ret, val;
  746. mutex_lock(&st->lock);
  747. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  748. val = st->rx[0];
  749. mutex_unlock(&st->lock);
  750. if (ret)
  751. goto error_ret;
  752. switch (val & SCA3000_REG_MODE_MODE_MASK) {
  753. case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
  754. len += sprintf(buf + len, "%d %d %d\n",
  755. st->info->measurement_mode_freq,
  756. st->info->measurement_mode_freq / 2,
  757. st->info->measurement_mode_freq / 4);
  758. break;
  759. case SCA3000_REG_MODE_MEAS_MODE_OP_1:
  760. len += sprintf(buf + len, "%d %d %d\n",
  761. st->info->option_mode_1_freq,
  762. st->info->option_mode_1_freq / 2,
  763. st->info->option_mode_1_freq / 4);
  764. break;
  765. case SCA3000_REG_MODE_MEAS_MODE_OP_2:
  766. len += sprintf(buf + len, "%d %d %d\n",
  767. st->info->option_mode_2_freq,
  768. st->info->option_mode_2_freq / 2,
  769. st->info->option_mode_2_freq / 4);
  770. break;
  771. }
  772. return len;
  773. error_ret:
  774. return ret;
  775. }
  776. /*
  777. * Should only really be registered if ring buffer support is compiled in.
  778. * Does no harm however and doing it right would add a fair bit of complexity
  779. */
  780. static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
  781. /**
  782. * sca3000_read_event_value() - query of a threshold or period
  783. **/
  784. static int sca3000_read_event_value(struct iio_dev *indio_dev,
  785. const struct iio_chan_spec *chan,
  786. enum iio_event_type type,
  787. enum iio_event_direction dir,
  788. enum iio_event_info info,
  789. int *val, int *val2)
  790. {
  791. int ret, i;
  792. struct sca3000_state *st = iio_priv(indio_dev);
  793. switch (info) {
  794. case IIO_EV_INFO_VALUE:
  795. mutex_lock(&st->lock);
  796. ret = sca3000_read_ctrl_reg(st,
  797. sca3000_addresses[chan->address][1]);
  798. mutex_unlock(&st->lock);
  799. if (ret < 0)
  800. return ret;
  801. *val = 0;
  802. if (chan->channel2 == IIO_MOD_Y)
  803. for_each_set_bit(i, (unsigned long *)&ret,
  804. ARRAY_SIZE(st->info->mot_det_mult_y))
  805. *val += st->info->mot_det_mult_y[i];
  806. else
  807. for_each_set_bit(i, (unsigned long *)&ret,
  808. ARRAY_SIZE(st->info->mot_det_mult_xz))
  809. *val += st->info->mot_det_mult_xz[i];
  810. return IIO_VAL_INT;
  811. case IIO_EV_INFO_PERIOD:
  812. *val = 0;
  813. *val2 = 226000;
  814. return IIO_VAL_INT_PLUS_MICRO;
  815. default:
  816. return -EINVAL;
  817. }
  818. }
  819. /**
  820. * sca3000_write_value() - control of threshold and period
  821. * @indio_dev: Device instance specific IIO information.
  822. * @chan: Description of the channel for which the event is being
  823. * configured.
  824. * @type: The type of event being configured, here magnitude rising
  825. * as everything else is read only.
  826. * @dir: Direction of the event (here rising)
  827. * @info: What information about the event are we configuring.
  828. * Here the threshold only.
  829. * @val: Integer part of the value being written..
  830. * @val2: Non integer part of the value being written. Here always 0.
  831. */
  832. static int sca3000_write_event_value(struct iio_dev *indio_dev,
  833. const struct iio_chan_spec *chan,
  834. enum iio_event_type type,
  835. enum iio_event_direction dir,
  836. enum iio_event_info info,
  837. int val, int val2)
  838. {
  839. struct sca3000_state *st = iio_priv(indio_dev);
  840. int ret;
  841. int i;
  842. u8 nonlinear = 0;
  843. if (chan->channel2 == IIO_MOD_Y) {
  844. i = ARRAY_SIZE(st->info->mot_det_mult_y);
  845. while (i > 0)
  846. if (val >= st->info->mot_det_mult_y[--i]) {
  847. nonlinear |= (1 << i);
  848. val -= st->info->mot_det_mult_y[i];
  849. }
  850. } else {
  851. i = ARRAY_SIZE(st->info->mot_det_mult_xz);
  852. while (i > 0)
  853. if (val >= st->info->mot_det_mult_xz[--i]) {
  854. nonlinear |= (1 << i);
  855. val -= st->info->mot_det_mult_xz[i];
  856. }
  857. }
  858. mutex_lock(&st->lock);
  859. ret = sca3000_write_ctrl_reg(st,
  860. sca3000_addresses[chan->address][1],
  861. nonlinear);
  862. mutex_unlock(&st->lock);
  863. return ret;
  864. }
  865. static struct attribute *sca3000_attributes[] = {
  866. &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
  867. &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
  868. NULL,
  869. };
  870. static const struct attribute_group sca3000_attribute_group = {
  871. .attrs = sca3000_attributes,
  872. };
  873. static int sca3000_read_data(struct sca3000_state *st,
  874. u8 reg_address_high,
  875. u8 *rx,
  876. int len)
  877. {
  878. int ret;
  879. struct spi_transfer xfer[2] = {
  880. {
  881. .len = 1,
  882. .tx_buf = st->tx,
  883. }, {
  884. .len = len,
  885. .rx_buf = rx,
  886. }
  887. };
  888. st->tx[0] = SCA3000_READ_REG(reg_address_high);
  889. ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
  890. if (ret) {
  891. dev_err(&st->us->dev, "problem reading register\n");
  892. return ret;
  893. }
  894. return 0;
  895. }
  896. /**
  897. * sca3000_ring_int_process() - ring specific interrupt handling.
  898. * @val: Value of the interrupt status register.
  899. * @indio_dev: Device instance specific IIO device structure.
  900. */
  901. static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
  902. {
  903. struct sca3000_state *st = iio_priv(indio_dev);
  904. int ret, i, num_available;
  905. mutex_lock(&st->lock);
  906. if (val & SCA3000_REG_INT_STATUS_HALF) {
  907. ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
  908. 1);
  909. if (ret)
  910. goto error_ret;
  911. num_available = st->rx[0];
  912. /*
  913. * num_available is the total number of samples available
  914. * i.e. number of time points * number of channels.
  915. */
  916. ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
  917. num_available * 2);
  918. if (ret)
  919. goto error_ret;
  920. for (i = 0; i < num_available / 3; i++) {
  921. /*
  922. * Dirty hack to cover for 11 bit in fifo, 13 bit
  923. * direct reading.
  924. *
  925. * In theory the bottom two bits are undefined.
  926. * In reality they appear to always be 0.
  927. */
  928. iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
  929. }
  930. }
  931. error_ret:
  932. mutex_unlock(&st->lock);
  933. }
  934. /**
  935. * sca3000_event_handler() - handling ring and non ring events
  936. * @irq: The irq being handled.
  937. * @private: struct iio_device pointer for the device.
  938. *
  939. * Ring related interrupt handler. Depending on event, push to
  940. * the ring buffer event chrdev or the event one.
  941. *
  942. * This function is complicated by the fact that the devices can signify ring
  943. * and non ring events via the same interrupt line and they can only
  944. * be distinguished via a read of the relevant status register.
  945. */
  946. static irqreturn_t sca3000_event_handler(int irq, void *private)
  947. {
  948. struct iio_dev *indio_dev = private;
  949. struct sca3000_state *st = iio_priv(indio_dev);
  950. int ret, val;
  951. s64 last_timestamp = iio_get_time_ns(indio_dev);
  952. /*
  953. * Could lead if badly timed to an extra read of status reg,
  954. * but ensures no interrupt is missed.
  955. */
  956. mutex_lock(&st->lock);
  957. ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
  958. val = st->rx[0];
  959. mutex_unlock(&st->lock);
  960. if (ret)
  961. goto done;
  962. sca3000_ring_int_process(val, indio_dev);
  963. if (val & SCA3000_INT_STATUS_FREE_FALL)
  964. iio_push_event(indio_dev,
  965. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  966. 0,
  967. IIO_MOD_X_AND_Y_AND_Z,
  968. IIO_EV_TYPE_MAG,
  969. IIO_EV_DIR_FALLING),
  970. last_timestamp);
  971. if (val & SCA3000_INT_STATUS_Y_TRIGGER)
  972. iio_push_event(indio_dev,
  973. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  974. 0,
  975. IIO_MOD_Y,
  976. IIO_EV_TYPE_MAG,
  977. IIO_EV_DIR_RISING),
  978. last_timestamp);
  979. if (val & SCA3000_INT_STATUS_X_TRIGGER)
  980. iio_push_event(indio_dev,
  981. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  982. 0,
  983. IIO_MOD_X,
  984. IIO_EV_TYPE_MAG,
  985. IIO_EV_DIR_RISING),
  986. last_timestamp);
  987. if (val & SCA3000_INT_STATUS_Z_TRIGGER)
  988. iio_push_event(indio_dev,
  989. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  990. 0,
  991. IIO_MOD_Z,
  992. IIO_EV_TYPE_MAG,
  993. IIO_EV_DIR_RISING),
  994. last_timestamp);
  995. done:
  996. return IRQ_HANDLED;
  997. }
  998. /**
  999. * sca3000_read_event_config() what events are enabled
  1000. **/
  1001. static int sca3000_read_event_config(struct iio_dev *indio_dev,
  1002. const struct iio_chan_spec *chan,
  1003. enum iio_event_type type,
  1004. enum iio_event_direction dir)
  1005. {
  1006. struct sca3000_state *st = iio_priv(indio_dev);
  1007. int ret;
  1008. /* read current value of mode register */
  1009. mutex_lock(&st->lock);
  1010. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1011. if (ret)
  1012. goto error_ret;
  1013. switch (chan->channel2) {
  1014. case IIO_MOD_X_AND_Y_AND_Z:
  1015. ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
  1016. break;
  1017. case IIO_MOD_X:
  1018. case IIO_MOD_Y:
  1019. case IIO_MOD_Z:
  1020. /*
  1021. * Motion detection mode cannot run at the same time as
  1022. * acceleration data being read.
  1023. */
  1024. if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
  1025. != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
  1026. ret = 0;
  1027. } else {
  1028. ret = sca3000_read_ctrl_reg(st,
  1029. SCA3000_REG_CTRL_SEL_MD_CTRL);
  1030. if (ret < 0)
  1031. goto error_ret;
  1032. /* only supporting logical or's for now */
  1033. ret = !!(ret & sca3000_addresses[chan->address][2]);
  1034. }
  1035. break;
  1036. default:
  1037. ret = -EINVAL;
  1038. }
  1039. error_ret:
  1040. mutex_unlock(&st->lock);
  1041. return ret;
  1042. }
  1043. static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
  1044. {
  1045. struct sca3000_state *st = iio_priv(indio_dev);
  1046. int ret;
  1047. /* read current value of mode register */
  1048. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1049. if (ret)
  1050. return ret;
  1051. /* if off and should be on */
  1052. if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
  1053. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1054. st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
  1055. /* if on and should be off */
  1056. else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
  1057. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1058. st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
  1059. else
  1060. return 0;
  1061. }
  1062. static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
  1063. int state)
  1064. {
  1065. struct sca3000_state *st = iio_priv(indio_dev);
  1066. int ret, ctrlval;
  1067. /*
  1068. * First read the motion detector config to find out if
  1069. * this axis is on
  1070. */
  1071. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
  1072. if (ret < 0)
  1073. return ret;
  1074. ctrlval = ret;
  1075. /* if off and should be on */
  1076. if (state && !(ctrlval & sca3000_addresses[axis][2])) {
  1077. ret = sca3000_write_ctrl_reg(st,
  1078. SCA3000_REG_CTRL_SEL_MD_CTRL,
  1079. ctrlval |
  1080. sca3000_addresses[axis][2]);
  1081. if (ret)
  1082. return ret;
  1083. st->mo_det_use_count++;
  1084. } else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
  1085. ret = sca3000_write_ctrl_reg(st,
  1086. SCA3000_REG_CTRL_SEL_MD_CTRL,
  1087. ctrlval &
  1088. ~(sca3000_addresses[axis][2]));
  1089. if (ret)
  1090. return ret;
  1091. st->mo_det_use_count--;
  1092. }
  1093. /* read current value of mode register */
  1094. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1095. if (ret)
  1096. return ret;
  1097. /* if off and should be on */
  1098. if ((st->mo_det_use_count) &&
  1099. ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
  1100. != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
  1101. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1102. (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
  1103. | SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
  1104. /* if on and should be off */
  1105. else if (!(st->mo_det_use_count) &&
  1106. ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
  1107. == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
  1108. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1109. st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
  1110. else
  1111. return 0;
  1112. }
  1113. /**
  1114. * sca3000_write_event_config() - simple on off control for motion detector
  1115. * @indio_dev: IIO device instance specific structure. Data specific to this
  1116. * particular driver may be accessed via iio_priv(indio_dev).
  1117. * @chan: Description of the channel whose event we are configuring.
  1118. * @type: The type of event.
  1119. * @dir: The direction of the event.
  1120. * @state: Desired state of event being configured.
  1121. *
  1122. * This is a per axis control, but enabling any will result in the
  1123. * motion detector unit being enabled.
  1124. * N.B. enabling motion detector stops normal data acquisition.
  1125. * There is a complexity in knowing which mode to return to when
  1126. * this mode is disabled. Currently normal mode is assumed.
  1127. **/
  1128. static int sca3000_write_event_config(struct iio_dev *indio_dev,
  1129. const struct iio_chan_spec *chan,
  1130. enum iio_event_type type,
  1131. enum iio_event_direction dir,
  1132. int state)
  1133. {
  1134. struct sca3000_state *st = iio_priv(indio_dev);
  1135. int ret;
  1136. mutex_lock(&st->lock);
  1137. switch (chan->channel2) {
  1138. case IIO_MOD_X_AND_Y_AND_Z:
  1139. ret = sca3000_freefall_set_state(indio_dev, state);
  1140. break;
  1141. case IIO_MOD_X:
  1142. case IIO_MOD_Y:
  1143. case IIO_MOD_Z:
  1144. ret = sca3000_motion_detect_set_state(indio_dev,
  1145. chan->address,
  1146. state);
  1147. break;
  1148. default:
  1149. ret = -EINVAL;
  1150. break;
  1151. }
  1152. mutex_unlock(&st->lock);
  1153. return ret;
  1154. }
  1155. static int sca3000_configure_ring(struct iio_dev *indio_dev)
  1156. {
  1157. struct iio_buffer *buffer;
  1158. buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
  1159. if (!buffer)
  1160. return -ENOMEM;
  1161. iio_device_attach_buffer(indio_dev, buffer);
  1162. indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
  1163. return 0;
  1164. }
  1165. static inline
  1166. int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
  1167. {
  1168. struct sca3000_state *st = iio_priv(indio_dev);
  1169. int ret;
  1170. mutex_lock(&st->lock);
  1171. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1172. if (ret)
  1173. goto error_ret;
  1174. if (state) {
  1175. dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
  1176. ret = sca3000_write_reg(st,
  1177. SCA3000_REG_MODE_ADDR,
  1178. (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
  1179. } else
  1180. ret = sca3000_write_reg(st,
  1181. SCA3000_REG_MODE_ADDR,
  1182. (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
  1183. error_ret:
  1184. mutex_unlock(&st->lock);
  1185. return ret;
  1186. }
  1187. /**
  1188. * sca3000_hw_ring_preenable() - hw ring buffer preenable function
  1189. * @indio_dev: structure representing the IIO device. Device instance
  1190. * specific state can be accessed via iio_priv(indio_dev).
  1191. *
  1192. * Very simple enable function as the chip will allows normal reads
  1193. * during ring buffer operation so as long as it is indeed running
  1194. * before we notify the core, the precise ordering does not matter.
  1195. */
  1196. static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
  1197. {
  1198. int ret;
  1199. struct sca3000_state *st = iio_priv(indio_dev);
  1200. mutex_lock(&st->lock);
  1201. /* Enable the 50% full interrupt */
  1202. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1203. if (ret)
  1204. goto error_unlock;
  1205. ret = sca3000_write_reg(st,
  1206. SCA3000_REG_INT_MASK_ADDR,
  1207. st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
  1208. if (ret)
  1209. goto error_unlock;
  1210. mutex_unlock(&st->lock);
  1211. return __sca3000_hw_ring_state_set(indio_dev, 1);
  1212. error_unlock:
  1213. mutex_unlock(&st->lock);
  1214. return ret;
  1215. }
  1216. static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
  1217. {
  1218. int ret;
  1219. struct sca3000_state *st = iio_priv(indio_dev);
  1220. ret = __sca3000_hw_ring_state_set(indio_dev, 0);
  1221. if (ret)
  1222. return ret;
  1223. /* Disable the 50% full interrupt */
  1224. mutex_lock(&st->lock);
  1225. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1226. if (ret)
  1227. goto unlock;
  1228. ret = sca3000_write_reg(st,
  1229. SCA3000_REG_INT_MASK_ADDR,
  1230. st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
  1231. unlock:
  1232. mutex_unlock(&st->lock);
  1233. return ret;
  1234. }
  1235. static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
  1236. .preenable = &sca3000_hw_ring_preenable,
  1237. .postdisable = &sca3000_hw_ring_postdisable,
  1238. };
  1239. /**
  1240. * sca3000_clean_setup() - get the device into a predictable state
  1241. * @st: Device instance specific private data structure
  1242. *
  1243. * Devices use flash memory to store many of the register values
  1244. * and hence can come up in somewhat unpredictable states.
  1245. * Hence reset everything on driver load.
  1246. */
  1247. static int sca3000_clean_setup(struct sca3000_state *st)
  1248. {
  1249. int ret;
  1250. mutex_lock(&st->lock);
  1251. /* Ensure all interrupts have been acknowledged */
  1252. ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
  1253. if (ret)
  1254. goto error_ret;
  1255. /* Turn off all motion detection channels */
  1256. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
  1257. if (ret < 0)
  1258. goto error_ret;
  1259. ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
  1260. ret & SCA3000_MD_CTRL_PROT_MASK);
  1261. if (ret)
  1262. goto error_ret;
  1263. /* Disable ring buffer */
  1264. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
  1265. if (ret < 0)
  1266. goto error_ret;
  1267. ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
  1268. (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
  1269. | SCA3000_REG_OUT_CTRL_BUF_X_EN
  1270. | SCA3000_REG_OUT_CTRL_BUF_Y_EN
  1271. | SCA3000_REG_OUT_CTRL_BUF_Z_EN
  1272. | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
  1273. if (ret)
  1274. goto error_ret;
  1275. /* Enable interrupts, relevant to mode and set up as active low */
  1276. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1277. if (ret)
  1278. goto error_ret;
  1279. ret = sca3000_write_reg(st,
  1280. SCA3000_REG_INT_MASK_ADDR,
  1281. (ret & SCA3000_REG_INT_MASK_PROT_MASK)
  1282. | SCA3000_REG_INT_MASK_ACTIVE_LOW);
  1283. if (ret)
  1284. goto error_ret;
  1285. /*
  1286. * Select normal measurement mode, free fall off, ring off
  1287. * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
  1288. * as that occurs in one of the example on the datasheet
  1289. */
  1290. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1291. if (ret)
  1292. goto error_ret;
  1293. ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1294. (st->rx[0] & SCA3000_MODE_PROT_MASK));
  1295. error_ret:
  1296. mutex_unlock(&st->lock);
  1297. return ret;
  1298. }
  1299. static const struct iio_info sca3000_info = {
  1300. .attrs = &sca3000_attribute_group,
  1301. .read_raw = &sca3000_read_raw,
  1302. .write_raw = &sca3000_write_raw,
  1303. .read_event_value = &sca3000_read_event_value,
  1304. .write_event_value = &sca3000_write_event_value,
  1305. .read_event_config = &sca3000_read_event_config,
  1306. .write_event_config = &sca3000_write_event_config,
  1307. .driver_module = THIS_MODULE,
  1308. };
  1309. static int sca3000_probe(struct spi_device *spi)
  1310. {
  1311. int ret;
  1312. struct sca3000_state *st;
  1313. struct iio_dev *indio_dev;
  1314. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  1315. if (!indio_dev)
  1316. return -ENOMEM;
  1317. st = iio_priv(indio_dev);
  1318. spi_set_drvdata(spi, indio_dev);
  1319. st->us = spi;
  1320. mutex_init(&st->lock);
  1321. st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
  1322. ->driver_data];
  1323. indio_dev->dev.parent = &spi->dev;
  1324. indio_dev->name = spi_get_device_id(spi)->name;
  1325. indio_dev->info = &sca3000_info;
  1326. if (st->info->temp_output) {
  1327. indio_dev->channels = sca3000_channels_with_temp;
  1328. indio_dev->num_channels =
  1329. ARRAY_SIZE(sca3000_channels_with_temp);
  1330. } else {
  1331. indio_dev->channels = sca3000_channels;
  1332. indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
  1333. }
  1334. indio_dev->modes = INDIO_DIRECT_MODE;
  1335. sca3000_configure_ring(indio_dev);
  1336. if (spi->irq) {
  1337. ret = request_threaded_irq(spi->irq,
  1338. NULL,
  1339. &sca3000_event_handler,
  1340. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1341. "sca3000",
  1342. indio_dev);
  1343. if (ret)
  1344. return ret;
  1345. }
  1346. indio_dev->setup_ops = &sca3000_ring_setup_ops;
  1347. ret = sca3000_clean_setup(st);
  1348. if (ret)
  1349. goto error_free_irq;
  1350. ret = sca3000_print_rev(indio_dev);
  1351. if (ret)
  1352. goto error_free_irq;
  1353. return iio_device_register(indio_dev);
  1354. error_free_irq:
  1355. if (spi->irq)
  1356. free_irq(spi->irq, indio_dev);
  1357. return ret;
  1358. }
  1359. static int sca3000_stop_all_interrupts(struct sca3000_state *st)
  1360. {
  1361. int ret;
  1362. mutex_lock(&st->lock);
  1363. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1364. if (ret)
  1365. goto error_ret;
  1366. ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
  1367. (st->rx[0] &
  1368. ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
  1369. SCA3000_REG_INT_MASK_RING_HALF |
  1370. SCA3000_REG_INT_MASK_ALL_INTS)));
  1371. error_ret:
  1372. mutex_unlock(&st->lock);
  1373. return ret;
  1374. }
  1375. static int sca3000_remove(struct spi_device *spi)
  1376. {
  1377. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  1378. struct sca3000_state *st = iio_priv(indio_dev);
  1379. iio_device_unregister(indio_dev);
  1380. /* Must ensure no interrupts can be generated after this! */
  1381. sca3000_stop_all_interrupts(st);
  1382. if (spi->irq)
  1383. free_irq(spi->irq, indio_dev);
  1384. return 0;
  1385. }
  1386. static const struct spi_device_id sca3000_id[] = {
  1387. {"sca3000_d01", d01},
  1388. {"sca3000_e02", e02},
  1389. {"sca3000_e04", e04},
  1390. {"sca3000_e05", e05},
  1391. {}
  1392. };
  1393. MODULE_DEVICE_TABLE(spi, sca3000_id);
  1394. static struct spi_driver sca3000_driver = {
  1395. .driver = {
  1396. .name = "sca3000",
  1397. },
  1398. .probe = sca3000_probe,
  1399. .remove = sca3000_remove,
  1400. .id_table = sca3000_id,
  1401. };
  1402. module_spi_driver(sca3000_driver);
  1403. MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
  1404. MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
  1405. MODULE_LICENSE("GPL v2");