i810_dma.c 32 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include <drm/drmP.h>
  33. #include <drm/i810_drm.h>
  34. #include "i810_drv.h"
  35. #include <linux/interrupt.h> /* For task queue support */
  36. #include <linux/delay.h>
  37. #include <linux/slab.h>
  38. #include <linux/pagemap.h>
  39. #define I810_BUF_FREE 2
  40. #define I810_BUF_CLIENT 1
  41. #define I810_BUF_HARDWARE 0
  42. #define I810_BUF_UNMAPPED 0
  43. #define I810_BUF_MAPPED 1
  44. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  45. {
  46. struct drm_device_dma *dma = dev->dma;
  47. int i;
  48. int used;
  49. /* Linear search might not be the best solution */
  50. for (i = 0; i < dma->buf_count; i++) {
  51. struct drm_buf *buf = dma->buflist[i];
  52. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  53. /* In use is already a pointer */
  54. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  55. I810_BUF_CLIENT);
  56. if (used == I810_BUF_FREE)
  57. return buf;
  58. }
  59. return NULL;
  60. }
  61. /* This should only be called if the buffer is not sent to the hardware
  62. * yet, the hardware updates in use for us once its on the ring buffer.
  63. */
  64. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  65. {
  66. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  67. int used;
  68. /* In use is already a pointer */
  69. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  70. if (used != I810_BUF_CLIENT) {
  71. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  72. return -EINVAL;
  73. }
  74. return 0;
  75. }
  76. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  77. {
  78. struct drm_file *priv = filp->private_data;
  79. struct drm_device *dev;
  80. drm_i810_private_t *dev_priv;
  81. struct drm_buf *buf;
  82. drm_i810_buf_priv_t *buf_priv;
  83. dev = priv->minor->dev;
  84. dev_priv = dev->dev_private;
  85. buf = dev_priv->mmap_buffer;
  86. buf_priv = buf->dev_private;
  87. vma->vm_flags |= VM_DONTCOPY;
  88. buf_priv->currently_mapped = I810_BUF_MAPPED;
  89. if (io_remap_pfn_range(vma, vma->vm_start,
  90. vma->vm_pgoff,
  91. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  92. return -EAGAIN;
  93. return 0;
  94. }
  95. static const struct file_operations i810_buffer_fops = {
  96. .open = drm_open,
  97. .release = drm_release,
  98. .unlocked_ioctl = drm_ioctl,
  99. .mmap = i810_mmap_buffers,
  100. .compat_ioctl = drm_compat_ioctl,
  101. .llseek = noop_llseek,
  102. };
  103. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  104. {
  105. struct drm_device *dev = file_priv->minor->dev;
  106. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  107. drm_i810_private_t *dev_priv = dev->dev_private;
  108. const struct file_operations *old_fops;
  109. int retcode = 0;
  110. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  111. return -EINVAL;
  112. /* This is all entirely broken */
  113. old_fops = file_priv->filp->f_op;
  114. file_priv->filp->f_op = &i810_buffer_fops;
  115. dev_priv->mmap_buffer = buf;
  116. buf_priv->virtual = (void *)vm_mmap(file_priv->filp, 0, buf->total,
  117. PROT_READ | PROT_WRITE,
  118. MAP_SHARED, buf->bus_address);
  119. dev_priv->mmap_buffer = NULL;
  120. file_priv->filp->f_op = old_fops;
  121. if (IS_ERR(buf_priv->virtual)) {
  122. /* Real error */
  123. DRM_ERROR("mmap error\n");
  124. retcode = PTR_ERR(buf_priv->virtual);
  125. buf_priv->virtual = NULL;
  126. }
  127. return retcode;
  128. }
  129. static int i810_unmap_buffer(struct drm_buf *buf)
  130. {
  131. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  132. int retcode = 0;
  133. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  134. return -EINVAL;
  135. retcode = vm_munmap((unsigned long)buf_priv->virtual,
  136. (size_t) buf->total);
  137. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  138. buf_priv->virtual = NULL;
  139. return retcode;
  140. }
  141. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  142. struct drm_file *file_priv)
  143. {
  144. struct drm_buf *buf;
  145. drm_i810_buf_priv_t *buf_priv;
  146. int retcode = 0;
  147. buf = i810_freelist_get(dev);
  148. if (!buf) {
  149. retcode = -ENOMEM;
  150. DRM_DEBUG("retcode=%d\n", retcode);
  151. return retcode;
  152. }
  153. retcode = i810_map_buffer(buf, file_priv);
  154. if (retcode) {
  155. i810_freelist_put(dev, buf);
  156. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  157. return retcode;
  158. }
  159. buf->file_priv = file_priv;
  160. buf_priv = buf->dev_private;
  161. d->granted = 1;
  162. d->request_idx = buf->idx;
  163. d->request_size = buf->total;
  164. d->virtual = buf_priv->virtual;
  165. return retcode;
  166. }
  167. static int i810_dma_cleanup(struct drm_device *dev)
  168. {
  169. struct drm_device_dma *dma = dev->dma;
  170. /* Make sure interrupts are disabled here because the uninstall ioctl
  171. * may not have been called from userspace and after dev_private
  172. * is freed, it's too late.
  173. */
  174. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  175. drm_irq_uninstall(dev);
  176. if (dev->dev_private) {
  177. int i;
  178. drm_i810_private_t *dev_priv =
  179. (drm_i810_private_t *) dev->dev_private;
  180. if (dev_priv->ring.virtual_start)
  181. drm_legacy_ioremapfree(&dev_priv->ring.map, dev);
  182. if (dev_priv->hw_status_page) {
  183. pci_free_consistent(dev->pdev, PAGE_SIZE,
  184. dev_priv->hw_status_page,
  185. dev_priv->dma_status_page);
  186. }
  187. kfree(dev->dev_private);
  188. dev->dev_private = NULL;
  189. for (i = 0; i < dma->buf_count; i++) {
  190. struct drm_buf *buf = dma->buflist[i];
  191. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  192. if (buf_priv->kernel_virtual && buf->total)
  193. drm_legacy_ioremapfree(&buf_priv->map, dev);
  194. }
  195. }
  196. return 0;
  197. }
  198. static int i810_wait_ring(struct drm_device *dev, int n)
  199. {
  200. drm_i810_private_t *dev_priv = dev->dev_private;
  201. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  202. int iters = 0;
  203. unsigned long end;
  204. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  205. end = jiffies + (HZ * 3);
  206. while (ring->space < n) {
  207. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  208. ring->space = ring->head - (ring->tail + 8);
  209. if (ring->space < 0)
  210. ring->space += ring->Size;
  211. if (ring->head != last_head) {
  212. end = jiffies + (HZ * 3);
  213. last_head = ring->head;
  214. }
  215. iters++;
  216. if (time_before(end, jiffies)) {
  217. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  218. DRM_ERROR("lockup\n");
  219. goto out_wait_ring;
  220. }
  221. udelay(1);
  222. }
  223. out_wait_ring:
  224. return iters;
  225. }
  226. static void i810_kernel_lost_context(struct drm_device *dev)
  227. {
  228. drm_i810_private_t *dev_priv = dev->dev_private;
  229. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  230. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  231. ring->tail = I810_READ(LP_RING + RING_TAIL);
  232. ring->space = ring->head - (ring->tail + 8);
  233. if (ring->space < 0)
  234. ring->space += ring->Size;
  235. }
  236. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  237. {
  238. struct drm_device_dma *dma = dev->dma;
  239. int my_idx = 24;
  240. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  241. int i;
  242. if (dma->buf_count > 1019) {
  243. /* Not enough space in the status page for the freelist */
  244. return -EINVAL;
  245. }
  246. for (i = 0; i < dma->buf_count; i++) {
  247. struct drm_buf *buf = dma->buflist[i];
  248. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  249. buf_priv->in_use = hw_status++;
  250. buf_priv->my_use_idx = my_idx;
  251. my_idx += 4;
  252. *buf_priv->in_use = I810_BUF_FREE;
  253. buf_priv->map.offset = buf->bus_address;
  254. buf_priv->map.size = buf->total;
  255. buf_priv->map.type = _DRM_AGP;
  256. buf_priv->map.flags = 0;
  257. buf_priv->map.mtrr = 0;
  258. drm_legacy_ioremap(&buf_priv->map, dev);
  259. buf_priv->kernel_virtual = buf_priv->map.handle;
  260. }
  261. return 0;
  262. }
  263. static int i810_dma_initialize(struct drm_device *dev,
  264. drm_i810_private_t *dev_priv,
  265. drm_i810_init_t *init)
  266. {
  267. struct drm_map_list *r_list;
  268. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  269. list_for_each_entry(r_list, &dev->maplist, head) {
  270. if (r_list->map &&
  271. r_list->map->type == _DRM_SHM &&
  272. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  273. dev_priv->sarea_map = r_list->map;
  274. break;
  275. }
  276. }
  277. if (!dev_priv->sarea_map) {
  278. dev->dev_private = (void *)dev_priv;
  279. i810_dma_cleanup(dev);
  280. DRM_ERROR("can not find sarea!\n");
  281. return -EINVAL;
  282. }
  283. dev_priv->mmio_map = drm_legacy_findmap(dev, init->mmio_offset);
  284. if (!dev_priv->mmio_map) {
  285. dev->dev_private = (void *)dev_priv;
  286. i810_dma_cleanup(dev);
  287. DRM_ERROR("can not find mmio map!\n");
  288. return -EINVAL;
  289. }
  290. dev->agp_buffer_token = init->buffers_offset;
  291. dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
  292. if (!dev->agp_buffer_map) {
  293. dev->dev_private = (void *)dev_priv;
  294. i810_dma_cleanup(dev);
  295. DRM_ERROR("can not find dma buffer map!\n");
  296. return -EINVAL;
  297. }
  298. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  299. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  300. dev_priv->ring.Start = init->ring_start;
  301. dev_priv->ring.End = init->ring_end;
  302. dev_priv->ring.Size = init->ring_size;
  303. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  304. dev_priv->ring.map.size = init->ring_size;
  305. dev_priv->ring.map.type = _DRM_AGP;
  306. dev_priv->ring.map.flags = 0;
  307. dev_priv->ring.map.mtrr = 0;
  308. drm_legacy_ioremap(&dev_priv->ring.map, dev);
  309. if (dev_priv->ring.map.handle == NULL) {
  310. dev->dev_private = (void *)dev_priv;
  311. i810_dma_cleanup(dev);
  312. DRM_ERROR("can not ioremap virtual address for"
  313. " ring buffer\n");
  314. return -ENOMEM;
  315. }
  316. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  317. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  318. dev_priv->w = init->w;
  319. dev_priv->h = init->h;
  320. dev_priv->pitch = init->pitch;
  321. dev_priv->back_offset = init->back_offset;
  322. dev_priv->depth_offset = init->depth_offset;
  323. dev_priv->front_offset = init->front_offset;
  324. dev_priv->overlay_offset = init->overlay_offset;
  325. dev_priv->overlay_physical = init->overlay_physical;
  326. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  327. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  328. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  329. /* Program Hardware Status Page */
  330. dev_priv->hw_status_page =
  331. pci_zalloc_consistent(dev->pdev, PAGE_SIZE,
  332. &dev_priv->dma_status_page);
  333. if (!dev_priv->hw_status_page) {
  334. dev->dev_private = (void *)dev_priv;
  335. i810_dma_cleanup(dev);
  336. DRM_ERROR("Can not allocate hardware status page\n");
  337. return -ENOMEM;
  338. }
  339. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  340. I810_WRITE(0x02080, dev_priv->dma_status_page);
  341. DRM_DEBUG("Enabled hardware status page\n");
  342. /* Now we need to init our freelist */
  343. if (i810_freelist_init(dev, dev_priv) != 0) {
  344. dev->dev_private = (void *)dev_priv;
  345. i810_dma_cleanup(dev);
  346. DRM_ERROR("Not enough space in the status page for"
  347. " the freelist\n");
  348. return -ENOMEM;
  349. }
  350. dev->dev_private = (void *)dev_priv;
  351. return 0;
  352. }
  353. static int i810_dma_init(struct drm_device *dev, void *data,
  354. struct drm_file *file_priv)
  355. {
  356. drm_i810_private_t *dev_priv;
  357. drm_i810_init_t *init = data;
  358. int retcode = 0;
  359. switch (init->func) {
  360. case I810_INIT_DMA_1_4:
  361. DRM_INFO("Using v1.4 init.\n");
  362. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  363. if (dev_priv == NULL)
  364. return -ENOMEM;
  365. retcode = i810_dma_initialize(dev, dev_priv, init);
  366. break;
  367. case I810_CLEANUP_DMA:
  368. DRM_INFO("DMA Cleanup\n");
  369. retcode = i810_dma_cleanup(dev);
  370. break;
  371. default:
  372. return -EINVAL;
  373. }
  374. return retcode;
  375. }
  376. /* Most efficient way to verify state for the i810 is as it is
  377. * emitted. Non-conformant state is silently dropped.
  378. *
  379. * Use 'volatile' & local var tmp to force the emitted values to be
  380. * identical to the verified ones.
  381. */
  382. static void i810EmitContextVerified(struct drm_device *dev,
  383. volatile unsigned int *code)
  384. {
  385. drm_i810_private_t *dev_priv = dev->dev_private;
  386. int i, j = 0;
  387. unsigned int tmp;
  388. RING_LOCALS;
  389. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  390. OUT_RING(GFX_OP_COLOR_FACTOR);
  391. OUT_RING(code[I810_CTXREG_CF1]);
  392. OUT_RING(GFX_OP_STIPPLE);
  393. OUT_RING(code[I810_CTXREG_ST1]);
  394. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  395. tmp = code[i];
  396. if ((tmp & (7 << 29)) == (3 << 29) &&
  397. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  398. OUT_RING(tmp);
  399. j++;
  400. } else
  401. printk("constext state dropped!!!\n");
  402. }
  403. if (j & 1)
  404. OUT_RING(0);
  405. ADVANCE_LP_RING();
  406. }
  407. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  408. {
  409. drm_i810_private_t *dev_priv = dev->dev_private;
  410. int i, j = 0;
  411. unsigned int tmp;
  412. RING_LOCALS;
  413. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  414. OUT_RING(GFX_OP_MAP_INFO);
  415. OUT_RING(code[I810_TEXREG_MI1]);
  416. OUT_RING(code[I810_TEXREG_MI2]);
  417. OUT_RING(code[I810_TEXREG_MI3]);
  418. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  419. tmp = code[i];
  420. if ((tmp & (7 << 29)) == (3 << 29) &&
  421. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  422. OUT_RING(tmp);
  423. j++;
  424. } else
  425. printk("texture state dropped!!!\n");
  426. }
  427. if (j & 1)
  428. OUT_RING(0);
  429. ADVANCE_LP_RING();
  430. }
  431. /* Need to do some additional checking when setting the dest buffer.
  432. */
  433. static void i810EmitDestVerified(struct drm_device *dev,
  434. volatile unsigned int *code)
  435. {
  436. drm_i810_private_t *dev_priv = dev->dev_private;
  437. unsigned int tmp;
  438. RING_LOCALS;
  439. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  440. tmp = code[I810_DESTREG_DI1];
  441. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  442. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  443. OUT_RING(tmp);
  444. } else
  445. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  446. tmp, dev_priv->front_di1, dev_priv->back_di1);
  447. /* invarient:
  448. */
  449. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  450. OUT_RING(dev_priv->zi1);
  451. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  452. OUT_RING(code[I810_DESTREG_DV1]);
  453. OUT_RING(GFX_OP_DRAWRECT_INFO);
  454. OUT_RING(code[I810_DESTREG_DR1]);
  455. OUT_RING(code[I810_DESTREG_DR2]);
  456. OUT_RING(code[I810_DESTREG_DR3]);
  457. OUT_RING(code[I810_DESTREG_DR4]);
  458. OUT_RING(0);
  459. ADVANCE_LP_RING();
  460. }
  461. static void i810EmitState(struct drm_device *dev)
  462. {
  463. drm_i810_private_t *dev_priv = dev->dev_private;
  464. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  465. unsigned int dirty = sarea_priv->dirty;
  466. DRM_DEBUG("%x\n", dirty);
  467. if (dirty & I810_UPLOAD_BUFFERS) {
  468. i810EmitDestVerified(dev, sarea_priv->BufferState);
  469. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  470. }
  471. if (dirty & I810_UPLOAD_CTX) {
  472. i810EmitContextVerified(dev, sarea_priv->ContextState);
  473. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  474. }
  475. if (dirty & I810_UPLOAD_TEX0) {
  476. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  477. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  478. }
  479. if (dirty & I810_UPLOAD_TEX1) {
  480. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  481. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  482. }
  483. }
  484. /* need to verify
  485. */
  486. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  487. unsigned int clear_color,
  488. unsigned int clear_zval)
  489. {
  490. drm_i810_private_t *dev_priv = dev->dev_private;
  491. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  492. int nbox = sarea_priv->nbox;
  493. struct drm_clip_rect *pbox = sarea_priv->boxes;
  494. int pitch = dev_priv->pitch;
  495. int cpp = 2;
  496. int i;
  497. RING_LOCALS;
  498. if (dev_priv->current_page == 1) {
  499. unsigned int tmp = flags;
  500. flags &= ~(I810_FRONT | I810_BACK);
  501. if (tmp & I810_FRONT)
  502. flags |= I810_BACK;
  503. if (tmp & I810_BACK)
  504. flags |= I810_FRONT;
  505. }
  506. i810_kernel_lost_context(dev);
  507. if (nbox > I810_NR_SAREA_CLIPRECTS)
  508. nbox = I810_NR_SAREA_CLIPRECTS;
  509. for (i = 0; i < nbox; i++, pbox++) {
  510. unsigned int x = pbox->x1;
  511. unsigned int y = pbox->y1;
  512. unsigned int width = (pbox->x2 - x) * cpp;
  513. unsigned int height = pbox->y2 - y;
  514. unsigned int start = y * pitch + x * cpp;
  515. if (pbox->x1 > pbox->x2 ||
  516. pbox->y1 > pbox->y2 ||
  517. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  518. continue;
  519. if (flags & I810_FRONT) {
  520. BEGIN_LP_RING(6);
  521. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  522. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  523. OUT_RING((height << 16) | width);
  524. OUT_RING(start);
  525. OUT_RING(clear_color);
  526. OUT_RING(0);
  527. ADVANCE_LP_RING();
  528. }
  529. if (flags & I810_BACK) {
  530. BEGIN_LP_RING(6);
  531. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  532. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  533. OUT_RING((height << 16) | width);
  534. OUT_RING(dev_priv->back_offset + start);
  535. OUT_RING(clear_color);
  536. OUT_RING(0);
  537. ADVANCE_LP_RING();
  538. }
  539. if (flags & I810_DEPTH) {
  540. BEGIN_LP_RING(6);
  541. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  542. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  543. OUT_RING((height << 16) | width);
  544. OUT_RING(dev_priv->depth_offset + start);
  545. OUT_RING(clear_zval);
  546. OUT_RING(0);
  547. ADVANCE_LP_RING();
  548. }
  549. }
  550. }
  551. static void i810_dma_dispatch_swap(struct drm_device *dev)
  552. {
  553. drm_i810_private_t *dev_priv = dev->dev_private;
  554. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  555. int nbox = sarea_priv->nbox;
  556. struct drm_clip_rect *pbox = sarea_priv->boxes;
  557. int pitch = dev_priv->pitch;
  558. int cpp = 2;
  559. int i;
  560. RING_LOCALS;
  561. DRM_DEBUG("swapbuffers\n");
  562. i810_kernel_lost_context(dev);
  563. if (nbox > I810_NR_SAREA_CLIPRECTS)
  564. nbox = I810_NR_SAREA_CLIPRECTS;
  565. for (i = 0; i < nbox; i++, pbox++) {
  566. unsigned int w = pbox->x2 - pbox->x1;
  567. unsigned int h = pbox->y2 - pbox->y1;
  568. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  569. unsigned int start = dst;
  570. if (pbox->x1 > pbox->x2 ||
  571. pbox->y1 > pbox->y2 ||
  572. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  573. continue;
  574. BEGIN_LP_RING(6);
  575. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  576. OUT_RING(pitch | (0xCC << 16));
  577. OUT_RING((h << 16) | (w * cpp));
  578. if (dev_priv->current_page == 0)
  579. OUT_RING(dev_priv->front_offset + start);
  580. else
  581. OUT_RING(dev_priv->back_offset + start);
  582. OUT_RING(pitch);
  583. if (dev_priv->current_page == 0)
  584. OUT_RING(dev_priv->back_offset + start);
  585. else
  586. OUT_RING(dev_priv->front_offset + start);
  587. ADVANCE_LP_RING();
  588. }
  589. }
  590. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  591. struct drm_buf *buf, int discard, int used)
  592. {
  593. drm_i810_private_t *dev_priv = dev->dev_private;
  594. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  595. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  596. struct drm_clip_rect *box = sarea_priv->boxes;
  597. int nbox = sarea_priv->nbox;
  598. unsigned long address = (unsigned long)buf->bus_address;
  599. unsigned long start = address - dev->agp->base;
  600. int i = 0;
  601. RING_LOCALS;
  602. i810_kernel_lost_context(dev);
  603. if (nbox > I810_NR_SAREA_CLIPRECTS)
  604. nbox = I810_NR_SAREA_CLIPRECTS;
  605. if (used < 0 || used > 4 * 1024)
  606. used = 0;
  607. if (sarea_priv->dirty)
  608. i810EmitState(dev);
  609. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  610. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  611. *(u32 *) buf_priv->kernel_virtual =
  612. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  613. if (used & 4) {
  614. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  615. used += 4;
  616. }
  617. i810_unmap_buffer(buf);
  618. }
  619. if (used) {
  620. do {
  621. if (i < nbox) {
  622. BEGIN_LP_RING(4);
  623. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  624. SC_ENABLE);
  625. OUT_RING(GFX_OP_SCISSOR_INFO);
  626. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  627. OUT_RING((box[i].x2 -
  628. 1) | ((box[i].y2 - 1) << 16));
  629. ADVANCE_LP_RING();
  630. }
  631. BEGIN_LP_RING(4);
  632. OUT_RING(CMD_OP_BATCH_BUFFER);
  633. OUT_RING(start | BB1_PROTECTED);
  634. OUT_RING(start + used - 4);
  635. OUT_RING(0);
  636. ADVANCE_LP_RING();
  637. } while (++i < nbox);
  638. }
  639. if (discard) {
  640. dev_priv->counter++;
  641. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  642. I810_BUF_HARDWARE);
  643. BEGIN_LP_RING(8);
  644. OUT_RING(CMD_STORE_DWORD_IDX);
  645. OUT_RING(20);
  646. OUT_RING(dev_priv->counter);
  647. OUT_RING(CMD_STORE_DWORD_IDX);
  648. OUT_RING(buf_priv->my_use_idx);
  649. OUT_RING(I810_BUF_FREE);
  650. OUT_RING(CMD_REPORT_HEAD);
  651. OUT_RING(0);
  652. ADVANCE_LP_RING();
  653. }
  654. }
  655. static void i810_dma_dispatch_flip(struct drm_device *dev)
  656. {
  657. drm_i810_private_t *dev_priv = dev->dev_private;
  658. int pitch = dev_priv->pitch;
  659. RING_LOCALS;
  660. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  661. dev_priv->current_page,
  662. dev_priv->sarea_priv->pf_current_page);
  663. i810_kernel_lost_context(dev);
  664. BEGIN_LP_RING(2);
  665. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  666. OUT_RING(0);
  667. ADVANCE_LP_RING();
  668. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  669. /* On i815 at least ASYNC is buggy */
  670. /* pitch<<5 is from 11.2.8 p158,
  671. its the pitch / 8 then left shifted 8,
  672. so (pitch >> 3) << 8 */
  673. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  674. if (dev_priv->current_page == 0) {
  675. OUT_RING(dev_priv->back_offset);
  676. dev_priv->current_page = 1;
  677. } else {
  678. OUT_RING(dev_priv->front_offset);
  679. dev_priv->current_page = 0;
  680. }
  681. OUT_RING(0);
  682. ADVANCE_LP_RING();
  683. BEGIN_LP_RING(2);
  684. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  685. OUT_RING(0);
  686. ADVANCE_LP_RING();
  687. /* Increment the frame counter. The client-side 3D driver must
  688. * throttle the framerate by waiting for this value before
  689. * performing the swapbuffer ioctl.
  690. */
  691. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  692. }
  693. static void i810_dma_quiescent(struct drm_device *dev)
  694. {
  695. drm_i810_private_t *dev_priv = dev->dev_private;
  696. RING_LOCALS;
  697. i810_kernel_lost_context(dev);
  698. BEGIN_LP_RING(4);
  699. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  700. OUT_RING(CMD_REPORT_HEAD);
  701. OUT_RING(0);
  702. OUT_RING(0);
  703. ADVANCE_LP_RING();
  704. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  705. }
  706. static int i810_flush_queue(struct drm_device *dev)
  707. {
  708. drm_i810_private_t *dev_priv = dev->dev_private;
  709. struct drm_device_dma *dma = dev->dma;
  710. int i, ret = 0;
  711. RING_LOCALS;
  712. i810_kernel_lost_context(dev);
  713. BEGIN_LP_RING(2);
  714. OUT_RING(CMD_REPORT_HEAD);
  715. OUT_RING(0);
  716. ADVANCE_LP_RING();
  717. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  718. for (i = 0; i < dma->buf_count; i++) {
  719. struct drm_buf *buf = dma->buflist[i];
  720. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  721. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  722. I810_BUF_FREE);
  723. if (used == I810_BUF_HARDWARE)
  724. DRM_DEBUG("reclaimed from HARDWARE\n");
  725. if (used == I810_BUF_CLIENT)
  726. DRM_DEBUG("still on client\n");
  727. }
  728. return ret;
  729. }
  730. /* Must be called with the lock held */
  731. void i810_driver_reclaim_buffers(struct drm_device *dev,
  732. struct drm_file *file_priv)
  733. {
  734. struct drm_device_dma *dma = dev->dma;
  735. int i;
  736. if (!dma)
  737. return;
  738. if (!dev->dev_private)
  739. return;
  740. if (!dma->buflist)
  741. return;
  742. i810_flush_queue(dev);
  743. for (i = 0; i < dma->buf_count; i++) {
  744. struct drm_buf *buf = dma->buflist[i];
  745. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  746. if (buf->file_priv == file_priv && buf_priv) {
  747. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  748. I810_BUF_FREE);
  749. if (used == I810_BUF_CLIENT)
  750. DRM_DEBUG("reclaimed from client\n");
  751. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  752. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  753. }
  754. }
  755. }
  756. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  757. struct drm_file *file_priv)
  758. {
  759. LOCK_TEST_WITH_RETURN(dev, file_priv);
  760. i810_flush_queue(dev);
  761. return 0;
  762. }
  763. static int i810_dma_vertex(struct drm_device *dev, void *data,
  764. struct drm_file *file_priv)
  765. {
  766. struct drm_device_dma *dma = dev->dma;
  767. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  768. u32 *hw_status = dev_priv->hw_status_page;
  769. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  770. dev_priv->sarea_priv;
  771. drm_i810_vertex_t *vertex = data;
  772. LOCK_TEST_WITH_RETURN(dev, file_priv);
  773. DRM_DEBUG("idx %d used %d discard %d\n",
  774. vertex->idx, vertex->used, vertex->discard);
  775. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  776. return -EINVAL;
  777. i810_dma_dispatch_vertex(dev,
  778. dma->buflist[vertex->idx],
  779. vertex->discard, vertex->used);
  780. sarea_priv->last_enqueue = dev_priv->counter - 1;
  781. sarea_priv->last_dispatch = (int)hw_status[5];
  782. return 0;
  783. }
  784. static int i810_clear_bufs(struct drm_device *dev, void *data,
  785. struct drm_file *file_priv)
  786. {
  787. drm_i810_clear_t *clear = data;
  788. LOCK_TEST_WITH_RETURN(dev, file_priv);
  789. /* GH: Someone's doing nasty things... */
  790. if (!dev->dev_private)
  791. return -EINVAL;
  792. i810_dma_dispatch_clear(dev, clear->flags,
  793. clear->clear_color, clear->clear_depth);
  794. return 0;
  795. }
  796. static int i810_swap_bufs(struct drm_device *dev, void *data,
  797. struct drm_file *file_priv)
  798. {
  799. DRM_DEBUG("\n");
  800. LOCK_TEST_WITH_RETURN(dev, file_priv);
  801. i810_dma_dispatch_swap(dev);
  802. return 0;
  803. }
  804. static int i810_getage(struct drm_device *dev, void *data,
  805. struct drm_file *file_priv)
  806. {
  807. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  808. u32 *hw_status = dev_priv->hw_status_page;
  809. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  810. dev_priv->sarea_priv;
  811. sarea_priv->last_dispatch = (int)hw_status[5];
  812. return 0;
  813. }
  814. static int i810_getbuf(struct drm_device *dev, void *data,
  815. struct drm_file *file_priv)
  816. {
  817. int retcode = 0;
  818. drm_i810_dma_t *d = data;
  819. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  820. u32 *hw_status = dev_priv->hw_status_page;
  821. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  822. dev_priv->sarea_priv;
  823. LOCK_TEST_WITH_RETURN(dev, file_priv);
  824. d->granted = 0;
  825. retcode = i810_dma_get_buffer(dev, d, file_priv);
  826. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  827. task_pid_nr(current), retcode, d->granted);
  828. sarea_priv->last_dispatch = (int)hw_status[5];
  829. return retcode;
  830. }
  831. static int i810_copybuf(struct drm_device *dev, void *data,
  832. struct drm_file *file_priv)
  833. {
  834. /* Never copy - 2.4.x doesn't need it */
  835. return 0;
  836. }
  837. static int i810_docopy(struct drm_device *dev, void *data,
  838. struct drm_file *file_priv)
  839. {
  840. /* Never copy - 2.4.x doesn't need it */
  841. return 0;
  842. }
  843. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  844. unsigned int last_render)
  845. {
  846. drm_i810_private_t *dev_priv = dev->dev_private;
  847. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  848. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  849. unsigned long address = (unsigned long)buf->bus_address;
  850. unsigned long start = address - dev->agp->base;
  851. int u;
  852. RING_LOCALS;
  853. i810_kernel_lost_context(dev);
  854. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  855. if (u != I810_BUF_CLIENT)
  856. DRM_DEBUG("MC found buffer that isn't mine!\n");
  857. if (used < 0 || used > 4 * 1024)
  858. used = 0;
  859. sarea_priv->dirty = 0x7f;
  860. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  861. dev_priv->counter++;
  862. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  863. DRM_DEBUG("start : %lx\n", start);
  864. DRM_DEBUG("used : %d\n", used);
  865. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  866. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  867. if (used & 4) {
  868. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  869. used += 4;
  870. }
  871. i810_unmap_buffer(buf);
  872. }
  873. BEGIN_LP_RING(4);
  874. OUT_RING(CMD_OP_BATCH_BUFFER);
  875. OUT_RING(start | BB1_PROTECTED);
  876. OUT_RING(start + used - 4);
  877. OUT_RING(0);
  878. ADVANCE_LP_RING();
  879. BEGIN_LP_RING(8);
  880. OUT_RING(CMD_STORE_DWORD_IDX);
  881. OUT_RING(buf_priv->my_use_idx);
  882. OUT_RING(I810_BUF_FREE);
  883. OUT_RING(0);
  884. OUT_RING(CMD_STORE_DWORD_IDX);
  885. OUT_RING(16);
  886. OUT_RING(last_render);
  887. OUT_RING(0);
  888. ADVANCE_LP_RING();
  889. }
  890. static int i810_dma_mc(struct drm_device *dev, void *data,
  891. struct drm_file *file_priv)
  892. {
  893. struct drm_device_dma *dma = dev->dma;
  894. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  895. u32 *hw_status = dev_priv->hw_status_page;
  896. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  897. dev_priv->sarea_priv;
  898. drm_i810_mc_t *mc = data;
  899. LOCK_TEST_WITH_RETURN(dev, file_priv);
  900. if (mc->idx >= dma->buf_count || mc->idx < 0)
  901. return -EINVAL;
  902. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  903. mc->last_render);
  904. sarea_priv->last_enqueue = dev_priv->counter - 1;
  905. sarea_priv->last_dispatch = (int)hw_status[5];
  906. return 0;
  907. }
  908. static int i810_rstatus(struct drm_device *dev, void *data,
  909. struct drm_file *file_priv)
  910. {
  911. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  912. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  913. }
  914. static int i810_ov0_info(struct drm_device *dev, void *data,
  915. struct drm_file *file_priv)
  916. {
  917. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  918. drm_i810_overlay_t *ov = data;
  919. ov->offset = dev_priv->overlay_offset;
  920. ov->physical = dev_priv->overlay_physical;
  921. return 0;
  922. }
  923. static int i810_fstatus(struct drm_device *dev, void *data,
  924. struct drm_file *file_priv)
  925. {
  926. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  927. LOCK_TEST_WITH_RETURN(dev, file_priv);
  928. return I810_READ(0x30008);
  929. }
  930. static int i810_ov0_flip(struct drm_device *dev, void *data,
  931. struct drm_file *file_priv)
  932. {
  933. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  934. LOCK_TEST_WITH_RETURN(dev, file_priv);
  935. /* Tell the overlay to update */
  936. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  937. return 0;
  938. }
  939. /* Not sure why this isn't set all the time:
  940. */
  941. static void i810_do_init_pageflip(struct drm_device *dev)
  942. {
  943. drm_i810_private_t *dev_priv = dev->dev_private;
  944. DRM_DEBUG("\n");
  945. dev_priv->page_flipping = 1;
  946. dev_priv->current_page = 0;
  947. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  948. }
  949. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  950. {
  951. drm_i810_private_t *dev_priv = dev->dev_private;
  952. DRM_DEBUG("\n");
  953. if (dev_priv->current_page != 0)
  954. i810_dma_dispatch_flip(dev);
  955. dev_priv->page_flipping = 0;
  956. return 0;
  957. }
  958. static int i810_flip_bufs(struct drm_device *dev, void *data,
  959. struct drm_file *file_priv)
  960. {
  961. drm_i810_private_t *dev_priv = dev->dev_private;
  962. DRM_DEBUG("\n");
  963. LOCK_TEST_WITH_RETURN(dev, file_priv);
  964. if (!dev_priv->page_flipping)
  965. i810_do_init_pageflip(dev);
  966. i810_dma_dispatch_flip(dev);
  967. return 0;
  968. }
  969. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  970. {
  971. dev->agp = drm_agp_init(dev);
  972. if (dev->agp) {
  973. dev->agp->agp_mtrr = arch_phys_wc_add(
  974. dev->agp->agp_info.aper_base,
  975. dev->agp->agp_info.aper_size *
  976. 1024 * 1024);
  977. }
  978. /* Our userspace depends upon the agp mapping support. */
  979. if (!dev->agp)
  980. return -EINVAL;
  981. pci_set_master(dev->pdev);
  982. return 0;
  983. }
  984. void i810_driver_lastclose(struct drm_device *dev)
  985. {
  986. i810_dma_cleanup(dev);
  987. }
  988. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  989. {
  990. if (dev->dev_private) {
  991. drm_i810_private_t *dev_priv = dev->dev_private;
  992. if (dev_priv->page_flipping)
  993. i810_do_cleanup_pageflip(dev);
  994. }
  995. if (file_priv->master && file_priv->master->lock.hw_lock) {
  996. drm_legacy_idlelock_take(&file_priv->master->lock);
  997. i810_driver_reclaim_buffers(dev, file_priv);
  998. drm_legacy_idlelock_release(&file_priv->master->lock);
  999. } else {
  1000. /* master disappeared, clean up stuff anyway and hope nothing
  1001. * goes wrong */
  1002. i810_driver_reclaim_buffers(dev, file_priv);
  1003. }
  1004. }
  1005. int i810_driver_dma_quiescent(struct drm_device *dev)
  1006. {
  1007. i810_dma_quiescent(dev);
  1008. return 0;
  1009. }
  1010. const struct drm_ioctl_desc i810_ioctls[] = {
  1011. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1012. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1013. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1014. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1015. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1016. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1026. };
  1027. int i810_max_ioctl = ARRAY_SIZE(i810_ioctls);