kv_dpm.c 91 KB

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  1. /*
  2. * Copyright 2013 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <drm/drmP.h>
  24. #include "amdgpu.h"
  25. #include "amdgpu_pm.h"
  26. #include "cikd.h"
  27. #include "atom.h"
  28. #include "amdgpu_atombios.h"
  29. #include "amdgpu_dpm.h"
  30. #include "kv_dpm.h"
  31. #include "gfx_v7_0.h"
  32. #include <linux/seq_file.h>
  33. #include "smu/smu_7_0_0_d.h"
  34. #include "smu/smu_7_0_0_sh_mask.h"
  35. #include "gca/gfx_7_2_d.h"
  36. #include "gca/gfx_7_2_sh_mask.h"
  37. #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
  38. #define KV_MINIMUM_ENGINE_CLOCK 800
  39. #define SMC_RAM_END 0x40000
  40. static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
  41. static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
  42. static int kv_enable_nb_dpm(struct amdgpu_device *adev,
  43. bool enable);
  44. static void kv_init_graphics_levels(struct amdgpu_device *adev);
  45. static int kv_calculate_ds_divider(struct amdgpu_device *adev);
  46. static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
  47. static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
  48. static void kv_enable_new_levels(struct amdgpu_device *adev);
  49. static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
  50. struct amdgpu_ps *new_rps);
  51. static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
  52. static int kv_set_enabled_levels(struct amdgpu_device *adev);
  53. static int kv_force_dpm_highest(struct amdgpu_device *adev);
  54. static int kv_force_dpm_lowest(struct amdgpu_device *adev);
  55. static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
  56. struct amdgpu_ps *new_rps,
  57. struct amdgpu_ps *old_rps);
  58. static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
  59. int min_temp, int max_temp);
  60. static int kv_init_fps_limits(struct amdgpu_device *adev);
  61. static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
  62. static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
  63. static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
  64. static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
  65. static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
  66. struct sumo_vid_mapping_table *vid_mapping_table,
  67. u32 vid_2bit)
  68. {
  69. struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  70. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  71. u32 i;
  72. if (vddc_sclk_table && vddc_sclk_table->count) {
  73. if (vid_2bit < vddc_sclk_table->count)
  74. return vddc_sclk_table->entries[vid_2bit].v;
  75. else
  76. return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
  77. } else {
  78. for (i = 0; i < vid_mapping_table->num_entries; i++) {
  79. if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
  80. return vid_mapping_table->entries[i].vid_7bit;
  81. }
  82. return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
  83. }
  84. }
  85. static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
  86. struct sumo_vid_mapping_table *vid_mapping_table,
  87. u32 vid_7bit)
  88. {
  89. struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  90. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  91. u32 i;
  92. if (vddc_sclk_table && vddc_sclk_table->count) {
  93. for (i = 0; i < vddc_sclk_table->count; i++) {
  94. if (vddc_sclk_table->entries[i].v == vid_7bit)
  95. return i;
  96. }
  97. return vddc_sclk_table->count - 1;
  98. } else {
  99. for (i = 0; i < vid_mapping_table->num_entries; i++) {
  100. if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
  101. return vid_mapping_table->entries[i].vid_2bit;
  102. }
  103. return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
  104. }
  105. }
  106. static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
  107. {
  108. /* This bit selects who handles display phy powergating.
  109. * Clear the bit to let atom handle it.
  110. * Set it to let the driver handle it.
  111. * For now we just let atom handle it.
  112. */
  113. #if 0
  114. u32 v = RREG32(mmDOUT_SCRATCH3);
  115. if (enable)
  116. v |= 0x4;
  117. else
  118. v &= 0xFFFFFFFB;
  119. WREG32(mmDOUT_SCRATCH3, v);
  120. #endif
  121. }
  122. static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
  123. struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
  124. ATOM_AVAILABLE_SCLK_LIST *table)
  125. {
  126. u32 i;
  127. u32 n = 0;
  128. u32 prev_sclk = 0;
  129. for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
  130. if (table[i].ulSupportedSCLK > prev_sclk) {
  131. sclk_voltage_mapping_table->entries[n].sclk_frequency =
  132. table[i].ulSupportedSCLK;
  133. sclk_voltage_mapping_table->entries[n].vid_2bit =
  134. table[i].usVoltageIndex;
  135. prev_sclk = table[i].ulSupportedSCLK;
  136. n++;
  137. }
  138. }
  139. sclk_voltage_mapping_table->num_max_dpm_entries = n;
  140. }
  141. static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
  142. struct sumo_vid_mapping_table *vid_mapping_table,
  143. ATOM_AVAILABLE_SCLK_LIST *table)
  144. {
  145. u32 i, j;
  146. for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
  147. if (table[i].ulSupportedSCLK != 0) {
  148. vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
  149. table[i].usVoltageID;
  150. vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
  151. table[i].usVoltageIndex;
  152. }
  153. }
  154. for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
  155. if (vid_mapping_table->entries[i].vid_7bit == 0) {
  156. for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
  157. if (vid_mapping_table->entries[j].vid_7bit != 0) {
  158. vid_mapping_table->entries[i] =
  159. vid_mapping_table->entries[j];
  160. vid_mapping_table->entries[j].vid_7bit = 0;
  161. break;
  162. }
  163. }
  164. if (j == SUMO_MAX_NUMBER_VOLTAGES)
  165. break;
  166. }
  167. }
  168. vid_mapping_table->num_entries = i;
  169. }
  170. #if 0
  171. static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
  172. {
  173. { 0, 4, 1 },
  174. { 1, 4, 1 },
  175. { 2, 5, 1 },
  176. { 3, 4, 2 },
  177. { 4, 1, 1 },
  178. { 5, 5, 2 },
  179. { 6, 6, 1 },
  180. { 7, 9, 2 },
  181. { 0xffffffff }
  182. };
  183. static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
  184. {
  185. { 0, 4, 1 },
  186. { 0xffffffff }
  187. };
  188. static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
  189. {
  190. { 0, 4, 1 },
  191. { 0xffffffff }
  192. };
  193. static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
  194. {
  195. { 0, 4, 1 },
  196. { 0xffffffff }
  197. };
  198. static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
  199. {
  200. { 0, 4, 1 },
  201. { 0xffffffff }
  202. };
  203. static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
  204. {
  205. { 0, 4, 1 },
  206. { 1, 4, 1 },
  207. { 2, 5, 1 },
  208. { 3, 4, 1 },
  209. { 4, 1, 1 },
  210. { 5, 5, 1 },
  211. { 6, 6, 1 },
  212. { 7, 9, 1 },
  213. { 8, 4, 1 },
  214. { 9, 2, 1 },
  215. { 10, 3, 1 },
  216. { 11, 6, 1 },
  217. { 12, 8, 2 },
  218. { 13, 1, 1 },
  219. { 14, 2, 1 },
  220. { 15, 3, 1 },
  221. { 16, 1, 1 },
  222. { 17, 4, 1 },
  223. { 18, 3, 1 },
  224. { 19, 1, 1 },
  225. { 20, 8, 1 },
  226. { 21, 5, 1 },
  227. { 22, 1, 1 },
  228. { 23, 1, 1 },
  229. { 24, 4, 1 },
  230. { 27, 6, 1 },
  231. { 28, 1, 1 },
  232. { 0xffffffff }
  233. };
  234. static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
  235. {
  236. { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
  237. };
  238. static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
  239. {
  240. { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
  241. };
  242. static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
  243. {
  244. { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
  245. };
  246. static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
  247. {
  248. { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
  249. };
  250. static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
  251. {
  252. { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
  253. };
  254. static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
  255. {
  256. { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
  257. };
  258. #endif
  259. static const struct kv_pt_config_reg didt_config_kv[] =
  260. {
  261. { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  262. { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  263. { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  264. { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  265. { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  266. { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  267. { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  268. { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  269. { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  270. { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  271. { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  272. { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  273. { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
  274. { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
  275. { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
  276. { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  277. { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  278. { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  279. { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  280. { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  281. { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  282. { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  283. { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  284. { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  285. { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  286. { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  287. { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  288. { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  289. { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  290. { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  291. { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
  292. { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
  293. { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
  294. { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  295. { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  296. { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  297. { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  298. { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  299. { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  300. { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  301. { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  302. { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  303. { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  304. { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  305. { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  306. { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  307. { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  308. { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  309. { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
  310. { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
  311. { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
  312. { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  313. { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  314. { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  315. { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  316. { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  317. { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  318. { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  319. { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  320. { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  321. { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  322. { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  323. { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  324. { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
  325. { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
  326. { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
  327. { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
  328. { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
  329. { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
  330. { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  331. { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
  332. { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
  333. { 0xFFFFFFFF }
  334. };
  335. static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
  336. {
  337. struct kv_ps *ps = rps->ps_priv;
  338. return ps;
  339. }
  340. static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
  341. {
  342. struct kv_power_info *pi = adev->pm.dpm.priv;
  343. return pi;
  344. }
  345. #if 0
  346. static void kv_program_local_cac_table(struct amdgpu_device *adev,
  347. const struct kv_lcac_config_values *local_cac_table,
  348. const struct kv_lcac_config_reg *local_cac_reg)
  349. {
  350. u32 i, count, data;
  351. const struct kv_lcac_config_values *values = local_cac_table;
  352. while (values->block_id != 0xffffffff) {
  353. count = values->signal_id;
  354. for (i = 0; i < count; i++) {
  355. data = ((values->block_id << local_cac_reg->block_shift) &
  356. local_cac_reg->block_mask);
  357. data |= ((i << local_cac_reg->signal_shift) &
  358. local_cac_reg->signal_mask);
  359. data |= ((values->t << local_cac_reg->t_shift) &
  360. local_cac_reg->t_mask);
  361. data |= ((1 << local_cac_reg->enable_shift) &
  362. local_cac_reg->enable_mask);
  363. WREG32_SMC(local_cac_reg->cntl, data);
  364. }
  365. values++;
  366. }
  367. }
  368. #endif
  369. static int kv_program_pt_config_registers(struct amdgpu_device *adev,
  370. const struct kv_pt_config_reg *cac_config_regs)
  371. {
  372. const struct kv_pt_config_reg *config_regs = cac_config_regs;
  373. u32 data;
  374. u32 cache = 0;
  375. if (config_regs == NULL)
  376. return -EINVAL;
  377. while (config_regs->offset != 0xFFFFFFFF) {
  378. if (config_regs->type == KV_CONFIGREG_CACHE) {
  379. cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
  380. } else {
  381. switch (config_regs->type) {
  382. case KV_CONFIGREG_SMC_IND:
  383. data = RREG32_SMC(config_regs->offset);
  384. break;
  385. case KV_CONFIGREG_DIDT_IND:
  386. data = RREG32_DIDT(config_regs->offset);
  387. break;
  388. default:
  389. data = RREG32(config_regs->offset);
  390. break;
  391. }
  392. data &= ~config_regs->mask;
  393. data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
  394. data |= cache;
  395. cache = 0;
  396. switch (config_regs->type) {
  397. case KV_CONFIGREG_SMC_IND:
  398. WREG32_SMC(config_regs->offset, data);
  399. break;
  400. case KV_CONFIGREG_DIDT_IND:
  401. WREG32_DIDT(config_regs->offset, data);
  402. break;
  403. default:
  404. WREG32(config_regs->offset, data);
  405. break;
  406. }
  407. }
  408. config_regs++;
  409. }
  410. return 0;
  411. }
  412. static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
  413. {
  414. struct kv_power_info *pi = kv_get_pi(adev);
  415. u32 data;
  416. if (pi->caps_sq_ramping) {
  417. data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
  418. if (enable)
  419. data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
  420. else
  421. data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
  422. WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
  423. }
  424. if (pi->caps_db_ramping) {
  425. data = RREG32_DIDT(ixDIDT_DB_CTRL0);
  426. if (enable)
  427. data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
  428. else
  429. data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
  430. WREG32_DIDT(ixDIDT_DB_CTRL0, data);
  431. }
  432. if (pi->caps_td_ramping) {
  433. data = RREG32_DIDT(ixDIDT_TD_CTRL0);
  434. if (enable)
  435. data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
  436. else
  437. data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
  438. WREG32_DIDT(ixDIDT_TD_CTRL0, data);
  439. }
  440. if (pi->caps_tcp_ramping) {
  441. data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
  442. if (enable)
  443. data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
  444. else
  445. data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
  446. WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
  447. }
  448. }
  449. static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
  450. {
  451. struct kv_power_info *pi = kv_get_pi(adev);
  452. int ret;
  453. if (pi->caps_sq_ramping ||
  454. pi->caps_db_ramping ||
  455. pi->caps_td_ramping ||
  456. pi->caps_tcp_ramping) {
  457. adev->gfx.rlc.funcs->enter_safe_mode(adev);
  458. if (enable) {
  459. ret = kv_program_pt_config_registers(adev, didt_config_kv);
  460. if (ret) {
  461. adev->gfx.rlc.funcs->exit_safe_mode(adev);
  462. return ret;
  463. }
  464. }
  465. kv_do_enable_didt(adev, enable);
  466. adev->gfx.rlc.funcs->exit_safe_mode(adev);
  467. }
  468. return 0;
  469. }
  470. #if 0
  471. static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
  472. {
  473. struct kv_power_info *pi = kv_get_pi(adev);
  474. if (pi->caps_cac) {
  475. WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
  476. WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
  477. kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
  478. WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
  479. WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
  480. kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
  481. WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
  482. WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
  483. kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
  484. WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
  485. WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
  486. kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
  487. WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
  488. WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
  489. kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
  490. WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
  491. WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
  492. kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
  493. }
  494. }
  495. #endif
  496. static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
  497. {
  498. struct kv_power_info *pi = kv_get_pi(adev);
  499. int ret = 0;
  500. if (pi->caps_cac) {
  501. if (enable) {
  502. ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
  503. if (ret)
  504. pi->cac_enabled = false;
  505. else
  506. pi->cac_enabled = true;
  507. } else if (pi->cac_enabled) {
  508. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
  509. pi->cac_enabled = false;
  510. }
  511. }
  512. return ret;
  513. }
  514. static int kv_process_firmware_header(struct amdgpu_device *adev)
  515. {
  516. struct kv_power_info *pi = kv_get_pi(adev);
  517. u32 tmp;
  518. int ret;
  519. ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
  520. offsetof(SMU7_Firmware_Header, DpmTable),
  521. &tmp, pi->sram_end);
  522. if (ret == 0)
  523. pi->dpm_table_start = tmp;
  524. ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
  525. offsetof(SMU7_Firmware_Header, SoftRegisters),
  526. &tmp, pi->sram_end);
  527. if (ret == 0)
  528. pi->soft_regs_start = tmp;
  529. return ret;
  530. }
  531. static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
  532. {
  533. struct kv_power_info *pi = kv_get_pi(adev);
  534. int ret;
  535. pi->graphics_voltage_change_enable = 1;
  536. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  537. pi->dpm_table_start +
  538. offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
  539. &pi->graphics_voltage_change_enable,
  540. sizeof(u8), pi->sram_end);
  541. return ret;
  542. }
  543. static int kv_set_dpm_interval(struct amdgpu_device *adev)
  544. {
  545. struct kv_power_info *pi = kv_get_pi(adev);
  546. int ret;
  547. pi->graphics_interval = 1;
  548. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  549. pi->dpm_table_start +
  550. offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
  551. &pi->graphics_interval,
  552. sizeof(u8), pi->sram_end);
  553. return ret;
  554. }
  555. static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
  556. {
  557. struct kv_power_info *pi = kv_get_pi(adev);
  558. int ret;
  559. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  560. pi->dpm_table_start +
  561. offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
  562. &pi->graphics_boot_level,
  563. sizeof(u8), pi->sram_end);
  564. return ret;
  565. }
  566. static void kv_program_vc(struct amdgpu_device *adev)
  567. {
  568. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
  569. }
  570. static void kv_clear_vc(struct amdgpu_device *adev)
  571. {
  572. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
  573. }
  574. static int kv_set_divider_value(struct amdgpu_device *adev,
  575. u32 index, u32 sclk)
  576. {
  577. struct kv_power_info *pi = kv_get_pi(adev);
  578. struct atom_clock_dividers dividers;
  579. int ret;
  580. ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
  581. sclk, false, &dividers);
  582. if (ret)
  583. return ret;
  584. pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
  585. pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
  586. return 0;
  587. }
  588. static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
  589. u16 voltage)
  590. {
  591. return 6200 - (voltage * 25);
  592. }
  593. static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
  594. u32 vid_2bit)
  595. {
  596. struct kv_power_info *pi = kv_get_pi(adev);
  597. u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
  598. &pi->sys_info.vid_mapping_table,
  599. vid_2bit);
  600. return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
  601. }
  602. static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
  603. {
  604. struct kv_power_info *pi = kv_get_pi(adev);
  605. pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
  606. pi->graphics_level[index].MinVddNb =
  607. cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
  608. return 0;
  609. }
  610. static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
  611. {
  612. struct kv_power_info *pi = kv_get_pi(adev);
  613. pi->graphics_level[index].AT = cpu_to_be16((u16)at);
  614. return 0;
  615. }
  616. static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
  617. u32 index, bool enable)
  618. {
  619. struct kv_power_info *pi = kv_get_pi(adev);
  620. pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
  621. }
  622. static void kv_start_dpm(struct amdgpu_device *adev)
  623. {
  624. u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  625. tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
  626. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  627. amdgpu_kv_smc_dpm_enable(adev, true);
  628. }
  629. static void kv_stop_dpm(struct amdgpu_device *adev)
  630. {
  631. amdgpu_kv_smc_dpm_enable(adev, false);
  632. }
  633. static void kv_start_am(struct amdgpu_device *adev)
  634. {
  635. u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  636. sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
  637. SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
  638. sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
  639. WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
  640. }
  641. static void kv_reset_am(struct amdgpu_device *adev)
  642. {
  643. u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  644. sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
  645. SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
  646. WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
  647. }
  648. static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
  649. {
  650. return amdgpu_kv_notify_message_to_smu(adev, freeze ?
  651. PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
  652. }
  653. static int kv_force_lowest_valid(struct amdgpu_device *adev)
  654. {
  655. return kv_force_dpm_lowest(adev);
  656. }
  657. static int kv_unforce_levels(struct amdgpu_device *adev)
  658. {
  659. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
  660. return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
  661. else
  662. return kv_set_enabled_levels(adev);
  663. }
  664. static int kv_update_sclk_t(struct amdgpu_device *adev)
  665. {
  666. struct kv_power_info *pi = kv_get_pi(adev);
  667. u32 low_sclk_interrupt_t = 0;
  668. int ret = 0;
  669. if (pi->caps_sclk_throttle_low_notification) {
  670. low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
  671. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  672. pi->dpm_table_start +
  673. offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
  674. (u8 *)&low_sclk_interrupt_t,
  675. sizeof(u32), pi->sram_end);
  676. }
  677. return ret;
  678. }
  679. static int kv_program_bootup_state(struct amdgpu_device *adev)
  680. {
  681. struct kv_power_info *pi = kv_get_pi(adev);
  682. u32 i;
  683. struct amdgpu_clock_voltage_dependency_table *table =
  684. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  685. if (table && table->count) {
  686. for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
  687. if (table->entries[i].clk == pi->boot_pl.sclk)
  688. break;
  689. }
  690. pi->graphics_boot_level = (u8)i;
  691. kv_dpm_power_level_enable(adev, i, true);
  692. } else {
  693. struct sumo_sclk_voltage_mapping_table *table =
  694. &pi->sys_info.sclk_voltage_mapping_table;
  695. if (table->num_max_dpm_entries == 0)
  696. return -EINVAL;
  697. for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
  698. if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
  699. break;
  700. }
  701. pi->graphics_boot_level = (u8)i;
  702. kv_dpm_power_level_enable(adev, i, true);
  703. }
  704. return 0;
  705. }
  706. static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
  707. {
  708. struct kv_power_info *pi = kv_get_pi(adev);
  709. int ret;
  710. pi->graphics_therm_throttle_enable = 1;
  711. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  712. pi->dpm_table_start +
  713. offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
  714. &pi->graphics_therm_throttle_enable,
  715. sizeof(u8), pi->sram_end);
  716. return ret;
  717. }
  718. static int kv_upload_dpm_settings(struct amdgpu_device *adev)
  719. {
  720. struct kv_power_info *pi = kv_get_pi(adev);
  721. int ret;
  722. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  723. pi->dpm_table_start +
  724. offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
  725. (u8 *)&pi->graphics_level,
  726. sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
  727. pi->sram_end);
  728. if (ret)
  729. return ret;
  730. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  731. pi->dpm_table_start +
  732. offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
  733. &pi->graphics_dpm_level_count,
  734. sizeof(u8), pi->sram_end);
  735. return ret;
  736. }
  737. static u32 kv_get_clock_difference(u32 a, u32 b)
  738. {
  739. return (a >= b) ? a - b : b - a;
  740. }
  741. static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
  742. {
  743. struct kv_power_info *pi = kv_get_pi(adev);
  744. u32 value;
  745. if (pi->caps_enable_dfs_bypass) {
  746. if (kv_get_clock_difference(clk, 40000) < 200)
  747. value = 3;
  748. else if (kv_get_clock_difference(clk, 30000) < 200)
  749. value = 2;
  750. else if (kv_get_clock_difference(clk, 20000) < 200)
  751. value = 7;
  752. else if (kv_get_clock_difference(clk, 15000) < 200)
  753. value = 6;
  754. else if (kv_get_clock_difference(clk, 10000) < 200)
  755. value = 8;
  756. else
  757. value = 0;
  758. } else {
  759. value = 0;
  760. }
  761. return value;
  762. }
  763. static int kv_populate_uvd_table(struct amdgpu_device *adev)
  764. {
  765. struct kv_power_info *pi = kv_get_pi(adev);
  766. struct amdgpu_uvd_clock_voltage_dependency_table *table =
  767. &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
  768. struct atom_clock_dividers dividers;
  769. int ret;
  770. u32 i;
  771. if (table == NULL || table->count == 0)
  772. return 0;
  773. pi->uvd_level_count = 0;
  774. for (i = 0; i < table->count; i++) {
  775. if (pi->high_voltage_t &&
  776. (pi->high_voltage_t < table->entries[i].v))
  777. break;
  778. pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
  779. pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
  780. pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
  781. pi->uvd_level[i].VClkBypassCntl =
  782. (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
  783. pi->uvd_level[i].DClkBypassCntl =
  784. (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
  785. ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
  786. table->entries[i].vclk, false, &dividers);
  787. if (ret)
  788. return ret;
  789. pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
  790. ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
  791. table->entries[i].dclk, false, &dividers);
  792. if (ret)
  793. return ret;
  794. pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
  795. pi->uvd_level_count++;
  796. }
  797. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  798. pi->dpm_table_start +
  799. offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
  800. (u8 *)&pi->uvd_level_count,
  801. sizeof(u8), pi->sram_end);
  802. if (ret)
  803. return ret;
  804. pi->uvd_interval = 1;
  805. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  806. pi->dpm_table_start +
  807. offsetof(SMU7_Fusion_DpmTable, UVDInterval),
  808. &pi->uvd_interval,
  809. sizeof(u8), pi->sram_end);
  810. if (ret)
  811. return ret;
  812. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  813. pi->dpm_table_start +
  814. offsetof(SMU7_Fusion_DpmTable, UvdLevel),
  815. (u8 *)&pi->uvd_level,
  816. sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
  817. pi->sram_end);
  818. return ret;
  819. }
  820. static int kv_populate_vce_table(struct amdgpu_device *adev)
  821. {
  822. struct kv_power_info *pi = kv_get_pi(adev);
  823. int ret;
  824. u32 i;
  825. struct amdgpu_vce_clock_voltage_dependency_table *table =
  826. &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
  827. struct atom_clock_dividers dividers;
  828. if (table == NULL || table->count == 0)
  829. return 0;
  830. pi->vce_level_count = 0;
  831. for (i = 0; i < table->count; i++) {
  832. if (pi->high_voltage_t &&
  833. pi->high_voltage_t < table->entries[i].v)
  834. break;
  835. pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
  836. pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
  837. pi->vce_level[i].ClkBypassCntl =
  838. (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
  839. ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
  840. table->entries[i].evclk, false, &dividers);
  841. if (ret)
  842. return ret;
  843. pi->vce_level[i].Divider = (u8)dividers.post_div;
  844. pi->vce_level_count++;
  845. }
  846. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  847. pi->dpm_table_start +
  848. offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
  849. (u8 *)&pi->vce_level_count,
  850. sizeof(u8),
  851. pi->sram_end);
  852. if (ret)
  853. return ret;
  854. pi->vce_interval = 1;
  855. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  856. pi->dpm_table_start +
  857. offsetof(SMU7_Fusion_DpmTable, VCEInterval),
  858. (u8 *)&pi->vce_interval,
  859. sizeof(u8),
  860. pi->sram_end);
  861. if (ret)
  862. return ret;
  863. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  864. pi->dpm_table_start +
  865. offsetof(SMU7_Fusion_DpmTable, VceLevel),
  866. (u8 *)&pi->vce_level,
  867. sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
  868. pi->sram_end);
  869. return ret;
  870. }
  871. static int kv_populate_samu_table(struct amdgpu_device *adev)
  872. {
  873. struct kv_power_info *pi = kv_get_pi(adev);
  874. struct amdgpu_clock_voltage_dependency_table *table =
  875. &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
  876. struct atom_clock_dividers dividers;
  877. int ret;
  878. u32 i;
  879. if (table == NULL || table->count == 0)
  880. return 0;
  881. pi->samu_level_count = 0;
  882. for (i = 0; i < table->count; i++) {
  883. if (pi->high_voltage_t &&
  884. pi->high_voltage_t < table->entries[i].v)
  885. break;
  886. pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
  887. pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
  888. pi->samu_level[i].ClkBypassCntl =
  889. (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
  890. ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
  891. table->entries[i].clk, false, &dividers);
  892. if (ret)
  893. return ret;
  894. pi->samu_level[i].Divider = (u8)dividers.post_div;
  895. pi->samu_level_count++;
  896. }
  897. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  898. pi->dpm_table_start +
  899. offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
  900. (u8 *)&pi->samu_level_count,
  901. sizeof(u8),
  902. pi->sram_end);
  903. if (ret)
  904. return ret;
  905. pi->samu_interval = 1;
  906. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  907. pi->dpm_table_start +
  908. offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
  909. (u8 *)&pi->samu_interval,
  910. sizeof(u8),
  911. pi->sram_end);
  912. if (ret)
  913. return ret;
  914. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  915. pi->dpm_table_start +
  916. offsetof(SMU7_Fusion_DpmTable, SamuLevel),
  917. (u8 *)&pi->samu_level,
  918. sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
  919. pi->sram_end);
  920. if (ret)
  921. return ret;
  922. return ret;
  923. }
  924. static int kv_populate_acp_table(struct amdgpu_device *adev)
  925. {
  926. struct kv_power_info *pi = kv_get_pi(adev);
  927. struct amdgpu_clock_voltage_dependency_table *table =
  928. &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
  929. struct atom_clock_dividers dividers;
  930. int ret;
  931. u32 i;
  932. if (table == NULL || table->count == 0)
  933. return 0;
  934. pi->acp_level_count = 0;
  935. for (i = 0; i < table->count; i++) {
  936. pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
  937. pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
  938. ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
  939. table->entries[i].clk, false, &dividers);
  940. if (ret)
  941. return ret;
  942. pi->acp_level[i].Divider = (u8)dividers.post_div;
  943. pi->acp_level_count++;
  944. }
  945. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  946. pi->dpm_table_start +
  947. offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
  948. (u8 *)&pi->acp_level_count,
  949. sizeof(u8),
  950. pi->sram_end);
  951. if (ret)
  952. return ret;
  953. pi->acp_interval = 1;
  954. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  955. pi->dpm_table_start +
  956. offsetof(SMU7_Fusion_DpmTable, ACPInterval),
  957. (u8 *)&pi->acp_interval,
  958. sizeof(u8),
  959. pi->sram_end);
  960. if (ret)
  961. return ret;
  962. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  963. pi->dpm_table_start +
  964. offsetof(SMU7_Fusion_DpmTable, AcpLevel),
  965. (u8 *)&pi->acp_level,
  966. sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
  967. pi->sram_end);
  968. if (ret)
  969. return ret;
  970. return ret;
  971. }
  972. static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
  973. {
  974. struct kv_power_info *pi = kv_get_pi(adev);
  975. u32 i;
  976. struct amdgpu_clock_voltage_dependency_table *table =
  977. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  978. if (table && table->count) {
  979. for (i = 0; i < pi->graphics_dpm_level_count; i++) {
  980. if (pi->caps_enable_dfs_bypass) {
  981. if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
  982. pi->graphics_level[i].ClkBypassCntl = 3;
  983. else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
  984. pi->graphics_level[i].ClkBypassCntl = 2;
  985. else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
  986. pi->graphics_level[i].ClkBypassCntl = 7;
  987. else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
  988. pi->graphics_level[i].ClkBypassCntl = 6;
  989. else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
  990. pi->graphics_level[i].ClkBypassCntl = 8;
  991. else
  992. pi->graphics_level[i].ClkBypassCntl = 0;
  993. } else {
  994. pi->graphics_level[i].ClkBypassCntl = 0;
  995. }
  996. }
  997. } else {
  998. struct sumo_sclk_voltage_mapping_table *table =
  999. &pi->sys_info.sclk_voltage_mapping_table;
  1000. for (i = 0; i < pi->graphics_dpm_level_count; i++) {
  1001. if (pi->caps_enable_dfs_bypass) {
  1002. if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
  1003. pi->graphics_level[i].ClkBypassCntl = 3;
  1004. else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
  1005. pi->graphics_level[i].ClkBypassCntl = 2;
  1006. else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
  1007. pi->graphics_level[i].ClkBypassCntl = 7;
  1008. else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
  1009. pi->graphics_level[i].ClkBypassCntl = 6;
  1010. else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
  1011. pi->graphics_level[i].ClkBypassCntl = 8;
  1012. else
  1013. pi->graphics_level[i].ClkBypassCntl = 0;
  1014. } else {
  1015. pi->graphics_level[i].ClkBypassCntl = 0;
  1016. }
  1017. }
  1018. }
  1019. }
  1020. static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
  1021. {
  1022. return amdgpu_kv_notify_message_to_smu(adev, enable ?
  1023. PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
  1024. }
  1025. static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
  1026. {
  1027. struct kv_power_info *pi = kv_get_pi(adev);
  1028. pi->acp_boot_level = 0xff;
  1029. }
  1030. static void kv_update_current_ps(struct amdgpu_device *adev,
  1031. struct amdgpu_ps *rps)
  1032. {
  1033. struct kv_ps *new_ps = kv_get_ps(rps);
  1034. struct kv_power_info *pi = kv_get_pi(adev);
  1035. pi->current_rps = *rps;
  1036. pi->current_ps = *new_ps;
  1037. pi->current_rps.ps_priv = &pi->current_ps;
  1038. adev->pm.dpm.current_ps = &pi->current_rps;
  1039. }
  1040. static void kv_update_requested_ps(struct amdgpu_device *adev,
  1041. struct amdgpu_ps *rps)
  1042. {
  1043. struct kv_ps *new_ps = kv_get_ps(rps);
  1044. struct kv_power_info *pi = kv_get_pi(adev);
  1045. pi->requested_rps = *rps;
  1046. pi->requested_ps = *new_ps;
  1047. pi->requested_rps.ps_priv = &pi->requested_ps;
  1048. adev->pm.dpm.requested_ps = &pi->requested_rps;
  1049. }
  1050. static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
  1051. {
  1052. struct kv_power_info *pi = kv_get_pi(adev);
  1053. int ret;
  1054. if (pi->bapm_enable) {
  1055. ret = amdgpu_kv_smc_bapm_enable(adev, enable);
  1056. if (ret)
  1057. DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
  1058. }
  1059. }
  1060. static int kv_dpm_enable(struct amdgpu_device *adev)
  1061. {
  1062. struct kv_power_info *pi = kv_get_pi(adev);
  1063. int ret;
  1064. ret = kv_process_firmware_header(adev);
  1065. if (ret) {
  1066. DRM_ERROR("kv_process_firmware_header failed\n");
  1067. return ret;
  1068. }
  1069. kv_init_fps_limits(adev);
  1070. kv_init_graphics_levels(adev);
  1071. ret = kv_program_bootup_state(adev);
  1072. if (ret) {
  1073. DRM_ERROR("kv_program_bootup_state failed\n");
  1074. return ret;
  1075. }
  1076. kv_calculate_dfs_bypass_settings(adev);
  1077. ret = kv_upload_dpm_settings(adev);
  1078. if (ret) {
  1079. DRM_ERROR("kv_upload_dpm_settings failed\n");
  1080. return ret;
  1081. }
  1082. ret = kv_populate_uvd_table(adev);
  1083. if (ret) {
  1084. DRM_ERROR("kv_populate_uvd_table failed\n");
  1085. return ret;
  1086. }
  1087. ret = kv_populate_vce_table(adev);
  1088. if (ret) {
  1089. DRM_ERROR("kv_populate_vce_table failed\n");
  1090. return ret;
  1091. }
  1092. ret = kv_populate_samu_table(adev);
  1093. if (ret) {
  1094. DRM_ERROR("kv_populate_samu_table failed\n");
  1095. return ret;
  1096. }
  1097. ret = kv_populate_acp_table(adev);
  1098. if (ret) {
  1099. DRM_ERROR("kv_populate_acp_table failed\n");
  1100. return ret;
  1101. }
  1102. kv_program_vc(adev);
  1103. #if 0
  1104. kv_initialize_hardware_cac_manager(adev);
  1105. #endif
  1106. kv_start_am(adev);
  1107. if (pi->enable_auto_thermal_throttling) {
  1108. ret = kv_enable_auto_thermal_throttling(adev);
  1109. if (ret) {
  1110. DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
  1111. return ret;
  1112. }
  1113. }
  1114. ret = kv_enable_dpm_voltage_scaling(adev);
  1115. if (ret) {
  1116. DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
  1117. return ret;
  1118. }
  1119. ret = kv_set_dpm_interval(adev);
  1120. if (ret) {
  1121. DRM_ERROR("kv_set_dpm_interval failed\n");
  1122. return ret;
  1123. }
  1124. ret = kv_set_dpm_boot_state(adev);
  1125. if (ret) {
  1126. DRM_ERROR("kv_set_dpm_boot_state failed\n");
  1127. return ret;
  1128. }
  1129. ret = kv_enable_ulv(adev, true);
  1130. if (ret) {
  1131. DRM_ERROR("kv_enable_ulv failed\n");
  1132. return ret;
  1133. }
  1134. kv_start_dpm(adev);
  1135. ret = kv_enable_didt(adev, true);
  1136. if (ret) {
  1137. DRM_ERROR("kv_enable_didt failed\n");
  1138. return ret;
  1139. }
  1140. ret = kv_enable_smc_cac(adev, true);
  1141. if (ret) {
  1142. DRM_ERROR("kv_enable_smc_cac failed\n");
  1143. return ret;
  1144. }
  1145. kv_reset_acp_boot_level(adev);
  1146. ret = amdgpu_kv_smc_bapm_enable(adev, false);
  1147. if (ret) {
  1148. DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
  1149. return ret;
  1150. }
  1151. if (adev->irq.installed &&
  1152. amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
  1153. ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
  1154. if (ret) {
  1155. DRM_ERROR("kv_set_thermal_temperature_range failed\n");
  1156. return ret;
  1157. }
  1158. amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
  1159. AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
  1160. amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
  1161. AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
  1162. }
  1163. return ret;
  1164. }
  1165. static void kv_dpm_disable(struct amdgpu_device *adev)
  1166. {
  1167. amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
  1168. AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
  1169. amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
  1170. AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
  1171. amdgpu_kv_smc_bapm_enable(adev, false);
  1172. if (adev->asic_type == CHIP_MULLINS)
  1173. kv_enable_nb_dpm(adev, false);
  1174. /* powerup blocks */
  1175. kv_dpm_powergate_acp(adev, false);
  1176. kv_dpm_powergate_samu(adev, false);
  1177. kv_dpm_powergate_vce(adev, false);
  1178. kv_dpm_powergate_uvd(adev, false);
  1179. kv_enable_smc_cac(adev, false);
  1180. kv_enable_didt(adev, false);
  1181. kv_clear_vc(adev);
  1182. kv_stop_dpm(adev);
  1183. kv_enable_ulv(adev, false);
  1184. kv_reset_am(adev);
  1185. kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
  1186. }
  1187. #if 0
  1188. static int kv_write_smc_soft_register(struct amdgpu_device *adev,
  1189. u16 reg_offset, u32 value)
  1190. {
  1191. struct kv_power_info *pi = kv_get_pi(adev);
  1192. return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
  1193. (u8 *)&value, sizeof(u16), pi->sram_end);
  1194. }
  1195. static int kv_read_smc_soft_register(struct amdgpu_device *adev,
  1196. u16 reg_offset, u32 *value)
  1197. {
  1198. struct kv_power_info *pi = kv_get_pi(adev);
  1199. return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
  1200. value, pi->sram_end);
  1201. }
  1202. #endif
  1203. static void kv_init_sclk_t(struct amdgpu_device *adev)
  1204. {
  1205. struct kv_power_info *pi = kv_get_pi(adev);
  1206. pi->low_sclk_interrupt_t = 0;
  1207. }
  1208. static int kv_init_fps_limits(struct amdgpu_device *adev)
  1209. {
  1210. struct kv_power_info *pi = kv_get_pi(adev);
  1211. int ret = 0;
  1212. if (pi->caps_fps) {
  1213. u16 tmp;
  1214. tmp = 45;
  1215. pi->fps_high_t = cpu_to_be16(tmp);
  1216. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1217. pi->dpm_table_start +
  1218. offsetof(SMU7_Fusion_DpmTable, FpsHighT),
  1219. (u8 *)&pi->fps_high_t,
  1220. sizeof(u16), pi->sram_end);
  1221. tmp = 30;
  1222. pi->fps_low_t = cpu_to_be16(tmp);
  1223. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1224. pi->dpm_table_start +
  1225. offsetof(SMU7_Fusion_DpmTable, FpsLowT),
  1226. (u8 *)&pi->fps_low_t,
  1227. sizeof(u16), pi->sram_end);
  1228. }
  1229. return ret;
  1230. }
  1231. static void kv_init_powergate_state(struct amdgpu_device *adev)
  1232. {
  1233. struct kv_power_info *pi = kv_get_pi(adev);
  1234. pi->uvd_power_gated = false;
  1235. pi->vce_power_gated = false;
  1236. pi->samu_power_gated = false;
  1237. pi->acp_power_gated = false;
  1238. }
  1239. static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
  1240. {
  1241. return amdgpu_kv_notify_message_to_smu(adev, enable ?
  1242. PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
  1243. }
  1244. static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
  1245. {
  1246. return amdgpu_kv_notify_message_to_smu(adev, enable ?
  1247. PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
  1248. }
  1249. static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
  1250. {
  1251. return amdgpu_kv_notify_message_to_smu(adev, enable ?
  1252. PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
  1253. }
  1254. static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
  1255. {
  1256. return amdgpu_kv_notify_message_to_smu(adev, enable ?
  1257. PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
  1258. }
  1259. static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
  1260. {
  1261. struct kv_power_info *pi = kv_get_pi(adev);
  1262. struct amdgpu_uvd_clock_voltage_dependency_table *table =
  1263. &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
  1264. int ret;
  1265. u32 mask;
  1266. if (!gate) {
  1267. if (table->count)
  1268. pi->uvd_boot_level = table->count - 1;
  1269. else
  1270. pi->uvd_boot_level = 0;
  1271. if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
  1272. mask = 1 << pi->uvd_boot_level;
  1273. } else {
  1274. mask = 0x1f;
  1275. }
  1276. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1277. pi->dpm_table_start +
  1278. offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
  1279. (uint8_t *)&pi->uvd_boot_level,
  1280. sizeof(u8), pi->sram_end);
  1281. if (ret)
  1282. return ret;
  1283. amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  1284. PPSMC_MSG_UVDDPM_SetEnabledMask,
  1285. mask);
  1286. }
  1287. return kv_enable_uvd_dpm(adev, !gate);
  1288. }
  1289. static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
  1290. {
  1291. u8 i;
  1292. struct amdgpu_vce_clock_voltage_dependency_table *table =
  1293. &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
  1294. for (i = 0; i < table->count; i++) {
  1295. if (table->entries[i].evclk >= evclk)
  1296. break;
  1297. }
  1298. return i;
  1299. }
  1300. static int kv_update_vce_dpm(struct amdgpu_device *adev,
  1301. struct amdgpu_ps *amdgpu_new_state,
  1302. struct amdgpu_ps *amdgpu_current_state)
  1303. {
  1304. struct kv_power_info *pi = kv_get_pi(adev);
  1305. struct amdgpu_vce_clock_voltage_dependency_table *table =
  1306. &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
  1307. int ret;
  1308. if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
  1309. kv_dpm_powergate_vce(adev, false);
  1310. if (pi->caps_stable_p_state)
  1311. pi->vce_boot_level = table->count - 1;
  1312. else
  1313. pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
  1314. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1315. pi->dpm_table_start +
  1316. offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
  1317. (u8 *)&pi->vce_boot_level,
  1318. sizeof(u8),
  1319. pi->sram_end);
  1320. if (ret)
  1321. return ret;
  1322. if (pi->caps_stable_p_state)
  1323. amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  1324. PPSMC_MSG_VCEDPM_SetEnabledMask,
  1325. (1 << pi->vce_boot_level));
  1326. kv_enable_vce_dpm(adev, true);
  1327. } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
  1328. kv_enable_vce_dpm(adev, false);
  1329. kv_dpm_powergate_vce(adev, true);
  1330. }
  1331. return 0;
  1332. }
  1333. static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
  1334. {
  1335. struct kv_power_info *pi = kv_get_pi(adev);
  1336. struct amdgpu_clock_voltage_dependency_table *table =
  1337. &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
  1338. int ret;
  1339. if (!gate) {
  1340. if (pi->caps_stable_p_state)
  1341. pi->samu_boot_level = table->count - 1;
  1342. else
  1343. pi->samu_boot_level = 0;
  1344. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1345. pi->dpm_table_start +
  1346. offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
  1347. (u8 *)&pi->samu_boot_level,
  1348. sizeof(u8),
  1349. pi->sram_end);
  1350. if (ret)
  1351. return ret;
  1352. if (pi->caps_stable_p_state)
  1353. amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  1354. PPSMC_MSG_SAMUDPM_SetEnabledMask,
  1355. (1 << pi->samu_boot_level));
  1356. }
  1357. return kv_enable_samu_dpm(adev, !gate);
  1358. }
  1359. static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
  1360. {
  1361. u8 i;
  1362. struct amdgpu_clock_voltage_dependency_table *table =
  1363. &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
  1364. for (i = 0; i < table->count; i++) {
  1365. if (table->entries[i].clk >= 0) /* XXX */
  1366. break;
  1367. }
  1368. if (i >= table->count)
  1369. i = table->count - 1;
  1370. return i;
  1371. }
  1372. static void kv_update_acp_boot_level(struct amdgpu_device *adev)
  1373. {
  1374. struct kv_power_info *pi = kv_get_pi(adev);
  1375. u8 acp_boot_level;
  1376. if (!pi->caps_stable_p_state) {
  1377. acp_boot_level = kv_get_acp_boot_level(adev);
  1378. if (acp_boot_level != pi->acp_boot_level) {
  1379. pi->acp_boot_level = acp_boot_level;
  1380. amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  1381. PPSMC_MSG_ACPDPM_SetEnabledMask,
  1382. (1 << pi->acp_boot_level));
  1383. }
  1384. }
  1385. }
  1386. static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
  1387. {
  1388. struct kv_power_info *pi = kv_get_pi(adev);
  1389. struct amdgpu_clock_voltage_dependency_table *table =
  1390. &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
  1391. int ret;
  1392. if (!gate) {
  1393. if (pi->caps_stable_p_state)
  1394. pi->acp_boot_level = table->count - 1;
  1395. else
  1396. pi->acp_boot_level = kv_get_acp_boot_level(adev);
  1397. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1398. pi->dpm_table_start +
  1399. offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
  1400. (u8 *)&pi->acp_boot_level,
  1401. sizeof(u8),
  1402. pi->sram_end);
  1403. if (ret)
  1404. return ret;
  1405. if (pi->caps_stable_p_state)
  1406. amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  1407. PPSMC_MSG_ACPDPM_SetEnabledMask,
  1408. (1 << pi->acp_boot_level));
  1409. }
  1410. return kv_enable_acp_dpm(adev, !gate);
  1411. }
  1412. static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
  1413. {
  1414. struct kv_power_info *pi = kv_get_pi(adev);
  1415. int ret;
  1416. pi->uvd_power_gated = gate;
  1417. if (gate) {
  1418. /* stop the UVD block */
  1419. ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
  1420. AMD_PG_STATE_GATE);
  1421. kv_update_uvd_dpm(adev, gate);
  1422. if (pi->caps_uvd_pg)
  1423. /* power off the UVD block */
  1424. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
  1425. } else {
  1426. if (pi->caps_uvd_pg)
  1427. /* power on the UVD block */
  1428. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
  1429. /* re-init the UVD block */
  1430. kv_update_uvd_dpm(adev, gate);
  1431. ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
  1432. AMD_PG_STATE_UNGATE);
  1433. }
  1434. }
  1435. static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
  1436. {
  1437. struct kv_power_info *pi = kv_get_pi(adev);
  1438. if (pi->vce_power_gated == gate)
  1439. return;
  1440. pi->vce_power_gated = gate;
  1441. if (!pi->caps_vce_pg)
  1442. return;
  1443. if (gate)
  1444. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
  1445. else
  1446. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
  1447. }
  1448. static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
  1449. {
  1450. struct kv_power_info *pi = kv_get_pi(adev);
  1451. if (pi->samu_power_gated == gate)
  1452. return;
  1453. pi->samu_power_gated = gate;
  1454. if (gate) {
  1455. kv_update_samu_dpm(adev, true);
  1456. if (pi->caps_samu_pg)
  1457. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
  1458. } else {
  1459. if (pi->caps_samu_pg)
  1460. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
  1461. kv_update_samu_dpm(adev, false);
  1462. }
  1463. }
  1464. static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
  1465. {
  1466. struct kv_power_info *pi = kv_get_pi(adev);
  1467. if (pi->acp_power_gated == gate)
  1468. return;
  1469. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
  1470. return;
  1471. pi->acp_power_gated = gate;
  1472. if (gate) {
  1473. kv_update_acp_dpm(adev, true);
  1474. if (pi->caps_acp_pg)
  1475. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
  1476. } else {
  1477. if (pi->caps_acp_pg)
  1478. amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
  1479. kv_update_acp_dpm(adev, false);
  1480. }
  1481. }
  1482. static void kv_set_valid_clock_range(struct amdgpu_device *adev,
  1483. struct amdgpu_ps *new_rps)
  1484. {
  1485. struct kv_ps *new_ps = kv_get_ps(new_rps);
  1486. struct kv_power_info *pi = kv_get_pi(adev);
  1487. u32 i;
  1488. struct amdgpu_clock_voltage_dependency_table *table =
  1489. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  1490. if (table && table->count) {
  1491. for (i = 0; i < pi->graphics_dpm_level_count; i++) {
  1492. if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
  1493. (i == (pi->graphics_dpm_level_count - 1))) {
  1494. pi->lowest_valid = i;
  1495. break;
  1496. }
  1497. }
  1498. for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
  1499. if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
  1500. break;
  1501. }
  1502. pi->highest_valid = i;
  1503. if (pi->lowest_valid > pi->highest_valid) {
  1504. if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
  1505. (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
  1506. pi->highest_valid = pi->lowest_valid;
  1507. else
  1508. pi->lowest_valid = pi->highest_valid;
  1509. }
  1510. } else {
  1511. struct sumo_sclk_voltage_mapping_table *table =
  1512. &pi->sys_info.sclk_voltage_mapping_table;
  1513. for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
  1514. if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
  1515. i == (int)(pi->graphics_dpm_level_count - 1)) {
  1516. pi->lowest_valid = i;
  1517. break;
  1518. }
  1519. }
  1520. for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
  1521. if (table->entries[i].sclk_frequency <=
  1522. new_ps->levels[new_ps->num_levels - 1].sclk)
  1523. break;
  1524. }
  1525. pi->highest_valid = i;
  1526. if (pi->lowest_valid > pi->highest_valid) {
  1527. if ((new_ps->levels[0].sclk -
  1528. table->entries[pi->highest_valid].sclk_frequency) >
  1529. (table->entries[pi->lowest_valid].sclk_frequency -
  1530. new_ps->levels[new_ps->num_levels -1].sclk))
  1531. pi->highest_valid = pi->lowest_valid;
  1532. else
  1533. pi->lowest_valid = pi->highest_valid;
  1534. }
  1535. }
  1536. }
  1537. static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
  1538. struct amdgpu_ps *new_rps)
  1539. {
  1540. struct kv_ps *new_ps = kv_get_ps(new_rps);
  1541. struct kv_power_info *pi = kv_get_pi(adev);
  1542. int ret = 0;
  1543. u8 clk_bypass_cntl;
  1544. if (pi->caps_enable_dfs_bypass) {
  1545. clk_bypass_cntl = new_ps->need_dfs_bypass ?
  1546. pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
  1547. ret = amdgpu_kv_copy_bytes_to_smc(adev,
  1548. (pi->dpm_table_start +
  1549. offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
  1550. (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
  1551. offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
  1552. &clk_bypass_cntl,
  1553. sizeof(u8), pi->sram_end);
  1554. }
  1555. return ret;
  1556. }
  1557. static int kv_enable_nb_dpm(struct amdgpu_device *adev,
  1558. bool enable)
  1559. {
  1560. struct kv_power_info *pi = kv_get_pi(adev);
  1561. int ret = 0;
  1562. if (enable) {
  1563. if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
  1564. ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
  1565. if (ret == 0)
  1566. pi->nb_dpm_enabled = true;
  1567. }
  1568. } else {
  1569. if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
  1570. ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
  1571. if (ret == 0)
  1572. pi->nb_dpm_enabled = false;
  1573. }
  1574. }
  1575. return ret;
  1576. }
  1577. static int kv_dpm_force_performance_level(struct amdgpu_device *adev,
  1578. enum amd_dpm_forced_level level)
  1579. {
  1580. int ret;
  1581. if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
  1582. ret = kv_force_dpm_highest(adev);
  1583. if (ret)
  1584. return ret;
  1585. } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
  1586. ret = kv_force_dpm_lowest(adev);
  1587. if (ret)
  1588. return ret;
  1589. } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
  1590. ret = kv_unforce_levels(adev);
  1591. if (ret)
  1592. return ret;
  1593. }
  1594. adev->pm.dpm.forced_level = level;
  1595. return 0;
  1596. }
  1597. static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev)
  1598. {
  1599. struct kv_power_info *pi = kv_get_pi(adev);
  1600. struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
  1601. struct amdgpu_ps *new_ps = &requested_ps;
  1602. kv_update_requested_ps(adev, new_ps);
  1603. kv_apply_state_adjust_rules(adev,
  1604. &pi->requested_rps,
  1605. &pi->current_rps);
  1606. return 0;
  1607. }
  1608. static int kv_dpm_set_power_state(struct amdgpu_device *adev)
  1609. {
  1610. struct kv_power_info *pi = kv_get_pi(adev);
  1611. struct amdgpu_ps *new_ps = &pi->requested_rps;
  1612. struct amdgpu_ps *old_ps = &pi->current_rps;
  1613. int ret;
  1614. if (pi->bapm_enable) {
  1615. ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power);
  1616. if (ret) {
  1617. DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
  1618. return ret;
  1619. }
  1620. }
  1621. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
  1622. if (pi->enable_dpm) {
  1623. kv_set_valid_clock_range(adev, new_ps);
  1624. kv_update_dfs_bypass_settings(adev, new_ps);
  1625. ret = kv_calculate_ds_divider(adev);
  1626. if (ret) {
  1627. DRM_ERROR("kv_calculate_ds_divider failed\n");
  1628. return ret;
  1629. }
  1630. kv_calculate_nbps_level_settings(adev);
  1631. kv_calculate_dpm_settings(adev);
  1632. kv_force_lowest_valid(adev);
  1633. kv_enable_new_levels(adev);
  1634. kv_upload_dpm_settings(adev);
  1635. kv_program_nbps_index_settings(adev, new_ps);
  1636. kv_unforce_levels(adev);
  1637. kv_set_enabled_levels(adev);
  1638. kv_force_lowest_valid(adev);
  1639. kv_unforce_levels(adev);
  1640. ret = kv_update_vce_dpm(adev, new_ps, old_ps);
  1641. if (ret) {
  1642. DRM_ERROR("kv_update_vce_dpm failed\n");
  1643. return ret;
  1644. }
  1645. kv_update_sclk_t(adev);
  1646. if (adev->asic_type == CHIP_MULLINS)
  1647. kv_enable_nb_dpm(adev, true);
  1648. }
  1649. } else {
  1650. if (pi->enable_dpm) {
  1651. kv_set_valid_clock_range(adev, new_ps);
  1652. kv_update_dfs_bypass_settings(adev, new_ps);
  1653. ret = kv_calculate_ds_divider(adev);
  1654. if (ret) {
  1655. DRM_ERROR("kv_calculate_ds_divider failed\n");
  1656. return ret;
  1657. }
  1658. kv_calculate_nbps_level_settings(adev);
  1659. kv_calculate_dpm_settings(adev);
  1660. kv_freeze_sclk_dpm(adev, true);
  1661. kv_upload_dpm_settings(adev);
  1662. kv_program_nbps_index_settings(adev, new_ps);
  1663. kv_freeze_sclk_dpm(adev, false);
  1664. kv_set_enabled_levels(adev);
  1665. ret = kv_update_vce_dpm(adev, new_ps, old_ps);
  1666. if (ret) {
  1667. DRM_ERROR("kv_update_vce_dpm failed\n");
  1668. return ret;
  1669. }
  1670. kv_update_acp_boot_level(adev);
  1671. kv_update_sclk_t(adev);
  1672. kv_enable_nb_dpm(adev, true);
  1673. }
  1674. }
  1675. return 0;
  1676. }
  1677. static void kv_dpm_post_set_power_state(struct amdgpu_device *adev)
  1678. {
  1679. struct kv_power_info *pi = kv_get_pi(adev);
  1680. struct amdgpu_ps *new_ps = &pi->requested_rps;
  1681. kv_update_current_ps(adev, new_ps);
  1682. }
  1683. static void kv_dpm_setup_asic(struct amdgpu_device *adev)
  1684. {
  1685. sumo_take_smu_control(adev, true);
  1686. kv_init_powergate_state(adev);
  1687. kv_init_sclk_t(adev);
  1688. }
  1689. #if 0
  1690. static void kv_dpm_reset_asic(struct amdgpu_device *adev)
  1691. {
  1692. struct kv_power_info *pi = kv_get_pi(adev);
  1693. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
  1694. kv_force_lowest_valid(adev);
  1695. kv_init_graphics_levels(adev);
  1696. kv_program_bootup_state(adev);
  1697. kv_upload_dpm_settings(adev);
  1698. kv_force_lowest_valid(adev);
  1699. kv_unforce_levels(adev);
  1700. } else {
  1701. kv_init_graphics_levels(adev);
  1702. kv_program_bootup_state(adev);
  1703. kv_freeze_sclk_dpm(adev, true);
  1704. kv_upload_dpm_settings(adev);
  1705. kv_freeze_sclk_dpm(adev, false);
  1706. kv_set_enabled_level(adev, pi->graphics_boot_level);
  1707. }
  1708. }
  1709. #endif
  1710. static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
  1711. struct amdgpu_clock_and_voltage_limits *table)
  1712. {
  1713. struct kv_power_info *pi = kv_get_pi(adev);
  1714. if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
  1715. int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
  1716. table->sclk =
  1717. pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
  1718. table->vddc =
  1719. kv_convert_2bit_index_to_voltage(adev,
  1720. pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
  1721. }
  1722. table->mclk = pi->sys_info.nbp_memory_clock[0];
  1723. }
  1724. static void kv_patch_voltage_values(struct amdgpu_device *adev)
  1725. {
  1726. int i;
  1727. struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
  1728. &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
  1729. struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
  1730. &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
  1731. struct amdgpu_clock_voltage_dependency_table *samu_table =
  1732. &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
  1733. struct amdgpu_clock_voltage_dependency_table *acp_table =
  1734. &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
  1735. if (uvd_table->count) {
  1736. for (i = 0; i < uvd_table->count; i++)
  1737. uvd_table->entries[i].v =
  1738. kv_convert_8bit_index_to_voltage(adev,
  1739. uvd_table->entries[i].v);
  1740. }
  1741. if (vce_table->count) {
  1742. for (i = 0; i < vce_table->count; i++)
  1743. vce_table->entries[i].v =
  1744. kv_convert_8bit_index_to_voltage(adev,
  1745. vce_table->entries[i].v);
  1746. }
  1747. if (samu_table->count) {
  1748. for (i = 0; i < samu_table->count; i++)
  1749. samu_table->entries[i].v =
  1750. kv_convert_8bit_index_to_voltage(adev,
  1751. samu_table->entries[i].v);
  1752. }
  1753. if (acp_table->count) {
  1754. for (i = 0; i < acp_table->count; i++)
  1755. acp_table->entries[i].v =
  1756. kv_convert_8bit_index_to_voltage(adev,
  1757. acp_table->entries[i].v);
  1758. }
  1759. }
  1760. static void kv_construct_boot_state(struct amdgpu_device *adev)
  1761. {
  1762. struct kv_power_info *pi = kv_get_pi(adev);
  1763. pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
  1764. pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
  1765. pi->boot_pl.ds_divider_index = 0;
  1766. pi->boot_pl.ss_divider_index = 0;
  1767. pi->boot_pl.allow_gnb_slow = 1;
  1768. pi->boot_pl.force_nbp_state = 0;
  1769. pi->boot_pl.display_wm = 0;
  1770. pi->boot_pl.vce_wm = 0;
  1771. }
  1772. static int kv_force_dpm_highest(struct amdgpu_device *adev)
  1773. {
  1774. int ret;
  1775. u32 enable_mask, i;
  1776. ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
  1777. if (ret)
  1778. return ret;
  1779. for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
  1780. if (enable_mask & (1 << i))
  1781. break;
  1782. }
  1783. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
  1784. return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
  1785. else
  1786. return kv_set_enabled_level(adev, i);
  1787. }
  1788. static int kv_force_dpm_lowest(struct amdgpu_device *adev)
  1789. {
  1790. int ret;
  1791. u32 enable_mask, i;
  1792. ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
  1793. if (ret)
  1794. return ret;
  1795. for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
  1796. if (enable_mask & (1 << i))
  1797. break;
  1798. }
  1799. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
  1800. return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
  1801. else
  1802. return kv_set_enabled_level(adev, i);
  1803. }
  1804. static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
  1805. u32 sclk, u32 min_sclk_in_sr)
  1806. {
  1807. struct kv_power_info *pi = kv_get_pi(adev);
  1808. u32 i;
  1809. u32 temp;
  1810. u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
  1811. if (sclk < min)
  1812. return 0;
  1813. if (!pi->caps_sclk_ds)
  1814. return 0;
  1815. for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
  1816. temp = sclk >> i;
  1817. if (temp >= min)
  1818. break;
  1819. }
  1820. return (u8)i;
  1821. }
  1822. static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
  1823. {
  1824. struct kv_power_info *pi = kv_get_pi(adev);
  1825. struct amdgpu_clock_voltage_dependency_table *table =
  1826. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  1827. int i;
  1828. if (table && table->count) {
  1829. for (i = table->count - 1; i >= 0; i--) {
  1830. if (pi->high_voltage_t &&
  1831. (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
  1832. pi->high_voltage_t)) {
  1833. *limit = i;
  1834. return 0;
  1835. }
  1836. }
  1837. } else {
  1838. struct sumo_sclk_voltage_mapping_table *table =
  1839. &pi->sys_info.sclk_voltage_mapping_table;
  1840. for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
  1841. if (pi->high_voltage_t &&
  1842. (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
  1843. pi->high_voltage_t)) {
  1844. *limit = i;
  1845. return 0;
  1846. }
  1847. }
  1848. }
  1849. *limit = 0;
  1850. return 0;
  1851. }
  1852. static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
  1853. struct amdgpu_ps *new_rps,
  1854. struct amdgpu_ps *old_rps)
  1855. {
  1856. struct kv_ps *ps = kv_get_ps(new_rps);
  1857. struct kv_power_info *pi = kv_get_pi(adev);
  1858. u32 min_sclk = 10000; /* ??? */
  1859. u32 sclk, mclk = 0;
  1860. int i, limit;
  1861. bool force_high;
  1862. struct amdgpu_clock_voltage_dependency_table *table =
  1863. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  1864. u32 stable_p_state_sclk = 0;
  1865. struct amdgpu_clock_and_voltage_limits *max_limits =
  1866. &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  1867. if (new_rps->vce_active) {
  1868. new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
  1869. new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
  1870. } else {
  1871. new_rps->evclk = 0;
  1872. new_rps->ecclk = 0;
  1873. }
  1874. mclk = max_limits->mclk;
  1875. sclk = min_sclk;
  1876. if (pi->caps_stable_p_state) {
  1877. stable_p_state_sclk = (max_limits->sclk * 75) / 100;
  1878. for (i = table->count - 1; i >= 0; i--) {
  1879. if (stable_p_state_sclk >= table->entries[i].clk) {
  1880. stable_p_state_sclk = table->entries[i].clk;
  1881. break;
  1882. }
  1883. }
  1884. if (i > 0)
  1885. stable_p_state_sclk = table->entries[0].clk;
  1886. sclk = stable_p_state_sclk;
  1887. }
  1888. if (new_rps->vce_active) {
  1889. if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
  1890. sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
  1891. }
  1892. ps->need_dfs_bypass = true;
  1893. for (i = 0; i < ps->num_levels; i++) {
  1894. if (ps->levels[i].sclk < sclk)
  1895. ps->levels[i].sclk = sclk;
  1896. }
  1897. if (table && table->count) {
  1898. for (i = 0; i < ps->num_levels; i++) {
  1899. if (pi->high_voltage_t &&
  1900. (pi->high_voltage_t <
  1901. kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
  1902. kv_get_high_voltage_limit(adev, &limit);
  1903. ps->levels[i].sclk = table->entries[limit].clk;
  1904. }
  1905. }
  1906. } else {
  1907. struct sumo_sclk_voltage_mapping_table *table =
  1908. &pi->sys_info.sclk_voltage_mapping_table;
  1909. for (i = 0; i < ps->num_levels; i++) {
  1910. if (pi->high_voltage_t &&
  1911. (pi->high_voltage_t <
  1912. kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
  1913. kv_get_high_voltage_limit(adev, &limit);
  1914. ps->levels[i].sclk = table->entries[limit].sclk_frequency;
  1915. }
  1916. }
  1917. }
  1918. if (pi->caps_stable_p_state) {
  1919. for (i = 0; i < ps->num_levels; i++) {
  1920. ps->levels[i].sclk = stable_p_state_sclk;
  1921. }
  1922. }
  1923. pi->video_start = new_rps->dclk || new_rps->vclk ||
  1924. new_rps->evclk || new_rps->ecclk;
  1925. if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
  1926. ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
  1927. pi->battery_state = true;
  1928. else
  1929. pi->battery_state = false;
  1930. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
  1931. ps->dpm0_pg_nb_ps_lo = 0x1;
  1932. ps->dpm0_pg_nb_ps_hi = 0x0;
  1933. ps->dpmx_nb_ps_lo = 0x1;
  1934. ps->dpmx_nb_ps_hi = 0x0;
  1935. } else {
  1936. ps->dpm0_pg_nb_ps_lo = 0x3;
  1937. ps->dpm0_pg_nb_ps_hi = 0x0;
  1938. ps->dpmx_nb_ps_lo = 0x3;
  1939. ps->dpmx_nb_ps_hi = 0x0;
  1940. if (pi->sys_info.nb_dpm_enable) {
  1941. force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
  1942. pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
  1943. pi->disable_nb_ps3_in_battery;
  1944. ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
  1945. ps->dpm0_pg_nb_ps_hi = 0x2;
  1946. ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
  1947. ps->dpmx_nb_ps_hi = 0x2;
  1948. }
  1949. }
  1950. }
  1951. static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
  1952. u32 index, bool enable)
  1953. {
  1954. struct kv_power_info *pi = kv_get_pi(adev);
  1955. pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
  1956. }
  1957. static int kv_calculate_ds_divider(struct amdgpu_device *adev)
  1958. {
  1959. struct kv_power_info *pi = kv_get_pi(adev);
  1960. u32 sclk_in_sr = 10000; /* ??? */
  1961. u32 i;
  1962. if (pi->lowest_valid > pi->highest_valid)
  1963. return -EINVAL;
  1964. for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
  1965. pi->graphics_level[i].DeepSleepDivId =
  1966. kv_get_sleep_divider_id_from_clock(adev,
  1967. be32_to_cpu(pi->graphics_level[i].SclkFrequency),
  1968. sclk_in_sr);
  1969. }
  1970. return 0;
  1971. }
  1972. static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
  1973. {
  1974. struct kv_power_info *pi = kv_get_pi(adev);
  1975. u32 i;
  1976. bool force_high;
  1977. struct amdgpu_clock_and_voltage_limits *max_limits =
  1978. &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  1979. u32 mclk = max_limits->mclk;
  1980. if (pi->lowest_valid > pi->highest_valid)
  1981. return -EINVAL;
  1982. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
  1983. for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
  1984. pi->graphics_level[i].GnbSlow = 1;
  1985. pi->graphics_level[i].ForceNbPs1 = 0;
  1986. pi->graphics_level[i].UpH = 0;
  1987. }
  1988. if (!pi->sys_info.nb_dpm_enable)
  1989. return 0;
  1990. force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
  1991. (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
  1992. if (force_high) {
  1993. for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
  1994. pi->graphics_level[i].GnbSlow = 0;
  1995. } else {
  1996. if (pi->battery_state)
  1997. pi->graphics_level[0].ForceNbPs1 = 1;
  1998. pi->graphics_level[1].GnbSlow = 0;
  1999. pi->graphics_level[2].GnbSlow = 0;
  2000. pi->graphics_level[3].GnbSlow = 0;
  2001. pi->graphics_level[4].GnbSlow = 0;
  2002. }
  2003. } else {
  2004. for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
  2005. pi->graphics_level[i].GnbSlow = 1;
  2006. pi->graphics_level[i].ForceNbPs1 = 0;
  2007. pi->graphics_level[i].UpH = 0;
  2008. }
  2009. if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
  2010. pi->graphics_level[pi->lowest_valid].UpH = 0x28;
  2011. pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
  2012. if (pi->lowest_valid != pi->highest_valid)
  2013. pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
  2014. }
  2015. }
  2016. return 0;
  2017. }
  2018. static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
  2019. {
  2020. struct kv_power_info *pi = kv_get_pi(adev);
  2021. u32 i;
  2022. if (pi->lowest_valid > pi->highest_valid)
  2023. return -EINVAL;
  2024. for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
  2025. pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
  2026. return 0;
  2027. }
  2028. static void kv_init_graphics_levels(struct amdgpu_device *adev)
  2029. {
  2030. struct kv_power_info *pi = kv_get_pi(adev);
  2031. u32 i;
  2032. struct amdgpu_clock_voltage_dependency_table *table =
  2033. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  2034. if (table && table->count) {
  2035. u32 vid_2bit;
  2036. pi->graphics_dpm_level_count = 0;
  2037. for (i = 0; i < table->count; i++) {
  2038. if (pi->high_voltage_t &&
  2039. (pi->high_voltage_t <
  2040. kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
  2041. break;
  2042. kv_set_divider_value(adev, i, table->entries[i].clk);
  2043. vid_2bit = kv_convert_vid7_to_vid2(adev,
  2044. &pi->sys_info.vid_mapping_table,
  2045. table->entries[i].v);
  2046. kv_set_vid(adev, i, vid_2bit);
  2047. kv_set_at(adev, i, pi->at[i]);
  2048. kv_dpm_power_level_enabled_for_throttle(adev, i, true);
  2049. pi->graphics_dpm_level_count++;
  2050. }
  2051. } else {
  2052. struct sumo_sclk_voltage_mapping_table *table =
  2053. &pi->sys_info.sclk_voltage_mapping_table;
  2054. pi->graphics_dpm_level_count = 0;
  2055. for (i = 0; i < table->num_max_dpm_entries; i++) {
  2056. if (pi->high_voltage_t &&
  2057. pi->high_voltage_t <
  2058. kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
  2059. break;
  2060. kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
  2061. kv_set_vid(adev, i, table->entries[i].vid_2bit);
  2062. kv_set_at(adev, i, pi->at[i]);
  2063. kv_dpm_power_level_enabled_for_throttle(adev, i, true);
  2064. pi->graphics_dpm_level_count++;
  2065. }
  2066. }
  2067. for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
  2068. kv_dpm_power_level_enable(adev, i, false);
  2069. }
  2070. static void kv_enable_new_levels(struct amdgpu_device *adev)
  2071. {
  2072. struct kv_power_info *pi = kv_get_pi(adev);
  2073. u32 i;
  2074. for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
  2075. if (i >= pi->lowest_valid && i <= pi->highest_valid)
  2076. kv_dpm_power_level_enable(adev, i, true);
  2077. }
  2078. }
  2079. static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
  2080. {
  2081. u32 new_mask = (1 << level);
  2082. return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  2083. PPSMC_MSG_SCLKDPM_SetEnabledMask,
  2084. new_mask);
  2085. }
  2086. static int kv_set_enabled_levels(struct amdgpu_device *adev)
  2087. {
  2088. struct kv_power_info *pi = kv_get_pi(adev);
  2089. u32 i, new_mask = 0;
  2090. for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
  2091. new_mask |= (1 << i);
  2092. return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
  2093. PPSMC_MSG_SCLKDPM_SetEnabledMask,
  2094. new_mask);
  2095. }
  2096. static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
  2097. struct amdgpu_ps *new_rps)
  2098. {
  2099. struct kv_ps *new_ps = kv_get_ps(new_rps);
  2100. struct kv_power_info *pi = kv_get_pi(adev);
  2101. u32 nbdpmconfig1;
  2102. if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
  2103. return;
  2104. if (pi->sys_info.nb_dpm_enable) {
  2105. nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
  2106. nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
  2107. NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
  2108. NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
  2109. NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
  2110. nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
  2111. (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
  2112. (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
  2113. (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
  2114. WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
  2115. }
  2116. }
  2117. static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
  2118. int min_temp, int max_temp)
  2119. {
  2120. int low_temp = 0 * 1000;
  2121. int high_temp = 255 * 1000;
  2122. u32 tmp;
  2123. if (low_temp < min_temp)
  2124. low_temp = min_temp;
  2125. if (high_temp > max_temp)
  2126. high_temp = max_temp;
  2127. if (high_temp < low_temp) {
  2128. DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
  2129. return -EINVAL;
  2130. }
  2131. tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
  2132. tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
  2133. CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
  2134. tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
  2135. ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
  2136. WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
  2137. adev->pm.dpm.thermal.min_temp = low_temp;
  2138. adev->pm.dpm.thermal.max_temp = high_temp;
  2139. return 0;
  2140. }
  2141. union igp_info {
  2142. struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  2143. struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
  2144. struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
  2145. struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
  2146. struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
  2147. struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
  2148. };
  2149. static int kv_parse_sys_info_table(struct amdgpu_device *adev)
  2150. {
  2151. struct kv_power_info *pi = kv_get_pi(adev);
  2152. struct amdgpu_mode_info *mode_info = &adev->mode_info;
  2153. int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  2154. union igp_info *igp_info;
  2155. u8 frev, crev;
  2156. u16 data_offset;
  2157. int i;
  2158. if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
  2159. &frev, &crev, &data_offset)) {
  2160. igp_info = (union igp_info *)(mode_info->atom_context->bios +
  2161. data_offset);
  2162. if (crev != 8) {
  2163. DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
  2164. return -EINVAL;
  2165. }
  2166. pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
  2167. pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
  2168. pi->sys_info.bootup_nb_voltage_index =
  2169. le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
  2170. if (igp_info->info_8.ucHtcTmpLmt == 0)
  2171. pi->sys_info.htc_tmp_lmt = 203;
  2172. else
  2173. pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
  2174. if (igp_info->info_8.ucHtcHystLmt == 0)
  2175. pi->sys_info.htc_hyst_lmt = 5;
  2176. else
  2177. pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
  2178. if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
  2179. DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
  2180. }
  2181. if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
  2182. pi->sys_info.nb_dpm_enable = true;
  2183. else
  2184. pi->sys_info.nb_dpm_enable = false;
  2185. for (i = 0; i < KV_NUM_NBPSTATES; i++) {
  2186. pi->sys_info.nbp_memory_clock[i] =
  2187. le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
  2188. pi->sys_info.nbp_n_clock[i] =
  2189. le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
  2190. }
  2191. if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
  2192. SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
  2193. pi->caps_enable_dfs_bypass = true;
  2194. sumo_construct_sclk_voltage_mapping_table(adev,
  2195. &pi->sys_info.sclk_voltage_mapping_table,
  2196. igp_info->info_8.sAvail_SCLK);
  2197. sumo_construct_vid_mapping_table(adev,
  2198. &pi->sys_info.vid_mapping_table,
  2199. igp_info->info_8.sAvail_SCLK);
  2200. kv_construct_max_power_limits_table(adev,
  2201. &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
  2202. }
  2203. return 0;
  2204. }
  2205. union power_info {
  2206. struct _ATOM_POWERPLAY_INFO info;
  2207. struct _ATOM_POWERPLAY_INFO_V2 info_2;
  2208. struct _ATOM_POWERPLAY_INFO_V3 info_3;
  2209. struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  2210. struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  2211. struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  2212. };
  2213. union pplib_clock_info {
  2214. struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  2215. struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  2216. struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  2217. struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  2218. };
  2219. union pplib_power_state {
  2220. struct _ATOM_PPLIB_STATE v1;
  2221. struct _ATOM_PPLIB_STATE_V2 v2;
  2222. };
  2223. static void kv_patch_boot_state(struct amdgpu_device *adev,
  2224. struct kv_ps *ps)
  2225. {
  2226. struct kv_power_info *pi = kv_get_pi(adev);
  2227. ps->num_levels = 1;
  2228. ps->levels[0] = pi->boot_pl;
  2229. }
  2230. static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
  2231. struct amdgpu_ps *rps,
  2232. struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
  2233. u8 table_rev)
  2234. {
  2235. struct kv_ps *ps = kv_get_ps(rps);
  2236. rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
  2237. rps->class = le16_to_cpu(non_clock_info->usClassification);
  2238. rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
  2239. if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
  2240. rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
  2241. rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
  2242. } else {
  2243. rps->vclk = 0;
  2244. rps->dclk = 0;
  2245. }
  2246. if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
  2247. adev->pm.dpm.boot_ps = rps;
  2248. kv_patch_boot_state(adev, ps);
  2249. }
  2250. if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
  2251. adev->pm.dpm.uvd_ps = rps;
  2252. }
  2253. static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
  2254. struct amdgpu_ps *rps, int index,
  2255. union pplib_clock_info *clock_info)
  2256. {
  2257. struct kv_power_info *pi = kv_get_pi(adev);
  2258. struct kv_ps *ps = kv_get_ps(rps);
  2259. struct kv_pl *pl = &ps->levels[index];
  2260. u32 sclk;
  2261. sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
  2262. sclk |= clock_info->sumo.ucEngineClockHigh << 16;
  2263. pl->sclk = sclk;
  2264. pl->vddc_index = clock_info->sumo.vddcIndex;
  2265. ps->num_levels = index + 1;
  2266. if (pi->caps_sclk_ds) {
  2267. pl->ds_divider_index = 5;
  2268. pl->ss_divider_index = 5;
  2269. }
  2270. }
  2271. static int kv_parse_power_table(struct amdgpu_device *adev)
  2272. {
  2273. struct amdgpu_mode_info *mode_info = &adev->mode_info;
  2274. struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
  2275. union pplib_power_state *power_state;
  2276. int i, j, k, non_clock_array_index, clock_array_index;
  2277. union pplib_clock_info *clock_info;
  2278. struct _StateArray *state_array;
  2279. struct _ClockInfoArray *clock_info_array;
  2280. struct _NonClockInfoArray *non_clock_info_array;
  2281. union power_info *power_info;
  2282. int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
  2283. u16 data_offset;
  2284. u8 frev, crev;
  2285. u8 *power_state_offset;
  2286. struct kv_ps *ps;
  2287. if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
  2288. &frev, &crev, &data_offset))
  2289. return -EINVAL;
  2290. power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
  2291. amdgpu_add_thermal_controller(adev);
  2292. state_array = (struct _StateArray *)
  2293. (mode_info->atom_context->bios + data_offset +
  2294. le16_to_cpu(power_info->pplib.usStateArrayOffset));
  2295. clock_info_array = (struct _ClockInfoArray *)
  2296. (mode_info->atom_context->bios + data_offset +
  2297. le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
  2298. non_clock_info_array = (struct _NonClockInfoArray *)
  2299. (mode_info->atom_context->bios + data_offset +
  2300. le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
  2301. adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
  2302. state_array->ucNumEntries, GFP_KERNEL);
  2303. if (!adev->pm.dpm.ps)
  2304. return -ENOMEM;
  2305. power_state_offset = (u8 *)state_array->states;
  2306. for (i = 0; i < state_array->ucNumEntries; i++) {
  2307. u8 *idx;
  2308. power_state = (union pplib_power_state *)power_state_offset;
  2309. non_clock_array_index = power_state->v2.nonClockInfoIndex;
  2310. non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
  2311. &non_clock_info_array->nonClockInfo[non_clock_array_index];
  2312. ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
  2313. if (ps == NULL) {
  2314. kfree(adev->pm.dpm.ps);
  2315. return -ENOMEM;
  2316. }
  2317. adev->pm.dpm.ps[i].ps_priv = ps;
  2318. k = 0;
  2319. idx = (u8 *)&power_state->v2.clockInfoIndex[0];
  2320. for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
  2321. clock_array_index = idx[j];
  2322. if (clock_array_index >= clock_info_array->ucNumEntries)
  2323. continue;
  2324. if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
  2325. break;
  2326. clock_info = (union pplib_clock_info *)
  2327. ((u8 *)&clock_info_array->clockInfo[0] +
  2328. (clock_array_index * clock_info_array->ucEntrySize));
  2329. kv_parse_pplib_clock_info(adev,
  2330. &adev->pm.dpm.ps[i], k,
  2331. clock_info);
  2332. k++;
  2333. }
  2334. kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
  2335. non_clock_info,
  2336. non_clock_info_array->ucEntrySize);
  2337. power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
  2338. }
  2339. adev->pm.dpm.num_ps = state_array->ucNumEntries;
  2340. /* fill in the vce power states */
  2341. for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
  2342. u32 sclk;
  2343. clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
  2344. clock_info = (union pplib_clock_info *)
  2345. &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
  2346. sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
  2347. sclk |= clock_info->sumo.ucEngineClockHigh << 16;
  2348. adev->pm.dpm.vce_states[i].sclk = sclk;
  2349. adev->pm.dpm.vce_states[i].mclk = 0;
  2350. }
  2351. return 0;
  2352. }
  2353. static int kv_dpm_init(struct amdgpu_device *adev)
  2354. {
  2355. struct kv_power_info *pi;
  2356. int ret, i;
  2357. pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
  2358. if (pi == NULL)
  2359. return -ENOMEM;
  2360. adev->pm.dpm.priv = pi;
  2361. ret = amdgpu_get_platform_caps(adev);
  2362. if (ret)
  2363. return ret;
  2364. ret = amdgpu_parse_extended_power_table(adev);
  2365. if (ret)
  2366. return ret;
  2367. for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
  2368. pi->at[i] = TRINITY_AT_DFLT;
  2369. pi->sram_end = SMC_RAM_END;
  2370. pi->enable_nb_dpm = true;
  2371. pi->caps_power_containment = true;
  2372. pi->caps_cac = true;
  2373. pi->enable_didt = false;
  2374. if (pi->enable_didt) {
  2375. pi->caps_sq_ramping = true;
  2376. pi->caps_db_ramping = true;
  2377. pi->caps_td_ramping = true;
  2378. pi->caps_tcp_ramping = true;
  2379. }
  2380. if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
  2381. pi->caps_sclk_ds = true;
  2382. else
  2383. pi->caps_sclk_ds = false;
  2384. pi->enable_auto_thermal_throttling = true;
  2385. pi->disable_nb_ps3_in_battery = false;
  2386. if (amdgpu_bapm == 0)
  2387. pi->bapm_enable = false;
  2388. else
  2389. pi->bapm_enable = true;
  2390. pi->voltage_drop_t = 0;
  2391. pi->caps_sclk_throttle_low_notification = false;
  2392. pi->caps_fps = false; /* true? */
  2393. pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
  2394. pi->caps_uvd_dpm = true;
  2395. pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
  2396. pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
  2397. pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
  2398. pi->caps_stable_p_state = false;
  2399. ret = kv_parse_sys_info_table(adev);
  2400. if (ret)
  2401. return ret;
  2402. kv_patch_voltage_values(adev);
  2403. kv_construct_boot_state(adev);
  2404. ret = kv_parse_power_table(adev);
  2405. if (ret)
  2406. return ret;
  2407. pi->enable_dpm = true;
  2408. return 0;
  2409. }
  2410. static void
  2411. kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
  2412. struct seq_file *m)
  2413. {
  2414. struct kv_power_info *pi = kv_get_pi(adev);
  2415. u32 current_index =
  2416. (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
  2417. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
  2418. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
  2419. u32 sclk, tmp;
  2420. u16 vddc;
  2421. if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
  2422. seq_printf(m, "invalid dpm profile %d\n", current_index);
  2423. } else {
  2424. sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
  2425. tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
  2426. SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
  2427. SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
  2428. vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
  2429. seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
  2430. seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
  2431. seq_printf(m, "power level %d sclk: %u vddc: %u\n",
  2432. current_index, sclk, vddc);
  2433. }
  2434. }
  2435. static void
  2436. kv_dpm_print_power_state(struct amdgpu_device *adev,
  2437. struct amdgpu_ps *rps)
  2438. {
  2439. int i;
  2440. struct kv_ps *ps = kv_get_ps(rps);
  2441. amdgpu_dpm_print_class_info(rps->class, rps->class2);
  2442. amdgpu_dpm_print_cap_info(rps->caps);
  2443. printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
  2444. for (i = 0; i < ps->num_levels; i++) {
  2445. struct kv_pl *pl = &ps->levels[i];
  2446. printk("\t\tpower level %d sclk: %u vddc: %u\n",
  2447. i, pl->sclk,
  2448. kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
  2449. }
  2450. amdgpu_dpm_print_ps_status(adev, rps);
  2451. }
  2452. static void kv_dpm_fini(struct amdgpu_device *adev)
  2453. {
  2454. int i;
  2455. for (i = 0; i < adev->pm.dpm.num_ps; i++) {
  2456. kfree(adev->pm.dpm.ps[i].ps_priv);
  2457. }
  2458. kfree(adev->pm.dpm.ps);
  2459. kfree(adev->pm.dpm.priv);
  2460. amdgpu_free_extended_power_table(adev);
  2461. }
  2462. static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev)
  2463. {
  2464. }
  2465. static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low)
  2466. {
  2467. struct kv_power_info *pi = kv_get_pi(adev);
  2468. struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
  2469. if (low)
  2470. return requested_state->levels[0].sclk;
  2471. else
  2472. return requested_state->levels[requested_state->num_levels - 1].sclk;
  2473. }
  2474. static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low)
  2475. {
  2476. struct kv_power_info *pi = kv_get_pi(adev);
  2477. return pi->sys_info.bootup_uma_clk;
  2478. }
  2479. /* get temperature in millidegrees */
  2480. static int kv_dpm_get_temp(struct amdgpu_device *adev)
  2481. {
  2482. u32 temp;
  2483. int actual_temp = 0;
  2484. temp = RREG32_SMC(0xC0300E0C);
  2485. if (temp)
  2486. actual_temp = (temp / 8) - 49;
  2487. else
  2488. actual_temp = 0;
  2489. actual_temp = actual_temp * 1000;
  2490. return actual_temp;
  2491. }
  2492. static int kv_dpm_early_init(void *handle)
  2493. {
  2494. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2495. kv_dpm_set_dpm_funcs(adev);
  2496. kv_dpm_set_irq_funcs(adev);
  2497. return 0;
  2498. }
  2499. static int kv_dpm_late_init(void *handle)
  2500. {
  2501. /* powerdown unused blocks for now */
  2502. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2503. int ret;
  2504. if (!amdgpu_dpm)
  2505. return 0;
  2506. /* init the sysfs and debugfs files late */
  2507. ret = amdgpu_pm_sysfs_init(adev);
  2508. if (ret)
  2509. return ret;
  2510. kv_dpm_powergate_acp(adev, true);
  2511. kv_dpm_powergate_samu(adev, true);
  2512. return 0;
  2513. }
  2514. static int kv_dpm_sw_init(void *handle)
  2515. {
  2516. int ret;
  2517. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2518. ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
  2519. &adev->pm.dpm.thermal.irq);
  2520. if (ret)
  2521. return ret;
  2522. ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
  2523. &adev->pm.dpm.thermal.irq);
  2524. if (ret)
  2525. return ret;
  2526. /* default to balanced state */
  2527. adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
  2528. adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
  2529. adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
  2530. adev->pm.default_sclk = adev->clock.default_sclk;
  2531. adev->pm.default_mclk = adev->clock.default_mclk;
  2532. adev->pm.current_sclk = adev->clock.default_sclk;
  2533. adev->pm.current_mclk = adev->clock.default_mclk;
  2534. adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
  2535. if (amdgpu_dpm == 0)
  2536. return 0;
  2537. INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
  2538. mutex_lock(&adev->pm.mutex);
  2539. ret = kv_dpm_init(adev);
  2540. if (ret)
  2541. goto dpm_failed;
  2542. adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
  2543. if (amdgpu_dpm == 1)
  2544. amdgpu_pm_print_power_states(adev);
  2545. mutex_unlock(&adev->pm.mutex);
  2546. DRM_INFO("amdgpu: dpm initialized\n");
  2547. return 0;
  2548. dpm_failed:
  2549. kv_dpm_fini(adev);
  2550. mutex_unlock(&adev->pm.mutex);
  2551. DRM_ERROR("amdgpu: dpm initialization failed\n");
  2552. return ret;
  2553. }
  2554. static int kv_dpm_sw_fini(void *handle)
  2555. {
  2556. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2557. flush_work(&adev->pm.dpm.thermal.work);
  2558. mutex_lock(&adev->pm.mutex);
  2559. amdgpu_pm_sysfs_fini(adev);
  2560. kv_dpm_fini(adev);
  2561. mutex_unlock(&adev->pm.mutex);
  2562. return 0;
  2563. }
  2564. static int kv_dpm_hw_init(void *handle)
  2565. {
  2566. int ret;
  2567. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2568. if (!amdgpu_dpm)
  2569. return 0;
  2570. mutex_lock(&adev->pm.mutex);
  2571. kv_dpm_setup_asic(adev);
  2572. ret = kv_dpm_enable(adev);
  2573. if (ret)
  2574. adev->pm.dpm_enabled = false;
  2575. else
  2576. adev->pm.dpm_enabled = true;
  2577. mutex_unlock(&adev->pm.mutex);
  2578. amdgpu_pm_compute_clocks(adev);
  2579. return ret;
  2580. }
  2581. static int kv_dpm_hw_fini(void *handle)
  2582. {
  2583. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2584. if (adev->pm.dpm_enabled) {
  2585. mutex_lock(&adev->pm.mutex);
  2586. kv_dpm_disable(adev);
  2587. mutex_unlock(&adev->pm.mutex);
  2588. }
  2589. return 0;
  2590. }
  2591. static int kv_dpm_suspend(void *handle)
  2592. {
  2593. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2594. if (adev->pm.dpm_enabled) {
  2595. mutex_lock(&adev->pm.mutex);
  2596. /* disable dpm */
  2597. kv_dpm_disable(adev);
  2598. /* reset the power state */
  2599. adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
  2600. mutex_unlock(&adev->pm.mutex);
  2601. }
  2602. return 0;
  2603. }
  2604. static int kv_dpm_resume(void *handle)
  2605. {
  2606. int ret;
  2607. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2608. if (adev->pm.dpm_enabled) {
  2609. /* asic init will reset to the boot state */
  2610. mutex_lock(&adev->pm.mutex);
  2611. kv_dpm_setup_asic(adev);
  2612. ret = kv_dpm_enable(adev);
  2613. if (ret)
  2614. adev->pm.dpm_enabled = false;
  2615. else
  2616. adev->pm.dpm_enabled = true;
  2617. mutex_unlock(&adev->pm.mutex);
  2618. if (adev->pm.dpm_enabled)
  2619. amdgpu_pm_compute_clocks(adev);
  2620. }
  2621. return 0;
  2622. }
  2623. static bool kv_dpm_is_idle(void *handle)
  2624. {
  2625. return true;
  2626. }
  2627. static int kv_dpm_wait_for_idle(void *handle)
  2628. {
  2629. return 0;
  2630. }
  2631. static int kv_dpm_soft_reset(void *handle)
  2632. {
  2633. return 0;
  2634. }
  2635. static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
  2636. struct amdgpu_irq_src *src,
  2637. unsigned type,
  2638. enum amdgpu_interrupt_state state)
  2639. {
  2640. u32 cg_thermal_int;
  2641. switch (type) {
  2642. case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
  2643. switch (state) {
  2644. case AMDGPU_IRQ_STATE_DISABLE:
  2645. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
  2646. cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
  2647. WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
  2648. break;
  2649. case AMDGPU_IRQ_STATE_ENABLE:
  2650. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
  2651. cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
  2652. WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
  2653. break;
  2654. default:
  2655. break;
  2656. }
  2657. break;
  2658. case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
  2659. switch (state) {
  2660. case AMDGPU_IRQ_STATE_DISABLE:
  2661. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
  2662. cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
  2663. WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
  2664. break;
  2665. case AMDGPU_IRQ_STATE_ENABLE:
  2666. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
  2667. cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
  2668. WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
  2669. break;
  2670. default:
  2671. break;
  2672. }
  2673. break;
  2674. default:
  2675. break;
  2676. }
  2677. return 0;
  2678. }
  2679. static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
  2680. struct amdgpu_irq_src *source,
  2681. struct amdgpu_iv_entry *entry)
  2682. {
  2683. bool queue_thermal = false;
  2684. if (entry == NULL)
  2685. return -EINVAL;
  2686. switch (entry->src_id) {
  2687. case 230: /* thermal low to high */
  2688. DRM_DEBUG("IH: thermal low to high\n");
  2689. adev->pm.dpm.thermal.high_to_low = false;
  2690. queue_thermal = true;
  2691. break;
  2692. case 231: /* thermal high to low */
  2693. DRM_DEBUG("IH: thermal high to low\n");
  2694. adev->pm.dpm.thermal.high_to_low = true;
  2695. queue_thermal = true;
  2696. break;
  2697. default:
  2698. break;
  2699. }
  2700. if (queue_thermal)
  2701. schedule_work(&adev->pm.dpm.thermal.work);
  2702. return 0;
  2703. }
  2704. static int kv_dpm_set_clockgating_state(void *handle,
  2705. enum amd_clockgating_state state)
  2706. {
  2707. return 0;
  2708. }
  2709. static int kv_dpm_set_powergating_state(void *handle,
  2710. enum amd_powergating_state state)
  2711. {
  2712. return 0;
  2713. }
  2714. static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
  2715. const struct kv_pl *kv_cpl2)
  2716. {
  2717. return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
  2718. (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
  2719. (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
  2720. (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
  2721. }
  2722. static int kv_check_state_equal(struct amdgpu_device *adev,
  2723. struct amdgpu_ps *cps,
  2724. struct amdgpu_ps *rps,
  2725. bool *equal)
  2726. {
  2727. struct kv_ps *kv_cps;
  2728. struct kv_ps *kv_rps;
  2729. int i;
  2730. if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
  2731. return -EINVAL;
  2732. kv_cps = kv_get_ps(cps);
  2733. kv_rps = kv_get_ps(rps);
  2734. if (kv_cps == NULL) {
  2735. *equal = false;
  2736. return 0;
  2737. }
  2738. if (kv_cps->num_levels != kv_rps->num_levels) {
  2739. *equal = false;
  2740. return 0;
  2741. }
  2742. for (i = 0; i < kv_cps->num_levels; i++) {
  2743. if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
  2744. &(kv_rps->levels[i]))) {
  2745. *equal = false;
  2746. return 0;
  2747. }
  2748. }
  2749. /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
  2750. *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
  2751. *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
  2752. return 0;
  2753. }
  2754. static int kv_dpm_read_sensor(struct amdgpu_device *adev, int idx,
  2755. void *value, int *size)
  2756. {
  2757. struct kv_power_info *pi = kv_get_pi(adev);
  2758. uint32_t sclk;
  2759. u32 pl_index =
  2760. (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
  2761. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
  2762. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
  2763. /* size must be at least 4 bytes for all sensors */
  2764. if (*size < 4)
  2765. return -EINVAL;
  2766. switch (idx) {
  2767. case AMDGPU_PP_SENSOR_GFX_SCLK:
  2768. if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
  2769. sclk = be32_to_cpu(
  2770. pi->graphics_level[pl_index].SclkFrequency);
  2771. *((uint32_t *)value) = sclk;
  2772. *size = 4;
  2773. return 0;
  2774. }
  2775. return -EINVAL;
  2776. case AMDGPU_PP_SENSOR_GPU_TEMP:
  2777. *((uint32_t *)value) = kv_dpm_get_temp(adev);
  2778. *size = 4;
  2779. return 0;
  2780. default:
  2781. return -EINVAL;
  2782. }
  2783. }
  2784. const struct amd_ip_funcs kv_dpm_ip_funcs = {
  2785. .name = "kv_dpm",
  2786. .early_init = kv_dpm_early_init,
  2787. .late_init = kv_dpm_late_init,
  2788. .sw_init = kv_dpm_sw_init,
  2789. .sw_fini = kv_dpm_sw_fini,
  2790. .hw_init = kv_dpm_hw_init,
  2791. .hw_fini = kv_dpm_hw_fini,
  2792. .suspend = kv_dpm_suspend,
  2793. .resume = kv_dpm_resume,
  2794. .is_idle = kv_dpm_is_idle,
  2795. .wait_for_idle = kv_dpm_wait_for_idle,
  2796. .soft_reset = kv_dpm_soft_reset,
  2797. .set_clockgating_state = kv_dpm_set_clockgating_state,
  2798. .set_powergating_state = kv_dpm_set_powergating_state,
  2799. };
  2800. static const struct amdgpu_dpm_funcs kv_dpm_funcs = {
  2801. .get_temperature = &kv_dpm_get_temp,
  2802. .pre_set_power_state = &kv_dpm_pre_set_power_state,
  2803. .set_power_state = &kv_dpm_set_power_state,
  2804. .post_set_power_state = &kv_dpm_post_set_power_state,
  2805. .display_configuration_changed = &kv_dpm_display_configuration_changed,
  2806. .get_sclk = &kv_dpm_get_sclk,
  2807. .get_mclk = &kv_dpm_get_mclk,
  2808. .print_power_state = &kv_dpm_print_power_state,
  2809. .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
  2810. .force_performance_level = &kv_dpm_force_performance_level,
  2811. .powergate_uvd = &kv_dpm_powergate_uvd,
  2812. .enable_bapm = &kv_dpm_enable_bapm,
  2813. .get_vce_clock_state = amdgpu_get_vce_clock_state,
  2814. .check_state_equal = kv_check_state_equal,
  2815. .read_sensor = &kv_dpm_read_sensor,
  2816. };
  2817. static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
  2818. {
  2819. if (adev->pm.funcs == NULL)
  2820. adev->pm.funcs = &kv_dpm_funcs;
  2821. }
  2822. static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
  2823. .set = kv_dpm_set_interrupt_state,
  2824. .process = kv_dpm_process_interrupt,
  2825. };
  2826. static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
  2827. {
  2828. adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
  2829. adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
  2830. }