amdgpu_vce.h 3.2 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef __AMDGPU_VCE_H__
  24. #define __AMDGPU_VCE_H__
  25. #define AMDGPU_MAX_VCE_HANDLES 16
  26. #define AMDGPU_VCE_FIRMWARE_OFFSET 256
  27. #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
  28. #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
  29. struct amdgpu_vce {
  30. struct amdgpu_bo *vcpu_bo;
  31. uint64_t gpu_addr;
  32. void *cpu_addr;
  33. void *saved_bo;
  34. unsigned fw_version;
  35. unsigned fb_version;
  36. atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
  37. struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
  38. uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
  39. struct delayed_work idle_work;
  40. struct mutex idle_mutex;
  41. const struct firmware *fw; /* VCE firmware */
  42. struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
  43. struct amdgpu_irq_src irq;
  44. unsigned harvest_config;
  45. struct amd_sched_entity entity;
  46. uint32_t srbm_soft_reset;
  47. unsigned num_rings;
  48. };
  49. int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
  50. int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
  51. int amdgpu_vce_suspend(struct amdgpu_device *adev);
  52. int amdgpu_vce_resume(struct amdgpu_device *adev);
  53. int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
  54. struct dma_fence **fence);
  55. int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
  56. bool direct, struct dma_fence **fence);
  57. void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
  58. int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
  59. int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
  60. void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
  61. unsigned vm_id, bool ctx_switch);
  62. void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
  63. unsigned flags);
  64. int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
  65. int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout);
  66. void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring);
  67. void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring);
  68. unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring);
  69. unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring);
  70. #endif