amdgpu_sync.c 8.3 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Christian König <christian.koenig@amd.com>
  29. */
  30. #include <drm/drmP.h>
  31. #include "amdgpu.h"
  32. #include "amdgpu_trace.h"
  33. struct amdgpu_sync_entry {
  34. struct hlist_node node;
  35. struct dma_fence *fence;
  36. };
  37. static struct kmem_cache *amdgpu_sync_slab;
  38. /**
  39. * amdgpu_sync_create - zero init sync object
  40. *
  41. * @sync: sync object to initialize
  42. *
  43. * Just clear the sync object for now.
  44. */
  45. void amdgpu_sync_create(struct amdgpu_sync *sync)
  46. {
  47. hash_init(sync->fences);
  48. sync->last_vm_update = NULL;
  49. }
  50. /**
  51. * amdgpu_sync_same_dev - test if fence belong to us
  52. *
  53. * @adev: amdgpu device to use for the test
  54. * @f: fence to test
  55. *
  56. * Test if the fence was issued by us.
  57. */
  58. static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
  59. struct dma_fence *f)
  60. {
  61. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  62. if (s_fence) {
  63. struct amdgpu_ring *ring;
  64. ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
  65. return ring->adev == adev;
  66. }
  67. return false;
  68. }
  69. /**
  70. * amdgpu_sync_get_owner - extract the owner of a fence
  71. *
  72. * @fence: fence get the owner from
  73. *
  74. * Extract who originally created the fence.
  75. */
  76. static void *amdgpu_sync_get_owner(struct dma_fence *f)
  77. {
  78. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  79. if (s_fence)
  80. return s_fence->owner;
  81. return AMDGPU_FENCE_OWNER_UNDEFINED;
  82. }
  83. /**
  84. * amdgpu_sync_keep_later - Keep the later fence
  85. *
  86. * @keep: existing fence to test
  87. * @fence: new fence
  88. *
  89. * Either keep the existing fence or the new one, depending which one is later.
  90. */
  91. static void amdgpu_sync_keep_later(struct dma_fence **keep,
  92. struct dma_fence *fence)
  93. {
  94. if (*keep && dma_fence_is_later(*keep, fence))
  95. return;
  96. dma_fence_put(*keep);
  97. *keep = dma_fence_get(fence);
  98. }
  99. /**
  100. * amdgpu_sync_add_later - add the fence to the hash
  101. *
  102. * @sync: sync object to add the fence to
  103. * @f: fence to add
  104. *
  105. * Tries to add the fence to an existing hash entry. Returns true when an entry
  106. * was found, false otherwise.
  107. */
  108. static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f)
  109. {
  110. struct amdgpu_sync_entry *e;
  111. hash_for_each_possible(sync->fences, e, node, f->context) {
  112. if (unlikely(e->fence->context != f->context))
  113. continue;
  114. amdgpu_sync_keep_later(&e->fence, f);
  115. return true;
  116. }
  117. return false;
  118. }
  119. /**
  120. * amdgpu_sync_fence - remember to sync to this fence
  121. *
  122. * @sync: sync object to add fence to
  123. * @fence: fence to sync to
  124. *
  125. */
  126. int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  127. struct dma_fence *f)
  128. {
  129. struct amdgpu_sync_entry *e;
  130. if (!f)
  131. return 0;
  132. if (amdgpu_sync_same_dev(adev, f) &&
  133. amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
  134. amdgpu_sync_keep_later(&sync->last_vm_update, f);
  135. if (amdgpu_sync_add_later(sync, f))
  136. return 0;
  137. e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
  138. if (!e)
  139. return -ENOMEM;
  140. hash_add(sync->fences, &e->node, f->context);
  141. e->fence = dma_fence_get(f);
  142. return 0;
  143. }
  144. /**
  145. * amdgpu_sync_resv - sync to a reservation object
  146. *
  147. * @sync: sync object to add fences from reservation object to
  148. * @resv: reservation object with embedded fence
  149. * @shared: true if we should only sync to the exclusive fence
  150. *
  151. * Sync to the fence
  152. */
  153. int amdgpu_sync_resv(struct amdgpu_device *adev,
  154. struct amdgpu_sync *sync,
  155. struct reservation_object *resv,
  156. void *owner)
  157. {
  158. struct reservation_object_list *flist;
  159. struct dma_fence *f;
  160. void *fence_owner;
  161. unsigned i;
  162. int r = 0;
  163. if (resv == NULL)
  164. return -EINVAL;
  165. /* always sync to the exclusive fence */
  166. f = reservation_object_get_excl(resv);
  167. r = amdgpu_sync_fence(adev, sync, f);
  168. flist = reservation_object_get_list(resv);
  169. if (!flist || r)
  170. return r;
  171. for (i = 0; i < flist->shared_count; ++i) {
  172. f = rcu_dereference_protected(flist->shared[i],
  173. reservation_object_held(resv));
  174. if (amdgpu_sync_same_dev(adev, f)) {
  175. /* VM updates are only interesting
  176. * for other VM updates and moves.
  177. */
  178. fence_owner = amdgpu_sync_get_owner(f);
  179. if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
  180. (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
  181. ((owner == AMDGPU_FENCE_OWNER_VM) !=
  182. (fence_owner == AMDGPU_FENCE_OWNER_VM)))
  183. continue;
  184. /* Ignore fence from the same owner as
  185. * long as it isn't undefined.
  186. */
  187. if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
  188. fence_owner == owner)
  189. continue;
  190. }
  191. r = amdgpu_sync_fence(adev, sync, f);
  192. if (r)
  193. break;
  194. }
  195. return r;
  196. }
  197. /**
  198. * amdgpu_sync_peek_fence - get the next fence not signaled yet
  199. *
  200. * @sync: the sync object
  201. * @ring: optional ring to use for test
  202. *
  203. * Returns the next fence not signaled yet without removing it from the sync
  204. * object.
  205. */
  206. struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
  207. struct amdgpu_ring *ring)
  208. {
  209. struct amdgpu_sync_entry *e;
  210. struct hlist_node *tmp;
  211. int i;
  212. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  213. struct dma_fence *f = e->fence;
  214. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  215. if (dma_fence_is_signaled(f)) {
  216. hash_del(&e->node);
  217. dma_fence_put(f);
  218. kmem_cache_free(amdgpu_sync_slab, e);
  219. continue;
  220. }
  221. if (ring && s_fence) {
  222. /* For fences from the same ring it is sufficient
  223. * when they are scheduled.
  224. */
  225. if (s_fence->sched == &ring->sched) {
  226. if (dma_fence_is_signaled(&s_fence->scheduled))
  227. continue;
  228. return &s_fence->scheduled;
  229. }
  230. }
  231. return f;
  232. }
  233. return NULL;
  234. }
  235. /**
  236. * amdgpu_sync_get_fence - get the next fence from the sync object
  237. *
  238. * @sync: sync object to use
  239. *
  240. * Get and removes the next fence from the sync object not signaled yet.
  241. */
  242. struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
  243. {
  244. struct amdgpu_sync_entry *e;
  245. struct hlist_node *tmp;
  246. struct dma_fence *f;
  247. int i;
  248. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  249. f = e->fence;
  250. hash_del(&e->node);
  251. kmem_cache_free(amdgpu_sync_slab, e);
  252. if (!dma_fence_is_signaled(f))
  253. return f;
  254. dma_fence_put(f);
  255. }
  256. return NULL;
  257. }
  258. int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
  259. {
  260. struct amdgpu_sync_entry *e;
  261. struct hlist_node *tmp;
  262. int i, r;
  263. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  264. r = dma_fence_wait(e->fence, intr);
  265. if (r)
  266. return r;
  267. hash_del(&e->node);
  268. dma_fence_put(e->fence);
  269. kmem_cache_free(amdgpu_sync_slab, e);
  270. }
  271. return 0;
  272. }
  273. /**
  274. * amdgpu_sync_free - free the sync object
  275. *
  276. * @sync: sync object to use
  277. *
  278. * Free the sync object.
  279. */
  280. void amdgpu_sync_free(struct amdgpu_sync *sync)
  281. {
  282. struct amdgpu_sync_entry *e;
  283. struct hlist_node *tmp;
  284. unsigned i;
  285. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  286. hash_del(&e->node);
  287. dma_fence_put(e->fence);
  288. kmem_cache_free(amdgpu_sync_slab, e);
  289. }
  290. dma_fence_put(sync->last_vm_update);
  291. }
  292. /**
  293. * amdgpu_sync_init - init sync object subsystem
  294. *
  295. * Allocate the slab allocator.
  296. */
  297. int amdgpu_sync_init(void)
  298. {
  299. amdgpu_sync_slab = kmem_cache_create(
  300. "amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0,
  301. SLAB_HWCACHE_ALIGN, NULL);
  302. if (!amdgpu_sync_slab)
  303. return -ENOMEM;
  304. return 0;
  305. }
  306. /**
  307. * amdgpu_sync_fini - fini sync object subsystem
  308. *
  309. * Free the slab allocator.
  310. */
  311. void amdgpu_sync_fini(void)
  312. {
  313. kmem_cache_destroy(amdgpu_sync_slab);
  314. }