amdgpu_job.c 5.6 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. *
  23. */
  24. #include <linux/kthread.h>
  25. #include <linux/wait.h>
  26. #include <linux/sched.h>
  27. #include <drm/drmP.h>
  28. #include "amdgpu.h"
  29. #include "amdgpu_trace.h"
  30. static void amdgpu_job_timedout(struct amd_sched_job *s_job)
  31. {
  32. struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
  33. DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
  34. job->base.sched->name,
  35. atomic_read(&job->ring->fence_drv.last_seq),
  36. job->ring->fence_drv.sync_seq);
  37. if (amdgpu_sriov_vf(job->adev))
  38. amdgpu_sriov_gpu_reset(job->adev, job);
  39. else
  40. amdgpu_gpu_reset(job->adev);
  41. }
  42. int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
  43. struct amdgpu_job **job, struct amdgpu_vm *vm)
  44. {
  45. size_t size = sizeof(struct amdgpu_job);
  46. if (num_ibs == 0)
  47. return -EINVAL;
  48. size += sizeof(struct amdgpu_ib) * num_ibs;
  49. *job = kzalloc(size, GFP_KERNEL);
  50. if (!*job)
  51. return -ENOMEM;
  52. (*job)->adev = adev;
  53. (*job)->vm = vm;
  54. (*job)->ibs = (void *)&(*job)[1];
  55. (*job)->num_ibs = num_ibs;
  56. amdgpu_sync_create(&(*job)->sync);
  57. amdgpu_sync_create(&(*job)->dep_sync);
  58. amdgpu_sync_create(&(*job)->sched_sync);
  59. return 0;
  60. }
  61. int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
  62. struct amdgpu_job **job)
  63. {
  64. int r;
  65. r = amdgpu_job_alloc(adev, 1, job, NULL);
  66. if (r)
  67. return r;
  68. r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
  69. if (r)
  70. kfree(*job);
  71. else
  72. (*job)->vm_pd_addr = adev->gart.table_addr;
  73. return r;
  74. }
  75. void amdgpu_job_free_resources(struct amdgpu_job *job)
  76. {
  77. struct dma_fence *f;
  78. unsigned i;
  79. /* use sched fence if available */
  80. f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
  81. for (i = 0; i < job->num_ibs; ++i)
  82. amdgpu_ib_free(job->adev, &job->ibs[i], f);
  83. }
  84. static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
  85. {
  86. struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
  87. dma_fence_put(job->fence);
  88. amdgpu_sync_free(&job->sync);
  89. amdgpu_sync_free(&job->dep_sync);
  90. amdgpu_sync_free(&job->sched_sync);
  91. kfree(job);
  92. }
  93. void amdgpu_job_free(struct amdgpu_job *job)
  94. {
  95. amdgpu_job_free_resources(job);
  96. dma_fence_put(job->fence);
  97. amdgpu_sync_free(&job->sync);
  98. amdgpu_sync_free(&job->dep_sync);
  99. amdgpu_sync_free(&job->sched_sync);
  100. kfree(job);
  101. }
  102. int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
  103. struct amd_sched_entity *entity, void *owner,
  104. struct dma_fence **f)
  105. {
  106. int r;
  107. job->ring = ring;
  108. if (!f)
  109. return -EINVAL;
  110. r = amd_sched_job_init(&job->base, &ring->sched, entity, owner);
  111. if (r)
  112. return r;
  113. job->owner = owner;
  114. job->fence_ctx = entity->fence_context;
  115. *f = dma_fence_get(&job->base.s_fence->finished);
  116. amdgpu_job_free_resources(job);
  117. amd_sched_entity_push_job(&job->base);
  118. return 0;
  119. }
  120. static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
  121. {
  122. struct amdgpu_job *job = to_amdgpu_job(sched_job);
  123. struct amdgpu_vm *vm = job->vm;
  124. struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync);
  125. int r;
  126. if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) {
  127. r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence);
  128. if (r)
  129. DRM_ERROR("Error adding fence to sync (%d)\n", r);
  130. }
  131. if (!fence)
  132. fence = amdgpu_sync_get_fence(&job->sync);
  133. while (fence == NULL && vm && !job->vm_id) {
  134. struct amdgpu_ring *ring = job->ring;
  135. r = amdgpu_vm_grab_id(vm, ring, &job->sync,
  136. &job->base.s_fence->finished,
  137. job);
  138. if (r)
  139. DRM_ERROR("Error getting VM ID (%d)\n", r);
  140. fence = amdgpu_sync_get_fence(&job->sync);
  141. }
  142. return fence;
  143. }
  144. static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job)
  145. {
  146. struct dma_fence *fence = NULL;
  147. struct amdgpu_job *job;
  148. struct amdgpu_fpriv *fpriv = NULL;
  149. int r;
  150. if (!sched_job) {
  151. DRM_ERROR("job is null\n");
  152. return NULL;
  153. }
  154. job = to_amdgpu_job(sched_job);
  155. BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
  156. trace_amdgpu_sched_run_job(job);
  157. if (job->vm)
  158. fpriv = container_of(job->vm, struct amdgpu_fpriv, vm);
  159. /* skip ib schedule when vram is lost */
  160. if (fpriv && amdgpu_kms_vram_lost(job->adev, fpriv))
  161. DRM_ERROR("Skip scheduling IBs!\n");
  162. else {
  163. r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence);
  164. if (r)
  165. DRM_ERROR("Error scheduling IBs (%d)\n", r);
  166. }
  167. /* if gpu reset, hw fence will be replaced here */
  168. dma_fence_put(job->fence);
  169. job->fence = dma_fence_get(fence);
  170. amdgpu_job_free_resources(job);
  171. return fence;
  172. }
  173. const struct amd_sched_backend_ops amdgpu_sched_ops = {
  174. .dependency = amdgpu_job_dependency,
  175. .run_job = amdgpu_job_run,
  176. .timedout_job = amdgpu_job_timedout,
  177. .free_job = amdgpu_job_free_cb
  178. };