amdgpu_ib.c 11 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. * Christian König
  28. */
  29. #include <linux/seq_file.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/amdgpu_drm.h>
  33. #include "amdgpu.h"
  34. #include "atom.h"
  35. #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
  36. /*
  37. * IB
  38. * IBs (Indirect Buffers) and areas of GPU accessible memory where
  39. * commands are stored. You can put a pointer to the IB in the
  40. * command ring and the hw will fetch the commands from the IB
  41. * and execute them. Generally userspace acceleration drivers
  42. * produce command buffers which are send to the kernel and
  43. * put in IBs for execution by the requested ring.
  44. */
  45. static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
  46. /**
  47. * amdgpu_ib_get - request an IB (Indirect Buffer)
  48. *
  49. * @ring: ring index the IB is associated with
  50. * @size: requested IB size
  51. * @ib: IB object returned
  52. *
  53. * Request an IB (all asics). IBs are allocated using the
  54. * suballocator.
  55. * Returns 0 on success, error on failure.
  56. */
  57. int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  58. unsigned size, struct amdgpu_ib *ib)
  59. {
  60. int r;
  61. if (size) {
  62. r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
  63. &ib->sa_bo, size, 256);
  64. if (r) {
  65. dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
  66. return r;
  67. }
  68. ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
  69. if (!vm)
  70. ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
  71. }
  72. return 0;
  73. }
  74. /**
  75. * amdgpu_ib_free - free an IB (Indirect Buffer)
  76. *
  77. * @adev: amdgpu_device pointer
  78. * @ib: IB object to free
  79. * @f: the fence SA bo need wait on for the ib alloation
  80. *
  81. * Free an IB (all asics).
  82. */
  83. void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
  84. struct dma_fence *f)
  85. {
  86. amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
  87. }
  88. /**
  89. * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
  90. *
  91. * @adev: amdgpu_device pointer
  92. * @num_ibs: number of IBs to schedule
  93. * @ibs: IB objects to schedule
  94. * @f: fence created during this submission
  95. *
  96. * Schedule an IB on the associated ring (all asics).
  97. * Returns 0 on success, error on failure.
  98. *
  99. * On SI, there are two parallel engines fed from the primary ring,
  100. * the CE (Constant Engine) and the DE (Drawing Engine). Since
  101. * resource descriptors have moved to memory, the CE allows you to
  102. * prime the caches while the DE is updating register state so that
  103. * the resource descriptors will be already in cache when the draw is
  104. * processed. To accomplish this, the userspace driver submits two
  105. * IBs, one for the CE and one for the DE. If there is a CE IB (called
  106. * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
  107. * to SI there was just a DE IB.
  108. */
  109. int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
  110. struct amdgpu_ib *ibs, struct amdgpu_job *job,
  111. struct dma_fence **f)
  112. {
  113. struct amdgpu_device *adev = ring->adev;
  114. struct amdgpu_ib *ib = &ibs[0];
  115. struct dma_fence *tmp = NULL;
  116. bool skip_preamble, need_ctx_switch;
  117. unsigned patch_offset = ~0;
  118. struct amdgpu_vm *vm;
  119. uint64_t fence_ctx;
  120. uint32_t status = 0, alloc_size;
  121. unsigned i;
  122. int r = 0;
  123. bool need_pipe_sync = false;
  124. if (num_ibs == 0)
  125. return -EINVAL;
  126. /* ring tests don't use a job */
  127. if (job) {
  128. vm = job->vm;
  129. fence_ctx = job->fence_ctx;
  130. } else {
  131. vm = NULL;
  132. fence_ctx = 0;
  133. }
  134. if (!ring->ready) {
  135. dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
  136. return -EINVAL;
  137. }
  138. if (vm && !job->vm_id) {
  139. dev_err(adev->dev, "VM IB without ID\n");
  140. return -EINVAL;
  141. }
  142. alloc_size = ring->funcs->emit_frame_size + num_ibs *
  143. ring->funcs->emit_ib_size;
  144. r = amdgpu_ring_alloc(ring, alloc_size);
  145. if (r) {
  146. dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
  147. return r;
  148. }
  149. if (ring->funcs->emit_pipeline_sync && job &&
  150. ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
  151. amdgpu_vm_need_pipeline_sync(ring, job))) {
  152. need_pipe_sync = true;
  153. dma_fence_put(tmp);
  154. }
  155. if (ring->funcs->insert_start)
  156. ring->funcs->insert_start(ring);
  157. if (job) {
  158. r = amdgpu_vm_flush(ring, job, need_pipe_sync);
  159. if (r) {
  160. amdgpu_ring_undo(ring);
  161. return r;
  162. }
  163. }
  164. if (ring->funcs->init_cond_exec)
  165. patch_offset = amdgpu_ring_init_cond_exec(ring);
  166. if (ring->funcs->emit_hdp_flush
  167. #ifdef CONFIG_X86_64
  168. && !(adev->flags & AMD_IS_APU)
  169. #endif
  170. )
  171. amdgpu_ring_emit_hdp_flush(ring);
  172. skip_preamble = ring->current_ctx == fence_ctx;
  173. need_ctx_switch = ring->current_ctx != fence_ctx;
  174. if (job && ring->funcs->emit_cntxcntl) {
  175. if (need_ctx_switch)
  176. status |= AMDGPU_HAVE_CTX_SWITCH;
  177. status |= job->preamble_status;
  178. amdgpu_ring_emit_cntxcntl(ring, status);
  179. }
  180. for (i = 0; i < num_ibs; ++i) {
  181. ib = &ibs[i];
  182. /* drop preamble IBs if we don't have a context switch */
  183. if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
  184. skip_preamble &&
  185. !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
  186. !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
  187. continue;
  188. amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
  189. need_ctx_switch);
  190. need_ctx_switch = false;
  191. }
  192. if (ring->funcs->emit_tmz)
  193. amdgpu_ring_emit_tmz(ring, false);
  194. if (ring->funcs->emit_hdp_invalidate
  195. #ifdef CONFIG_X86_64
  196. && !(adev->flags & AMD_IS_APU)
  197. #endif
  198. )
  199. amdgpu_ring_emit_hdp_invalidate(ring);
  200. r = amdgpu_fence_emit(ring, f);
  201. if (r) {
  202. dev_err(adev->dev, "failed to emit fence (%d)\n", r);
  203. if (job && job->vm_id)
  204. amdgpu_vm_reset_id(adev, ring->funcs->vmhub,
  205. job->vm_id);
  206. amdgpu_ring_undo(ring);
  207. return r;
  208. }
  209. if (ring->funcs->insert_end)
  210. ring->funcs->insert_end(ring);
  211. /* wrap the last IB with fence */
  212. if (job && job->uf_addr) {
  213. amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
  214. AMDGPU_FENCE_FLAG_64BIT);
  215. }
  216. if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
  217. amdgpu_ring_patch_cond_exec(ring, patch_offset);
  218. ring->current_ctx = fence_ctx;
  219. if (vm && ring->funcs->emit_switch_buffer)
  220. amdgpu_ring_emit_switch_buffer(ring);
  221. amdgpu_ring_commit(ring);
  222. return 0;
  223. }
  224. /**
  225. * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
  226. *
  227. * @adev: amdgpu_device pointer
  228. *
  229. * Initialize the suballocator to manage a pool of memory
  230. * for use as IBs (all asics).
  231. * Returns 0 on success, error on failure.
  232. */
  233. int amdgpu_ib_pool_init(struct amdgpu_device *adev)
  234. {
  235. int r;
  236. if (adev->ib_pool_ready) {
  237. return 0;
  238. }
  239. r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
  240. AMDGPU_IB_POOL_SIZE*64*1024,
  241. AMDGPU_GPU_PAGE_SIZE,
  242. AMDGPU_GEM_DOMAIN_GTT);
  243. if (r) {
  244. return r;
  245. }
  246. r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
  247. if (r) {
  248. return r;
  249. }
  250. adev->ib_pool_ready = true;
  251. if (amdgpu_debugfs_sa_init(adev)) {
  252. dev_err(adev->dev, "failed to register debugfs file for SA\n");
  253. }
  254. return 0;
  255. }
  256. /**
  257. * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
  258. *
  259. * @adev: amdgpu_device pointer
  260. *
  261. * Tear down the suballocator managing the pool of memory
  262. * for use as IBs (all asics).
  263. */
  264. void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
  265. {
  266. if (adev->ib_pool_ready) {
  267. amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
  268. amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
  269. adev->ib_pool_ready = false;
  270. }
  271. }
  272. /**
  273. * amdgpu_ib_ring_tests - test IBs on the rings
  274. *
  275. * @adev: amdgpu_device pointer
  276. *
  277. * Test an IB (Indirect Buffer) on each ring.
  278. * If the test fails, disable the ring.
  279. * Returns 0 on success, error if the primary GFX ring
  280. * IB test fails.
  281. */
  282. int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
  283. {
  284. unsigned i;
  285. int r, ret = 0;
  286. long tmo_gfx, tmo_mm;
  287. tmo_mm = tmo_gfx = AMDGPU_IB_TEST_TIMEOUT;
  288. if (amdgpu_sriov_vf(adev)) {
  289. /* for MM engines in hypervisor side they are not scheduled together
  290. * with CP and SDMA engines, so even in exclusive mode MM engine could
  291. * still running on other VF thus the IB TEST TIMEOUT for MM engines
  292. * under SR-IOV should be set to a long time. 8 sec should be enough
  293. * for the MM comes back to this VF.
  294. */
  295. tmo_mm = 8 * AMDGPU_IB_TEST_TIMEOUT;
  296. }
  297. if (amdgpu_sriov_runtime(adev)) {
  298. /* for CP & SDMA engines since they are scheduled together so
  299. * need to make the timeout width enough to cover the time
  300. * cost waiting for it coming back under RUNTIME only
  301. */
  302. tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
  303. }
  304. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  305. struct amdgpu_ring *ring = adev->rings[i];
  306. long tmo;
  307. if (!ring || !ring->ready)
  308. continue;
  309. /* MM engine need more time */
  310. if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
  311. ring->funcs->type == AMDGPU_RING_TYPE_VCE ||
  312. ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||
  313. ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||
  314. ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
  315. tmo = tmo_mm;
  316. else
  317. tmo = tmo_gfx;
  318. r = amdgpu_ring_test_ib(ring, tmo);
  319. if (r) {
  320. ring->ready = false;
  321. if (ring == &adev->gfx.gfx_ring[0]) {
  322. /* oh, oh, that's really bad */
  323. DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
  324. adev->accel_working = false;
  325. return r;
  326. } else {
  327. /* still not good, but we can live with it */
  328. DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
  329. ret = r;
  330. }
  331. }
  332. }
  333. return ret;
  334. }
  335. /*
  336. * Debugfs info
  337. */
  338. #if defined(CONFIG_DEBUG_FS)
  339. static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
  340. {
  341. struct drm_info_node *node = (struct drm_info_node *) m->private;
  342. struct drm_device *dev = node->minor->dev;
  343. struct amdgpu_device *adev = dev->dev_private;
  344. amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
  345. return 0;
  346. }
  347. static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
  348. {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
  349. };
  350. #endif
  351. static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
  352. {
  353. #if defined(CONFIG_DEBUG_FS)
  354. return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
  355. #else
  356. return 0;
  357. #endif
  358. }