amdgpu_device.c 95 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/kthread.h>
  29. #include <linux/console.h>
  30. #include <linux/slab.h>
  31. #include <linux/debugfs.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc_helper.h>
  34. #include <drm/amdgpu_drm.h>
  35. #include <linux/vgaarb.h>
  36. #include <linux/vga_switcheroo.h>
  37. #include <linux/efi.h>
  38. #include "amdgpu.h"
  39. #include "amdgpu_trace.h"
  40. #include "amdgpu_i2c.h"
  41. #include "atom.h"
  42. #include "amdgpu_atombios.h"
  43. #include "amdgpu_atomfirmware.h"
  44. #include "amd_pcie.h"
  45. #ifdef CONFIG_DRM_AMDGPU_SI
  46. #include "si.h"
  47. #endif
  48. #ifdef CONFIG_DRM_AMDGPU_CIK
  49. #include "cik.h"
  50. #endif
  51. #include "vi.h"
  52. #include "soc15.h"
  53. #include "bif/bif_4_1_d.h"
  54. #include <linux/pci.h>
  55. #include <linux/firmware.h>
  56. #include "amdgpu_vf_error.h"
  57. #include "amdgpu_amdkfd.h"
  58. MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  59. MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
  60. #define AMDGPU_RESUME_MS 2000
  61. static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  62. static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  63. static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
  64. static const char *amdgpu_asic_name[] = {
  65. "TAHITI",
  66. "PITCAIRN",
  67. "VERDE",
  68. "OLAND",
  69. "HAINAN",
  70. "BONAIRE",
  71. "KAVERI",
  72. "KABINI",
  73. "HAWAII",
  74. "MULLINS",
  75. "TOPAZ",
  76. "TONGA",
  77. "FIJI",
  78. "CARRIZO",
  79. "STONEY",
  80. "POLARIS10",
  81. "POLARIS11",
  82. "POLARIS12",
  83. "VEGA10",
  84. "RAVEN",
  85. "LAST",
  86. };
  87. bool amdgpu_device_is_px(struct drm_device *dev)
  88. {
  89. struct amdgpu_device *adev = dev->dev_private;
  90. if (adev->flags & AMD_IS_PX)
  91. return true;
  92. return false;
  93. }
  94. /*
  95. * MMIO register access helper functions.
  96. */
  97. uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  98. uint32_t acc_flags)
  99. {
  100. uint32_t ret;
  101. if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
  102. BUG_ON(in_interrupt());
  103. return amdgpu_virt_kiq_rreg(adev, reg);
  104. }
  105. if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
  106. ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
  107. else {
  108. unsigned long flags;
  109. spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  110. writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  111. ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  112. spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  113. }
  114. trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
  115. return ret;
  116. }
  117. void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  118. uint32_t acc_flags)
  119. {
  120. trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
  121. if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
  122. adev->last_mm_index = v;
  123. }
  124. if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
  125. BUG_ON(in_interrupt());
  126. return amdgpu_virt_kiq_wreg(adev, reg, v);
  127. }
  128. if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
  129. writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
  130. else {
  131. unsigned long flags;
  132. spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  133. writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  134. writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  135. spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  136. }
  137. if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
  138. udelay(500);
  139. }
  140. }
  141. u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
  142. {
  143. if ((reg * 4) < adev->rio_mem_size)
  144. return ioread32(adev->rio_mem + (reg * 4));
  145. else {
  146. iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
  147. return ioread32(adev->rio_mem + (mmMM_DATA * 4));
  148. }
  149. }
  150. void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  151. {
  152. if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
  153. adev->last_mm_index = v;
  154. }
  155. if ((reg * 4) < adev->rio_mem_size)
  156. iowrite32(v, adev->rio_mem + (reg * 4));
  157. else {
  158. iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
  159. iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
  160. }
  161. if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
  162. udelay(500);
  163. }
  164. }
  165. /**
  166. * amdgpu_mm_rdoorbell - read a doorbell dword
  167. *
  168. * @adev: amdgpu_device pointer
  169. * @index: doorbell index
  170. *
  171. * Returns the value in the doorbell aperture at the
  172. * requested doorbell index (CIK).
  173. */
  174. u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
  175. {
  176. if (index < adev->doorbell.num_doorbells) {
  177. return readl(adev->doorbell.ptr + index);
  178. } else {
  179. DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
  180. return 0;
  181. }
  182. }
  183. /**
  184. * amdgpu_mm_wdoorbell - write a doorbell dword
  185. *
  186. * @adev: amdgpu_device pointer
  187. * @index: doorbell index
  188. * @v: value to write
  189. *
  190. * Writes @v to the doorbell aperture at the
  191. * requested doorbell index (CIK).
  192. */
  193. void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
  194. {
  195. if (index < adev->doorbell.num_doorbells) {
  196. writel(v, adev->doorbell.ptr + index);
  197. } else {
  198. DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
  199. }
  200. }
  201. /**
  202. * amdgpu_mm_rdoorbell64 - read a doorbell Qword
  203. *
  204. * @adev: amdgpu_device pointer
  205. * @index: doorbell index
  206. *
  207. * Returns the value in the doorbell aperture at the
  208. * requested doorbell index (VEGA10+).
  209. */
  210. u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
  211. {
  212. if (index < adev->doorbell.num_doorbells) {
  213. return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
  214. } else {
  215. DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
  216. return 0;
  217. }
  218. }
  219. /**
  220. * amdgpu_mm_wdoorbell64 - write a doorbell Qword
  221. *
  222. * @adev: amdgpu_device pointer
  223. * @index: doorbell index
  224. * @v: value to write
  225. *
  226. * Writes @v to the doorbell aperture at the
  227. * requested doorbell index (VEGA10+).
  228. */
  229. void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
  230. {
  231. if (index < adev->doorbell.num_doorbells) {
  232. atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
  233. } else {
  234. DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
  235. }
  236. }
  237. /**
  238. * amdgpu_invalid_rreg - dummy reg read function
  239. *
  240. * @adev: amdgpu device pointer
  241. * @reg: offset of register
  242. *
  243. * Dummy register read function. Used for register blocks
  244. * that certain asics don't have (all asics).
  245. * Returns the value in the register.
  246. */
  247. static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
  248. {
  249. DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  250. BUG();
  251. return 0;
  252. }
  253. /**
  254. * amdgpu_invalid_wreg - dummy reg write function
  255. *
  256. * @adev: amdgpu device pointer
  257. * @reg: offset of register
  258. * @v: value to write to the register
  259. *
  260. * Dummy register read function. Used for register blocks
  261. * that certain asics don't have (all asics).
  262. */
  263. static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
  264. {
  265. DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  266. reg, v);
  267. BUG();
  268. }
  269. /**
  270. * amdgpu_block_invalid_rreg - dummy reg read function
  271. *
  272. * @adev: amdgpu device pointer
  273. * @block: offset of instance
  274. * @reg: offset of register
  275. *
  276. * Dummy register read function. Used for register blocks
  277. * that certain asics don't have (all asics).
  278. * Returns the value in the register.
  279. */
  280. static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
  281. uint32_t block, uint32_t reg)
  282. {
  283. DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
  284. reg, block);
  285. BUG();
  286. return 0;
  287. }
  288. /**
  289. * amdgpu_block_invalid_wreg - dummy reg write function
  290. *
  291. * @adev: amdgpu device pointer
  292. * @block: offset of instance
  293. * @reg: offset of register
  294. * @v: value to write to the register
  295. *
  296. * Dummy register read function. Used for register blocks
  297. * that certain asics don't have (all asics).
  298. */
  299. static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
  300. uint32_t block,
  301. uint32_t reg, uint32_t v)
  302. {
  303. DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
  304. reg, block, v);
  305. BUG();
  306. }
  307. static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
  308. {
  309. return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
  310. PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
  311. &adev->vram_scratch.robj,
  312. &adev->vram_scratch.gpu_addr,
  313. (void **)&adev->vram_scratch.ptr);
  314. }
  315. static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
  316. {
  317. amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
  318. }
  319. /**
  320. * amdgpu_program_register_sequence - program an array of registers.
  321. *
  322. * @adev: amdgpu_device pointer
  323. * @registers: pointer to the register array
  324. * @array_size: size of the register array
  325. *
  326. * Programs an array or registers with and and or masks.
  327. * This is a helper for setting golden registers.
  328. */
  329. void amdgpu_program_register_sequence(struct amdgpu_device *adev,
  330. const u32 *registers,
  331. const u32 array_size)
  332. {
  333. u32 tmp, reg, and_mask, or_mask;
  334. int i;
  335. if (array_size % 3)
  336. return;
  337. for (i = 0; i < array_size; i +=3) {
  338. reg = registers[i + 0];
  339. and_mask = registers[i + 1];
  340. or_mask = registers[i + 2];
  341. if (and_mask == 0xffffffff) {
  342. tmp = or_mask;
  343. } else {
  344. tmp = RREG32(reg);
  345. tmp &= ~and_mask;
  346. tmp |= or_mask;
  347. }
  348. WREG32(reg, tmp);
  349. }
  350. }
  351. void amdgpu_pci_config_reset(struct amdgpu_device *adev)
  352. {
  353. pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
  354. }
  355. /*
  356. * GPU doorbell aperture helpers function.
  357. */
  358. /**
  359. * amdgpu_doorbell_init - Init doorbell driver information.
  360. *
  361. * @adev: amdgpu_device pointer
  362. *
  363. * Init doorbell driver information (CIK)
  364. * Returns 0 on success, error on failure.
  365. */
  366. static int amdgpu_doorbell_init(struct amdgpu_device *adev)
  367. {
  368. /* doorbell bar mapping */
  369. adev->doorbell.base = pci_resource_start(adev->pdev, 2);
  370. adev->doorbell.size = pci_resource_len(adev->pdev, 2);
  371. adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
  372. AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
  373. if (adev->doorbell.num_doorbells == 0)
  374. return -EINVAL;
  375. adev->doorbell.ptr = ioremap(adev->doorbell.base,
  376. adev->doorbell.num_doorbells *
  377. sizeof(u32));
  378. if (adev->doorbell.ptr == NULL)
  379. return -ENOMEM;
  380. return 0;
  381. }
  382. /**
  383. * amdgpu_doorbell_fini - Tear down doorbell driver information.
  384. *
  385. * @adev: amdgpu_device pointer
  386. *
  387. * Tear down doorbell driver information (CIK)
  388. */
  389. static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
  390. {
  391. iounmap(adev->doorbell.ptr);
  392. adev->doorbell.ptr = NULL;
  393. }
  394. /**
  395. * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
  396. * setup amdkfd
  397. *
  398. * @adev: amdgpu_device pointer
  399. * @aperture_base: output returning doorbell aperture base physical address
  400. * @aperture_size: output returning doorbell aperture size in bytes
  401. * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
  402. *
  403. * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
  404. * takes doorbells required for its own rings and reports the setup to amdkfd.
  405. * amdgpu reserved doorbells are at the start of the doorbell aperture.
  406. */
  407. void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
  408. phys_addr_t *aperture_base,
  409. size_t *aperture_size,
  410. size_t *start_offset)
  411. {
  412. /*
  413. * The first num_doorbells are used by amdgpu.
  414. * amdkfd takes whatever's left in the aperture.
  415. */
  416. if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
  417. *aperture_base = adev->doorbell.base;
  418. *aperture_size = adev->doorbell.size;
  419. *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
  420. } else {
  421. *aperture_base = 0;
  422. *aperture_size = 0;
  423. *start_offset = 0;
  424. }
  425. }
  426. /*
  427. * amdgpu_wb_*()
  428. * Writeback is the method by which the GPU updates special pages in memory
  429. * with the status of certain GPU events (fences, ring pointers,etc.).
  430. */
  431. /**
  432. * amdgpu_wb_fini - Disable Writeback and free memory
  433. *
  434. * @adev: amdgpu_device pointer
  435. *
  436. * Disables Writeback and frees the Writeback memory (all asics).
  437. * Used at driver shutdown.
  438. */
  439. static void amdgpu_wb_fini(struct amdgpu_device *adev)
  440. {
  441. if (adev->wb.wb_obj) {
  442. amdgpu_bo_free_kernel(&adev->wb.wb_obj,
  443. &adev->wb.gpu_addr,
  444. (void **)&adev->wb.wb);
  445. adev->wb.wb_obj = NULL;
  446. }
  447. }
  448. /**
  449. * amdgpu_wb_init- Init Writeback driver info and allocate memory
  450. *
  451. * @adev: amdgpu_device pointer
  452. *
  453. * Initializes writeback and allocates writeback memory (all asics).
  454. * Used at driver startup.
  455. * Returns 0 on success or an -error on failure.
  456. */
  457. static int amdgpu_wb_init(struct amdgpu_device *adev)
  458. {
  459. int r;
  460. if (adev->wb.wb_obj == NULL) {
  461. /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
  462. r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
  463. PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
  464. &adev->wb.wb_obj, &adev->wb.gpu_addr,
  465. (void **)&adev->wb.wb);
  466. if (r) {
  467. dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
  468. return r;
  469. }
  470. adev->wb.num_wb = AMDGPU_MAX_WB;
  471. memset(&adev->wb.used, 0, sizeof(adev->wb.used));
  472. /* clear wb memory */
  473. memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
  474. }
  475. return 0;
  476. }
  477. /**
  478. * amdgpu_wb_get - Allocate a wb entry
  479. *
  480. * @adev: amdgpu_device pointer
  481. * @wb: wb index
  482. *
  483. * Allocate a wb slot for use by the driver (all asics).
  484. * Returns 0 on success or -EINVAL on failure.
  485. */
  486. int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
  487. {
  488. unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
  489. if (offset < adev->wb.num_wb) {
  490. __set_bit(offset, adev->wb.used);
  491. *wb = offset * 8; /* convert to dw offset */
  492. return 0;
  493. } else {
  494. return -EINVAL;
  495. }
  496. }
  497. /**
  498. * amdgpu_wb_free - Free a wb entry
  499. *
  500. * @adev: amdgpu_device pointer
  501. * @wb: wb index
  502. *
  503. * Free a wb slot allocated for use by the driver (all asics)
  504. */
  505. void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
  506. {
  507. if (wb < adev->wb.num_wb)
  508. __clear_bit(wb, adev->wb.used);
  509. }
  510. /**
  511. * amdgpu_vram_location - try to find VRAM location
  512. * @adev: amdgpu device structure holding all necessary informations
  513. * @mc: memory controller structure holding memory informations
  514. * @base: base address at which to put VRAM
  515. *
  516. * Function will try to place VRAM at base address provided
  517. * as parameter (which is so far either PCI aperture address or
  518. * for IGP TOM base address).
  519. *
  520. * If there is not enough space to fit the unvisible VRAM in the 32bits
  521. * address space then we limit the VRAM size to the aperture.
  522. *
  523. * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
  524. * this shouldn't be a problem as we are using the PCI aperture as a reference.
  525. * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
  526. * not IGP.
  527. *
  528. * Note: we use mc_vram_size as on some board we need to program the mc to
  529. * cover the whole aperture even if VRAM size is inferior to aperture size
  530. * Novell bug 204882 + along with lots of ubuntu ones
  531. *
  532. * Note: when limiting vram it's safe to overwritte real_vram_size because
  533. * we are not in case where real_vram_size is inferior to mc_vram_size (ie
  534. * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
  535. * ones)
  536. *
  537. * Note: IGP TOM addr should be the same as the aperture addr, we don't
  538. * explicitly check for that though.
  539. *
  540. * FIXME: when reducing VRAM size align new size on power of 2.
  541. */
  542. void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
  543. {
  544. uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
  545. mc->vram_start = base;
  546. if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
  547. dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
  548. mc->real_vram_size = mc->aper_size;
  549. mc->mc_vram_size = mc->aper_size;
  550. }
  551. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  552. if (limit && limit < mc->real_vram_size)
  553. mc->real_vram_size = limit;
  554. dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
  555. mc->mc_vram_size >> 20, mc->vram_start,
  556. mc->vram_end, mc->real_vram_size >> 20);
  557. }
  558. /**
  559. * amdgpu_gart_location - try to find GTT location
  560. * @adev: amdgpu device structure holding all necessary informations
  561. * @mc: memory controller structure holding memory informations
  562. *
  563. * Function will place try to place GTT before or after VRAM.
  564. *
  565. * If GTT size is bigger than space left then we ajust GTT size.
  566. * Thus function will never fails.
  567. *
  568. * FIXME: when reducing GTT size align new size on power of 2.
  569. */
  570. void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
  571. {
  572. u64 size_af, size_bf;
  573. size_af = adev->mc.mc_mask - mc->vram_end;
  574. size_bf = mc->vram_start;
  575. if (size_bf > size_af) {
  576. if (mc->gart_size > size_bf) {
  577. dev_warn(adev->dev, "limiting GTT\n");
  578. mc->gart_size = size_bf;
  579. }
  580. mc->gart_start = 0;
  581. } else {
  582. if (mc->gart_size > size_af) {
  583. dev_warn(adev->dev, "limiting GTT\n");
  584. mc->gart_size = size_af;
  585. }
  586. mc->gart_start = mc->vram_end + 1;
  587. }
  588. mc->gart_end = mc->gart_start + mc->gart_size - 1;
  589. dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
  590. mc->gart_size >> 20, mc->gart_start, mc->gart_end);
  591. }
  592. /*
  593. * GPU helpers function.
  594. */
  595. /**
  596. * amdgpu_need_post - check if the hw need post or not
  597. *
  598. * @adev: amdgpu_device pointer
  599. *
  600. * Check if the asic has been initialized (all asics) at driver startup
  601. * or post is needed if hw reset is performed.
  602. * Returns true if need or false if not.
  603. */
  604. bool amdgpu_need_post(struct amdgpu_device *adev)
  605. {
  606. uint32_t reg;
  607. if (adev->has_hw_reset) {
  608. adev->has_hw_reset = false;
  609. return true;
  610. }
  611. /* bios scratch used on CIK+ */
  612. if (adev->asic_type >= CHIP_BONAIRE)
  613. return amdgpu_atombios_scratch_need_asic_init(adev);
  614. /* check MEM_SIZE for older asics */
  615. reg = amdgpu_asic_get_config_memsize(adev);
  616. if ((reg != 0) && (reg != 0xffffffff))
  617. return false;
  618. return true;
  619. }
  620. static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
  621. {
  622. if (amdgpu_sriov_vf(adev))
  623. return false;
  624. if (amdgpu_passthrough(adev)) {
  625. /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
  626. * some old smc fw still need driver do vPost otherwise gpu hang, while
  627. * those smc fw version above 22.15 doesn't have this flaw, so we force
  628. * vpost executed for smc version below 22.15
  629. */
  630. if (adev->asic_type == CHIP_FIJI) {
  631. int err;
  632. uint32_t fw_ver;
  633. err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
  634. /* force vPost if error occured */
  635. if (err)
  636. return true;
  637. fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
  638. if (fw_ver < 0x00160e00)
  639. return true;
  640. }
  641. }
  642. return amdgpu_need_post(adev);
  643. }
  644. /**
  645. * amdgpu_dummy_page_init - init dummy page used by the driver
  646. *
  647. * @adev: amdgpu_device pointer
  648. *
  649. * Allocate the dummy page used by the driver (all asics).
  650. * This dummy page is used by the driver as a filler for gart entries
  651. * when pages are taken out of the GART
  652. * Returns 0 on sucess, -ENOMEM on failure.
  653. */
  654. int amdgpu_dummy_page_init(struct amdgpu_device *adev)
  655. {
  656. if (adev->dummy_page.page)
  657. return 0;
  658. adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
  659. if (adev->dummy_page.page == NULL)
  660. return -ENOMEM;
  661. adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
  662. 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  663. if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
  664. dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
  665. __free_page(adev->dummy_page.page);
  666. adev->dummy_page.page = NULL;
  667. return -ENOMEM;
  668. }
  669. return 0;
  670. }
  671. /**
  672. * amdgpu_dummy_page_fini - free dummy page used by the driver
  673. *
  674. * @adev: amdgpu_device pointer
  675. *
  676. * Frees the dummy page used by the driver (all asics).
  677. */
  678. void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
  679. {
  680. if (adev->dummy_page.page == NULL)
  681. return;
  682. pci_unmap_page(adev->pdev, adev->dummy_page.addr,
  683. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  684. __free_page(adev->dummy_page.page);
  685. adev->dummy_page.page = NULL;
  686. }
  687. /* ATOM accessor methods */
  688. /*
  689. * ATOM is an interpreted byte code stored in tables in the vbios. The
  690. * driver registers callbacks to access registers and the interpreter
  691. * in the driver parses the tables and executes then to program specific
  692. * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
  693. * atombios.h, and atom.c
  694. */
  695. /**
  696. * cail_pll_read - read PLL register
  697. *
  698. * @info: atom card_info pointer
  699. * @reg: PLL register offset
  700. *
  701. * Provides a PLL register accessor for the atom interpreter (r4xx+).
  702. * Returns the value of the PLL register.
  703. */
  704. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  705. {
  706. return 0;
  707. }
  708. /**
  709. * cail_pll_write - write PLL register
  710. *
  711. * @info: atom card_info pointer
  712. * @reg: PLL register offset
  713. * @val: value to write to the pll register
  714. *
  715. * Provides a PLL register accessor for the atom interpreter (r4xx+).
  716. */
  717. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  718. {
  719. }
  720. /**
  721. * cail_mc_read - read MC (Memory Controller) register
  722. *
  723. * @info: atom card_info pointer
  724. * @reg: MC register offset
  725. *
  726. * Provides an MC register accessor for the atom interpreter (r4xx+).
  727. * Returns the value of the MC register.
  728. */
  729. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  730. {
  731. return 0;
  732. }
  733. /**
  734. * cail_mc_write - write MC (Memory Controller) register
  735. *
  736. * @info: atom card_info pointer
  737. * @reg: MC register offset
  738. * @val: value to write to the pll register
  739. *
  740. * Provides a MC register accessor for the atom interpreter (r4xx+).
  741. */
  742. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  743. {
  744. }
  745. /**
  746. * cail_reg_write - write MMIO register
  747. *
  748. * @info: atom card_info pointer
  749. * @reg: MMIO register offset
  750. * @val: value to write to the pll register
  751. *
  752. * Provides a MMIO register accessor for the atom interpreter (r4xx+).
  753. */
  754. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  755. {
  756. struct amdgpu_device *adev = info->dev->dev_private;
  757. WREG32(reg, val);
  758. }
  759. /**
  760. * cail_reg_read - read MMIO register
  761. *
  762. * @info: atom card_info pointer
  763. * @reg: MMIO register offset
  764. *
  765. * Provides an MMIO register accessor for the atom interpreter (r4xx+).
  766. * Returns the value of the MMIO register.
  767. */
  768. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  769. {
  770. struct amdgpu_device *adev = info->dev->dev_private;
  771. uint32_t r;
  772. r = RREG32(reg);
  773. return r;
  774. }
  775. /**
  776. * cail_ioreg_write - write IO register
  777. *
  778. * @info: atom card_info pointer
  779. * @reg: IO register offset
  780. * @val: value to write to the pll register
  781. *
  782. * Provides a IO register accessor for the atom interpreter (r4xx+).
  783. */
  784. static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
  785. {
  786. struct amdgpu_device *adev = info->dev->dev_private;
  787. WREG32_IO(reg, val);
  788. }
  789. /**
  790. * cail_ioreg_read - read IO register
  791. *
  792. * @info: atom card_info pointer
  793. * @reg: IO register offset
  794. *
  795. * Provides an IO register accessor for the atom interpreter (r4xx+).
  796. * Returns the value of the IO register.
  797. */
  798. static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
  799. {
  800. struct amdgpu_device *adev = info->dev->dev_private;
  801. uint32_t r;
  802. r = RREG32_IO(reg);
  803. return r;
  804. }
  805. /**
  806. * amdgpu_atombios_fini - free the driver info and callbacks for atombios
  807. *
  808. * @adev: amdgpu_device pointer
  809. *
  810. * Frees the driver info and register access callbacks for the ATOM
  811. * interpreter (r4xx+).
  812. * Called at driver shutdown.
  813. */
  814. static void amdgpu_atombios_fini(struct amdgpu_device *adev)
  815. {
  816. if (adev->mode_info.atom_context) {
  817. kfree(adev->mode_info.atom_context->scratch);
  818. kfree(adev->mode_info.atom_context->iio);
  819. }
  820. kfree(adev->mode_info.atom_context);
  821. adev->mode_info.atom_context = NULL;
  822. kfree(adev->mode_info.atom_card_info);
  823. adev->mode_info.atom_card_info = NULL;
  824. }
  825. /**
  826. * amdgpu_atombios_init - init the driver info and callbacks for atombios
  827. *
  828. * @adev: amdgpu_device pointer
  829. *
  830. * Initializes the driver info and register access callbacks for the
  831. * ATOM interpreter (r4xx+).
  832. * Returns 0 on sucess, -ENOMEM on failure.
  833. * Called at driver startup.
  834. */
  835. static int amdgpu_atombios_init(struct amdgpu_device *adev)
  836. {
  837. struct card_info *atom_card_info =
  838. kzalloc(sizeof(struct card_info), GFP_KERNEL);
  839. if (!atom_card_info)
  840. return -ENOMEM;
  841. adev->mode_info.atom_card_info = atom_card_info;
  842. atom_card_info->dev = adev->ddev;
  843. atom_card_info->reg_read = cail_reg_read;
  844. atom_card_info->reg_write = cail_reg_write;
  845. /* needed for iio ops */
  846. if (adev->rio_mem) {
  847. atom_card_info->ioreg_read = cail_ioreg_read;
  848. atom_card_info->ioreg_write = cail_ioreg_write;
  849. } else {
  850. DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
  851. atom_card_info->ioreg_read = cail_reg_read;
  852. atom_card_info->ioreg_write = cail_reg_write;
  853. }
  854. atom_card_info->mc_read = cail_mc_read;
  855. atom_card_info->mc_write = cail_mc_write;
  856. atom_card_info->pll_read = cail_pll_read;
  857. atom_card_info->pll_write = cail_pll_write;
  858. adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
  859. if (!adev->mode_info.atom_context) {
  860. amdgpu_atombios_fini(adev);
  861. return -ENOMEM;
  862. }
  863. mutex_init(&adev->mode_info.atom_context->mutex);
  864. if (adev->is_atom_fw) {
  865. amdgpu_atomfirmware_scratch_regs_init(adev);
  866. amdgpu_atomfirmware_allocate_fb_scratch(adev);
  867. } else {
  868. amdgpu_atombios_scratch_regs_init(adev);
  869. amdgpu_atombios_allocate_fb_scratch(adev);
  870. }
  871. return 0;
  872. }
  873. /* if we get transitioned to only one device, take VGA back */
  874. /**
  875. * amdgpu_vga_set_decode - enable/disable vga decode
  876. *
  877. * @cookie: amdgpu_device pointer
  878. * @state: enable/disable vga decode
  879. *
  880. * Enable/disable vga decode (all asics).
  881. * Returns VGA resource flags.
  882. */
  883. static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
  884. {
  885. struct amdgpu_device *adev = cookie;
  886. amdgpu_asic_set_vga_state(adev, state);
  887. if (state)
  888. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  889. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  890. else
  891. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  892. }
  893. static void amdgpu_check_block_size(struct amdgpu_device *adev)
  894. {
  895. /* defines number of bits in page table versus page directory,
  896. * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
  897. * page table and the remaining bits are in the page directory */
  898. if (amdgpu_vm_block_size == -1)
  899. return;
  900. if (amdgpu_vm_block_size < 9) {
  901. dev_warn(adev->dev, "VM page table size (%d) too small\n",
  902. amdgpu_vm_block_size);
  903. goto def_value;
  904. }
  905. if (amdgpu_vm_block_size > 24 ||
  906. (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
  907. dev_warn(adev->dev, "VM page table size (%d) too large\n",
  908. amdgpu_vm_block_size);
  909. goto def_value;
  910. }
  911. return;
  912. def_value:
  913. amdgpu_vm_block_size = -1;
  914. }
  915. static void amdgpu_check_vm_size(struct amdgpu_device *adev)
  916. {
  917. /* no need to check the default value */
  918. if (amdgpu_vm_size == -1)
  919. return;
  920. if (!is_power_of_2(amdgpu_vm_size)) {
  921. dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
  922. amdgpu_vm_size);
  923. goto def_value;
  924. }
  925. if (amdgpu_vm_size < 1) {
  926. dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
  927. amdgpu_vm_size);
  928. goto def_value;
  929. }
  930. /*
  931. * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
  932. */
  933. if (amdgpu_vm_size > 1024) {
  934. dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
  935. amdgpu_vm_size);
  936. goto def_value;
  937. }
  938. return;
  939. def_value:
  940. amdgpu_vm_size = -1;
  941. }
  942. /**
  943. * amdgpu_check_arguments - validate module params
  944. *
  945. * @adev: amdgpu_device pointer
  946. *
  947. * Validates certain module parameters and updates
  948. * the associated values used by the driver (all asics).
  949. */
  950. static void amdgpu_check_arguments(struct amdgpu_device *adev)
  951. {
  952. if (amdgpu_sched_jobs < 4) {
  953. dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
  954. amdgpu_sched_jobs);
  955. amdgpu_sched_jobs = 4;
  956. } else if (!is_power_of_2(amdgpu_sched_jobs)){
  957. dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
  958. amdgpu_sched_jobs);
  959. amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
  960. }
  961. if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
  962. /* gart size must be greater or equal to 32M */
  963. dev_warn(adev->dev, "gart size (%d) too small\n",
  964. amdgpu_gart_size);
  965. amdgpu_gart_size = -1;
  966. }
  967. if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
  968. /* gtt size must be greater or equal to 32M */
  969. dev_warn(adev->dev, "gtt size (%d) too small\n",
  970. amdgpu_gtt_size);
  971. amdgpu_gtt_size = -1;
  972. }
  973. /* valid range is between 4 and 9 inclusive */
  974. if (amdgpu_vm_fragment_size != -1 &&
  975. (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
  976. dev_warn(adev->dev, "valid range is between 4 and 9\n");
  977. amdgpu_vm_fragment_size = -1;
  978. }
  979. amdgpu_check_vm_size(adev);
  980. amdgpu_check_block_size(adev);
  981. if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
  982. !is_power_of_2(amdgpu_vram_page_split))) {
  983. dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
  984. amdgpu_vram_page_split);
  985. amdgpu_vram_page_split = 1024;
  986. }
  987. }
  988. /**
  989. * amdgpu_switcheroo_set_state - set switcheroo state
  990. *
  991. * @pdev: pci dev pointer
  992. * @state: vga_switcheroo state
  993. *
  994. * Callback for the switcheroo driver. Suspends or resumes the
  995. * the asics before or after it is powered up using ACPI methods.
  996. */
  997. static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
  998. {
  999. struct drm_device *dev = pci_get_drvdata(pdev);
  1000. if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
  1001. return;
  1002. if (state == VGA_SWITCHEROO_ON) {
  1003. pr_info("amdgpu: switched on\n");
  1004. /* don't suspend or resume card normally */
  1005. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  1006. amdgpu_device_resume(dev, true, true);
  1007. dev->switch_power_state = DRM_SWITCH_POWER_ON;
  1008. drm_kms_helper_poll_enable(dev);
  1009. } else {
  1010. pr_info("amdgpu: switched off\n");
  1011. drm_kms_helper_poll_disable(dev);
  1012. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  1013. amdgpu_device_suspend(dev, true, true);
  1014. dev->switch_power_state = DRM_SWITCH_POWER_OFF;
  1015. }
  1016. }
  1017. /**
  1018. * amdgpu_switcheroo_can_switch - see if switcheroo state can change
  1019. *
  1020. * @pdev: pci dev pointer
  1021. *
  1022. * Callback for the switcheroo driver. Check of the switcheroo
  1023. * state can be changed.
  1024. * Returns true if the state can be changed, false if not.
  1025. */
  1026. static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
  1027. {
  1028. struct drm_device *dev = pci_get_drvdata(pdev);
  1029. /*
  1030. * FIXME: open_count is protected by drm_global_mutex but that would lead to
  1031. * locking inversion with the driver load path. And the access here is
  1032. * completely racy anyway. So don't bother with locking for now.
  1033. */
  1034. return dev->open_count == 0;
  1035. }
  1036. static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
  1037. .set_gpu_state = amdgpu_switcheroo_set_state,
  1038. .reprobe = NULL,
  1039. .can_switch = amdgpu_switcheroo_can_switch,
  1040. };
  1041. int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
  1042. enum amd_ip_block_type block_type,
  1043. enum amd_clockgating_state state)
  1044. {
  1045. int i, r = 0;
  1046. for (i = 0; i < adev->num_ip_blocks; i++) {
  1047. if (!adev->ip_blocks[i].status.valid)
  1048. continue;
  1049. if (adev->ip_blocks[i].version->type != block_type)
  1050. continue;
  1051. if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
  1052. continue;
  1053. r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
  1054. (void *)adev, state);
  1055. if (r)
  1056. DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
  1057. adev->ip_blocks[i].version->funcs->name, r);
  1058. }
  1059. return r;
  1060. }
  1061. int amdgpu_set_powergating_state(struct amdgpu_device *adev,
  1062. enum amd_ip_block_type block_type,
  1063. enum amd_powergating_state state)
  1064. {
  1065. int i, r = 0;
  1066. for (i = 0; i < adev->num_ip_blocks; i++) {
  1067. if (!adev->ip_blocks[i].status.valid)
  1068. continue;
  1069. if (adev->ip_blocks[i].version->type != block_type)
  1070. continue;
  1071. if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
  1072. continue;
  1073. r = adev->ip_blocks[i].version->funcs->set_powergating_state(
  1074. (void *)adev, state);
  1075. if (r)
  1076. DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
  1077. adev->ip_blocks[i].version->funcs->name, r);
  1078. }
  1079. return r;
  1080. }
  1081. void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
  1082. {
  1083. int i;
  1084. for (i = 0; i < adev->num_ip_blocks; i++) {
  1085. if (!adev->ip_blocks[i].status.valid)
  1086. continue;
  1087. if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
  1088. adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
  1089. }
  1090. }
  1091. int amdgpu_wait_for_idle(struct amdgpu_device *adev,
  1092. enum amd_ip_block_type block_type)
  1093. {
  1094. int i, r;
  1095. for (i = 0; i < adev->num_ip_blocks; i++) {
  1096. if (!adev->ip_blocks[i].status.valid)
  1097. continue;
  1098. if (adev->ip_blocks[i].version->type == block_type) {
  1099. r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
  1100. if (r)
  1101. return r;
  1102. break;
  1103. }
  1104. }
  1105. return 0;
  1106. }
  1107. bool amdgpu_is_idle(struct amdgpu_device *adev,
  1108. enum amd_ip_block_type block_type)
  1109. {
  1110. int i;
  1111. for (i = 0; i < adev->num_ip_blocks; i++) {
  1112. if (!adev->ip_blocks[i].status.valid)
  1113. continue;
  1114. if (adev->ip_blocks[i].version->type == block_type)
  1115. return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
  1116. }
  1117. return true;
  1118. }
  1119. struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
  1120. enum amd_ip_block_type type)
  1121. {
  1122. int i;
  1123. for (i = 0; i < adev->num_ip_blocks; i++)
  1124. if (adev->ip_blocks[i].version->type == type)
  1125. return &adev->ip_blocks[i];
  1126. return NULL;
  1127. }
  1128. /**
  1129. * amdgpu_ip_block_version_cmp
  1130. *
  1131. * @adev: amdgpu_device pointer
  1132. * @type: enum amd_ip_block_type
  1133. * @major: major version
  1134. * @minor: minor version
  1135. *
  1136. * return 0 if equal or greater
  1137. * return 1 if smaller or the ip_block doesn't exist
  1138. */
  1139. int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
  1140. enum amd_ip_block_type type,
  1141. u32 major, u32 minor)
  1142. {
  1143. struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
  1144. if (ip_block && ((ip_block->version->major > major) ||
  1145. ((ip_block->version->major == major) &&
  1146. (ip_block->version->minor >= minor))))
  1147. return 0;
  1148. return 1;
  1149. }
  1150. /**
  1151. * amdgpu_ip_block_add
  1152. *
  1153. * @adev: amdgpu_device pointer
  1154. * @ip_block_version: pointer to the IP to add
  1155. *
  1156. * Adds the IP block driver information to the collection of IPs
  1157. * on the asic.
  1158. */
  1159. int amdgpu_ip_block_add(struct amdgpu_device *adev,
  1160. const struct amdgpu_ip_block_version *ip_block_version)
  1161. {
  1162. if (!ip_block_version)
  1163. return -EINVAL;
  1164. DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
  1165. ip_block_version->funcs->name);
  1166. adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
  1167. return 0;
  1168. }
  1169. static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
  1170. {
  1171. adev->enable_virtual_display = false;
  1172. if (amdgpu_virtual_display) {
  1173. struct drm_device *ddev = adev->ddev;
  1174. const char *pci_address_name = pci_name(ddev->pdev);
  1175. char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
  1176. pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
  1177. pciaddstr_tmp = pciaddstr;
  1178. while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
  1179. pciaddname = strsep(&pciaddname_tmp, ",");
  1180. if (!strcmp("all", pciaddname)
  1181. || !strcmp(pci_address_name, pciaddname)) {
  1182. long num_crtc;
  1183. int res = -1;
  1184. adev->enable_virtual_display = true;
  1185. if (pciaddname_tmp)
  1186. res = kstrtol(pciaddname_tmp, 10,
  1187. &num_crtc);
  1188. if (!res) {
  1189. if (num_crtc < 1)
  1190. num_crtc = 1;
  1191. if (num_crtc > 6)
  1192. num_crtc = 6;
  1193. adev->mode_info.num_crtc = num_crtc;
  1194. } else {
  1195. adev->mode_info.num_crtc = 1;
  1196. }
  1197. break;
  1198. }
  1199. }
  1200. DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
  1201. amdgpu_virtual_display, pci_address_name,
  1202. adev->enable_virtual_display, adev->mode_info.num_crtc);
  1203. kfree(pciaddstr);
  1204. }
  1205. }
  1206. static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
  1207. {
  1208. const char *chip_name;
  1209. char fw_name[30];
  1210. int err;
  1211. const struct gpu_info_firmware_header_v1_0 *hdr;
  1212. adev->firmware.gpu_info_fw = NULL;
  1213. switch (adev->asic_type) {
  1214. case CHIP_TOPAZ:
  1215. case CHIP_TONGA:
  1216. case CHIP_FIJI:
  1217. case CHIP_POLARIS11:
  1218. case CHIP_POLARIS10:
  1219. case CHIP_POLARIS12:
  1220. case CHIP_CARRIZO:
  1221. case CHIP_STONEY:
  1222. #ifdef CONFIG_DRM_AMDGPU_SI
  1223. case CHIP_VERDE:
  1224. case CHIP_TAHITI:
  1225. case CHIP_PITCAIRN:
  1226. case CHIP_OLAND:
  1227. case CHIP_HAINAN:
  1228. #endif
  1229. #ifdef CONFIG_DRM_AMDGPU_CIK
  1230. case CHIP_BONAIRE:
  1231. case CHIP_HAWAII:
  1232. case CHIP_KAVERI:
  1233. case CHIP_KABINI:
  1234. case CHIP_MULLINS:
  1235. #endif
  1236. default:
  1237. return 0;
  1238. case CHIP_VEGA10:
  1239. chip_name = "vega10";
  1240. break;
  1241. case CHIP_RAVEN:
  1242. chip_name = "raven";
  1243. break;
  1244. }
  1245. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
  1246. err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
  1247. if (err) {
  1248. dev_err(adev->dev,
  1249. "Failed to load gpu_info firmware \"%s\"\n",
  1250. fw_name);
  1251. goto out;
  1252. }
  1253. err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
  1254. if (err) {
  1255. dev_err(adev->dev,
  1256. "Failed to validate gpu_info firmware \"%s\"\n",
  1257. fw_name);
  1258. goto out;
  1259. }
  1260. hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
  1261. amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
  1262. switch (hdr->version_major) {
  1263. case 1:
  1264. {
  1265. const struct gpu_info_firmware_v1_0 *gpu_info_fw =
  1266. (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
  1267. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  1268. adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
  1269. adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
  1270. adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
  1271. adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
  1272. adev->gfx.config.max_texture_channel_caches =
  1273. le32_to_cpu(gpu_info_fw->gc_num_tccs);
  1274. adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
  1275. adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
  1276. adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
  1277. adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
  1278. adev->gfx.config.double_offchip_lds_buf =
  1279. le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
  1280. adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
  1281. adev->gfx.cu_info.max_waves_per_simd =
  1282. le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
  1283. adev->gfx.cu_info.max_scratch_slots_per_cu =
  1284. le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
  1285. adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
  1286. break;
  1287. }
  1288. default:
  1289. dev_err(adev->dev,
  1290. "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
  1291. err = -EINVAL;
  1292. goto out;
  1293. }
  1294. out:
  1295. return err;
  1296. }
  1297. static int amdgpu_early_init(struct amdgpu_device *adev)
  1298. {
  1299. int i, r;
  1300. amdgpu_device_enable_virtual_display(adev);
  1301. switch (adev->asic_type) {
  1302. case CHIP_TOPAZ:
  1303. case CHIP_TONGA:
  1304. case CHIP_FIJI:
  1305. case CHIP_POLARIS11:
  1306. case CHIP_POLARIS10:
  1307. case CHIP_POLARIS12:
  1308. case CHIP_CARRIZO:
  1309. case CHIP_STONEY:
  1310. if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
  1311. adev->family = AMDGPU_FAMILY_CZ;
  1312. else
  1313. adev->family = AMDGPU_FAMILY_VI;
  1314. r = vi_set_ip_blocks(adev);
  1315. if (r)
  1316. return r;
  1317. break;
  1318. #ifdef CONFIG_DRM_AMDGPU_SI
  1319. case CHIP_VERDE:
  1320. case CHIP_TAHITI:
  1321. case CHIP_PITCAIRN:
  1322. case CHIP_OLAND:
  1323. case CHIP_HAINAN:
  1324. adev->family = AMDGPU_FAMILY_SI;
  1325. r = si_set_ip_blocks(adev);
  1326. if (r)
  1327. return r;
  1328. break;
  1329. #endif
  1330. #ifdef CONFIG_DRM_AMDGPU_CIK
  1331. case CHIP_BONAIRE:
  1332. case CHIP_HAWAII:
  1333. case CHIP_KAVERI:
  1334. case CHIP_KABINI:
  1335. case CHIP_MULLINS:
  1336. if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
  1337. adev->family = AMDGPU_FAMILY_CI;
  1338. else
  1339. adev->family = AMDGPU_FAMILY_KV;
  1340. r = cik_set_ip_blocks(adev);
  1341. if (r)
  1342. return r;
  1343. break;
  1344. #endif
  1345. case CHIP_VEGA10:
  1346. case CHIP_RAVEN:
  1347. if (adev->asic_type == CHIP_RAVEN)
  1348. adev->family = AMDGPU_FAMILY_RV;
  1349. else
  1350. adev->family = AMDGPU_FAMILY_AI;
  1351. r = soc15_set_ip_blocks(adev);
  1352. if (r)
  1353. return r;
  1354. break;
  1355. default:
  1356. /* FIXME: not supported yet */
  1357. return -EINVAL;
  1358. }
  1359. r = amdgpu_device_parse_gpu_info_fw(adev);
  1360. if (r)
  1361. return r;
  1362. if (amdgpu_sriov_vf(adev)) {
  1363. r = amdgpu_virt_request_full_gpu(adev, true);
  1364. if (r)
  1365. return r;
  1366. }
  1367. for (i = 0; i < adev->num_ip_blocks; i++) {
  1368. if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
  1369. DRM_ERROR("disabled ip block: %d <%s>\n",
  1370. i, adev->ip_blocks[i].version->funcs->name);
  1371. adev->ip_blocks[i].status.valid = false;
  1372. } else {
  1373. if (adev->ip_blocks[i].version->funcs->early_init) {
  1374. r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
  1375. if (r == -ENOENT) {
  1376. adev->ip_blocks[i].status.valid = false;
  1377. } else if (r) {
  1378. DRM_ERROR("early_init of IP block <%s> failed %d\n",
  1379. adev->ip_blocks[i].version->funcs->name, r);
  1380. return r;
  1381. } else {
  1382. adev->ip_blocks[i].status.valid = true;
  1383. }
  1384. } else {
  1385. adev->ip_blocks[i].status.valid = true;
  1386. }
  1387. }
  1388. }
  1389. adev->cg_flags &= amdgpu_cg_mask;
  1390. adev->pg_flags &= amdgpu_pg_mask;
  1391. return 0;
  1392. }
  1393. static int amdgpu_init(struct amdgpu_device *adev)
  1394. {
  1395. int i, r;
  1396. for (i = 0; i < adev->num_ip_blocks; i++) {
  1397. if (!adev->ip_blocks[i].status.valid)
  1398. continue;
  1399. r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
  1400. if (r) {
  1401. DRM_ERROR("sw_init of IP block <%s> failed %d\n",
  1402. adev->ip_blocks[i].version->funcs->name, r);
  1403. return r;
  1404. }
  1405. adev->ip_blocks[i].status.sw = true;
  1406. /* need to do gmc hw init early so we can allocate gpu mem */
  1407. if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
  1408. r = amdgpu_vram_scratch_init(adev);
  1409. if (r) {
  1410. DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
  1411. return r;
  1412. }
  1413. r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
  1414. if (r) {
  1415. DRM_ERROR("hw_init %d failed %d\n", i, r);
  1416. return r;
  1417. }
  1418. r = amdgpu_wb_init(adev);
  1419. if (r) {
  1420. DRM_ERROR("amdgpu_wb_init failed %d\n", r);
  1421. return r;
  1422. }
  1423. adev->ip_blocks[i].status.hw = true;
  1424. /* right after GMC hw init, we create CSA */
  1425. if (amdgpu_sriov_vf(adev)) {
  1426. r = amdgpu_allocate_static_csa(adev);
  1427. if (r) {
  1428. DRM_ERROR("allocate CSA failed %d\n", r);
  1429. return r;
  1430. }
  1431. }
  1432. }
  1433. }
  1434. for (i = 0; i < adev->num_ip_blocks; i++) {
  1435. if (!adev->ip_blocks[i].status.sw)
  1436. continue;
  1437. /* gmc hw init is done early */
  1438. if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
  1439. continue;
  1440. r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
  1441. if (r) {
  1442. DRM_ERROR("hw_init of IP block <%s> failed %d\n",
  1443. adev->ip_blocks[i].version->funcs->name, r);
  1444. return r;
  1445. }
  1446. adev->ip_blocks[i].status.hw = true;
  1447. }
  1448. return 0;
  1449. }
  1450. static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
  1451. {
  1452. memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
  1453. }
  1454. static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
  1455. {
  1456. return !!memcmp(adev->gart.ptr, adev->reset_magic,
  1457. AMDGPU_RESET_MAGIC_NUM);
  1458. }
  1459. static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
  1460. {
  1461. int i = 0, r;
  1462. for (i = 0; i < adev->num_ip_blocks; i++) {
  1463. if (!adev->ip_blocks[i].status.valid)
  1464. continue;
  1465. /* skip CG for VCE/UVD, it's handled specially */
  1466. if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
  1467. adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
  1468. /* enable clockgating to save power */
  1469. r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
  1470. AMD_CG_STATE_GATE);
  1471. if (r) {
  1472. DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
  1473. adev->ip_blocks[i].version->funcs->name, r);
  1474. return r;
  1475. }
  1476. }
  1477. }
  1478. return 0;
  1479. }
  1480. static int amdgpu_late_init(struct amdgpu_device *adev)
  1481. {
  1482. int i = 0, r;
  1483. for (i = 0; i < adev->num_ip_blocks; i++) {
  1484. if (!adev->ip_blocks[i].status.valid)
  1485. continue;
  1486. if (adev->ip_blocks[i].version->funcs->late_init) {
  1487. r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
  1488. if (r) {
  1489. DRM_ERROR("late_init of IP block <%s> failed %d\n",
  1490. adev->ip_blocks[i].version->funcs->name, r);
  1491. return r;
  1492. }
  1493. adev->ip_blocks[i].status.late_initialized = true;
  1494. }
  1495. }
  1496. mod_delayed_work(system_wq, &adev->late_init_work,
  1497. msecs_to_jiffies(AMDGPU_RESUME_MS));
  1498. amdgpu_fill_reset_magic(adev);
  1499. return 0;
  1500. }
  1501. static int amdgpu_fini(struct amdgpu_device *adev)
  1502. {
  1503. int i, r;
  1504. /* need to disable SMC first */
  1505. for (i = 0; i < adev->num_ip_blocks; i++) {
  1506. if (!adev->ip_blocks[i].status.hw)
  1507. continue;
  1508. if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
  1509. /* ungate blocks before hw fini so that we can shutdown the blocks safely */
  1510. r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
  1511. AMD_CG_STATE_UNGATE);
  1512. if (r) {
  1513. DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
  1514. adev->ip_blocks[i].version->funcs->name, r);
  1515. return r;
  1516. }
  1517. r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
  1518. /* XXX handle errors */
  1519. if (r) {
  1520. DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
  1521. adev->ip_blocks[i].version->funcs->name, r);
  1522. }
  1523. adev->ip_blocks[i].status.hw = false;
  1524. break;
  1525. }
  1526. }
  1527. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1528. if (!adev->ip_blocks[i].status.hw)
  1529. continue;
  1530. if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
  1531. amdgpu_wb_fini(adev);
  1532. amdgpu_vram_scratch_fini(adev);
  1533. }
  1534. if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
  1535. adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
  1536. /* ungate blocks before hw fini so that we can shutdown the blocks safely */
  1537. r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
  1538. AMD_CG_STATE_UNGATE);
  1539. if (r) {
  1540. DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
  1541. adev->ip_blocks[i].version->funcs->name, r);
  1542. return r;
  1543. }
  1544. }
  1545. r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
  1546. /* XXX handle errors */
  1547. if (r) {
  1548. DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
  1549. adev->ip_blocks[i].version->funcs->name, r);
  1550. }
  1551. adev->ip_blocks[i].status.hw = false;
  1552. }
  1553. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1554. if (!adev->ip_blocks[i].status.sw)
  1555. continue;
  1556. r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
  1557. /* XXX handle errors */
  1558. if (r) {
  1559. DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
  1560. adev->ip_blocks[i].version->funcs->name, r);
  1561. }
  1562. adev->ip_blocks[i].status.sw = false;
  1563. adev->ip_blocks[i].status.valid = false;
  1564. }
  1565. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1566. if (!adev->ip_blocks[i].status.late_initialized)
  1567. continue;
  1568. if (adev->ip_blocks[i].version->funcs->late_fini)
  1569. adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
  1570. adev->ip_blocks[i].status.late_initialized = false;
  1571. }
  1572. if (amdgpu_sriov_vf(adev)) {
  1573. amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
  1574. amdgpu_virt_release_full_gpu(adev, false);
  1575. }
  1576. return 0;
  1577. }
  1578. static void amdgpu_late_init_func_handler(struct work_struct *work)
  1579. {
  1580. struct amdgpu_device *adev =
  1581. container_of(work, struct amdgpu_device, late_init_work.work);
  1582. amdgpu_late_set_cg_state(adev);
  1583. }
  1584. int amdgpu_suspend(struct amdgpu_device *adev)
  1585. {
  1586. int i, r;
  1587. if (amdgpu_sriov_vf(adev))
  1588. amdgpu_virt_request_full_gpu(adev, false);
  1589. /* ungate SMC block first */
  1590. r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
  1591. AMD_CG_STATE_UNGATE);
  1592. if (r) {
  1593. DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
  1594. }
  1595. for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
  1596. if (!adev->ip_blocks[i].status.valid)
  1597. continue;
  1598. /* ungate blocks so that suspend can properly shut them down */
  1599. if (i != AMD_IP_BLOCK_TYPE_SMC) {
  1600. r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
  1601. AMD_CG_STATE_UNGATE);
  1602. if (r) {
  1603. DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
  1604. adev->ip_blocks[i].version->funcs->name, r);
  1605. }
  1606. }
  1607. /* XXX handle errors */
  1608. r = adev->ip_blocks[i].version->funcs->suspend(adev);
  1609. /* XXX handle errors */
  1610. if (r) {
  1611. DRM_ERROR("suspend of IP block <%s> failed %d\n",
  1612. adev->ip_blocks[i].version->funcs->name, r);
  1613. }
  1614. }
  1615. if (amdgpu_sriov_vf(adev))
  1616. amdgpu_virt_release_full_gpu(adev, false);
  1617. return 0;
  1618. }
  1619. static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
  1620. {
  1621. int i, r;
  1622. static enum amd_ip_block_type ip_order[] = {
  1623. AMD_IP_BLOCK_TYPE_GMC,
  1624. AMD_IP_BLOCK_TYPE_COMMON,
  1625. AMD_IP_BLOCK_TYPE_IH,
  1626. };
  1627. for (i = 0; i < adev->num_ip_blocks; i++) {
  1628. int j;
  1629. struct amdgpu_ip_block *block;
  1630. for (j = 0; j < adev->num_ip_blocks; j++) {
  1631. block = &adev->ip_blocks[j];
  1632. if (block->version->type != ip_order[i] ||
  1633. !block->status.valid)
  1634. continue;
  1635. r = block->version->funcs->hw_init(adev);
  1636. DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
  1637. }
  1638. }
  1639. return 0;
  1640. }
  1641. static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
  1642. {
  1643. int i, r;
  1644. static enum amd_ip_block_type ip_order[] = {
  1645. AMD_IP_BLOCK_TYPE_SMC,
  1646. AMD_IP_BLOCK_TYPE_DCE,
  1647. AMD_IP_BLOCK_TYPE_GFX,
  1648. AMD_IP_BLOCK_TYPE_SDMA,
  1649. AMD_IP_BLOCK_TYPE_UVD,
  1650. AMD_IP_BLOCK_TYPE_VCE
  1651. };
  1652. for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
  1653. int j;
  1654. struct amdgpu_ip_block *block;
  1655. for (j = 0; j < adev->num_ip_blocks; j++) {
  1656. block = &adev->ip_blocks[j];
  1657. if (block->version->type != ip_order[i] ||
  1658. !block->status.valid)
  1659. continue;
  1660. r = block->version->funcs->hw_init(adev);
  1661. DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
  1662. }
  1663. }
  1664. return 0;
  1665. }
  1666. static int amdgpu_resume_phase1(struct amdgpu_device *adev)
  1667. {
  1668. int i, r;
  1669. for (i = 0; i < adev->num_ip_blocks; i++) {
  1670. if (!adev->ip_blocks[i].status.valid)
  1671. continue;
  1672. if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
  1673. adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
  1674. adev->ip_blocks[i].version->type ==
  1675. AMD_IP_BLOCK_TYPE_IH) {
  1676. r = adev->ip_blocks[i].version->funcs->resume(adev);
  1677. if (r) {
  1678. DRM_ERROR("resume of IP block <%s> failed %d\n",
  1679. adev->ip_blocks[i].version->funcs->name, r);
  1680. return r;
  1681. }
  1682. }
  1683. }
  1684. return 0;
  1685. }
  1686. static int amdgpu_resume_phase2(struct amdgpu_device *adev)
  1687. {
  1688. int i, r;
  1689. for (i = 0; i < adev->num_ip_blocks; i++) {
  1690. if (!adev->ip_blocks[i].status.valid)
  1691. continue;
  1692. if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
  1693. adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
  1694. adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
  1695. continue;
  1696. r = adev->ip_blocks[i].version->funcs->resume(adev);
  1697. if (r) {
  1698. DRM_ERROR("resume of IP block <%s> failed %d\n",
  1699. adev->ip_blocks[i].version->funcs->name, r);
  1700. return r;
  1701. }
  1702. }
  1703. return 0;
  1704. }
  1705. static int amdgpu_resume(struct amdgpu_device *adev)
  1706. {
  1707. int r;
  1708. r = amdgpu_resume_phase1(adev);
  1709. if (r)
  1710. return r;
  1711. r = amdgpu_resume_phase2(adev);
  1712. return r;
  1713. }
  1714. static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
  1715. {
  1716. if (adev->is_atom_fw) {
  1717. if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
  1718. adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
  1719. } else {
  1720. if (amdgpu_atombios_has_gpu_virtualization_table(adev))
  1721. adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
  1722. }
  1723. }
  1724. /**
  1725. * amdgpu_device_init - initialize the driver
  1726. *
  1727. * @adev: amdgpu_device pointer
  1728. * @pdev: drm dev pointer
  1729. * @pdev: pci dev pointer
  1730. * @flags: driver flags
  1731. *
  1732. * Initializes the driver info and hw (all asics).
  1733. * Returns 0 for success or an error on failure.
  1734. * Called at driver startup.
  1735. */
  1736. int amdgpu_device_init(struct amdgpu_device *adev,
  1737. struct drm_device *ddev,
  1738. struct pci_dev *pdev,
  1739. uint32_t flags)
  1740. {
  1741. int r, i;
  1742. bool runtime = false;
  1743. u32 max_MBps;
  1744. adev->shutdown = false;
  1745. adev->dev = &pdev->dev;
  1746. adev->ddev = ddev;
  1747. adev->pdev = pdev;
  1748. adev->flags = flags;
  1749. adev->asic_type = flags & AMD_ASIC_MASK;
  1750. adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
  1751. adev->mc.gart_size = 512 * 1024 * 1024;
  1752. adev->accel_working = false;
  1753. adev->num_rings = 0;
  1754. adev->mman.buffer_funcs = NULL;
  1755. adev->mman.buffer_funcs_ring = NULL;
  1756. adev->vm_manager.vm_pte_funcs = NULL;
  1757. adev->vm_manager.vm_pte_num_rings = 0;
  1758. adev->gart.gart_funcs = NULL;
  1759. adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
  1760. adev->smc_rreg = &amdgpu_invalid_rreg;
  1761. adev->smc_wreg = &amdgpu_invalid_wreg;
  1762. adev->pcie_rreg = &amdgpu_invalid_rreg;
  1763. adev->pcie_wreg = &amdgpu_invalid_wreg;
  1764. adev->pciep_rreg = &amdgpu_invalid_rreg;
  1765. adev->pciep_wreg = &amdgpu_invalid_wreg;
  1766. adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
  1767. adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
  1768. adev->didt_rreg = &amdgpu_invalid_rreg;
  1769. adev->didt_wreg = &amdgpu_invalid_wreg;
  1770. adev->gc_cac_rreg = &amdgpu_invalid_rreg;
  1771. adev->gc_cac_wreg = &amdgpu_invalid_wreg;
  1772. adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
  1773. adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
  1774. DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
  1775. amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
  1776. pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
  1777. /* mutex initialization are all done here so we
  1778. * can recall function without having locking issues */
  1779. atomic_set(&adev->irq.ih.lock, 0);
  1780. mutex_init(&adev->firmware.mutex);
  1781. mutex_init(&adev->pm.mutex);
  1782. mutex_init(&adev->gfx.gpu_clock_mutex);
  1783. mutex_init(&adev->srbm_mutex);
  1784. mutex_init(&adev->grbm_idx_mutex);
  1785. mutex_init(&adev->mn_lock);
  1786. hash_init(adev->mn_hash);
  1787. amdgpu_check_arguments(adev);
  1788. spin_lock_init(&adev->mmio_idx_lock);
  1789. spin_lock_init(&adev->smc_idx_lock);
  1790. spin_lock_init(&adev->pcie_idx_lock);
  1791. spin_lock_init(&adev->uvd_ctx_idx_lock);
  1792. spin_lock_init(&adev->didt_idx_lock);
  1793. spin_lock_init(&adev->gc_cac_idx_lock);
  1794. spin_lock_init(&adev->se_cac_idx_lock);
  1795. spin_lock_init(&adev->audio_endpt_idx_lock);
  1796. spin_lock_init(&adev->mm_stats.lock);
  1797. INIT_LIST_HEAD(&adev->shadow_list);
  1798. mutex_init(&adev->shadow_list_lock);
  1799. INIT_LIST_HEAD(&adev->gtt_list);
  1800. spin_lock_init(&adev->gtt_list_lock);
  1801. INIT_LIST_HEAD(&adev->ring_lru_list);
  1802. spin_lock_init(&adev->ring_lru_list_lock);
  1803. INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
  1804. /* Registers mapping */
  1805. /* TODO: block userspace mapping of io register */
  1806. if (adev->asic_type >= CHIP_BONAIRE) {
  1807. adev->rmmio_base = pci_resource_start(adev->pdev, 5);
  1808. adev->rmmio_size = pci_resource_len(adev->pdev, 5);
  1809. } else {
  1810. adev->rmmio_base = pci_resource_start(adev->pdev, 2);
  1811. adev->rmmio_size = pci_resource_len(adev->pdev, 2);
  1812. }
  1813. adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
  1814. if (adev->rmmio == NULL) {
  1815. return -ENOMEM;
  1816. }
  1817. DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
  1818. DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
  1819. if (adev->asic_type >= CHIP_BONAIRE)
  1820. /* doorbell bar mapping */
  1821. amdgpu_doorbell_init(adev);
  1822. /* io port mapping */
  1823. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  1824. if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
  1825. adev->rio_mem_size = pci_resource_len(adev->pdev, i);
  1826. adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
  1827. break;
  1828. }
  1829. }
  1830. if (adev->rio_mem == NULL)
  1831. DRM_INFO("PCI I/O BAR is not found.\n");
  1832. /* early init functions */
  1833. r = amdgpu_early_init(adev);
  1834. if (r)
  1835. return r;
  1836. /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
  1837. /* this will fail for cards that aren't VGA class devices, just
  1838. * ignore it */
  1839. vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
  1840. if (amdgpu_device_is_px(ddev))
  1841. runtime = true;
  1842. if (!pci_is_thunderbolt_attached(adev->pdev))
  1843. vga_switcheroo_register_client(adev->pdev,
  1844. &amdgpu_switcheroo_ops, runtime);
  1845. if (runtime)
  1846. vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
  1847. /* Read BIOS */
  1848. if (!amdgpu_get_bios(adev)) {
  1849. r = -EINVAL;
  1850. goto failed;
  1851. }
  1852. r = amdgpu_atombios_init(adev);
  1853. if (r) {
  1854. dev_err(adev->dev, "amdgpu_atombios_init failed\n");
  1855. amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
  1856. goto failed;
  1857. }
  1858. /* detect if we are with an SRIOV vbios */
  1859. amdgpu_device_detect_sriov_bios(adev);
  1860. /* Post card if necessary */
  1861. if (amdgpu_vpost_needed(adev)) {
  1862. if (!adev->bios) {
  1863. dev_err(adev->dev, "no vBIOS found\n");
  1864. amdgpu_vf_error_put(AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
  1865. r = -EINVAL;
  1866. goto failed;
  1867. }
  1868. DRM_INFO("GPU posting now...\n");
  1869. r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
  1870. if (r) {
  1871. dev_err(adev->dev, "gpu post error!\n");
  1872. amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_POST_ERROR, 0, 0);
  1873. goto failed;
  1874. }
  1875. } else {
  1876. DRM_INFO("GPU post is not needed\n");
  1877. }
  1878. if (adev->is_atom_fw) {
  1879. /* Initialize clocks */
  1880. r = amdgpu_atomfirmware_get_clock_info(adev);
  1881. if (r) {
  1882. dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
  1883. amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
  1884. goto failed;
  1885. }
  1886. } else {
  1887. /* Initialize clocks */
  1888. r = amdgpu_atombios_get_clock_info(adev);
  1889. if (r) {
  1890. dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
  1891. amdgpu_vf_error_put(AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
  1892. goto failed;
  1893. }
  1894. /* init i2c buses */
  1895. amdgpu_atombios_i2c_init(adev);
  1896. }
  1897. /* Fence driver */
  1898. r = amdgpu_fence_driver_init(adev);
  1899. if (r) {
  1900. dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
  1901. amdgpu_vf_error_put(AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
  1902. goto failed;
  1903. }
  1904. /* init the mode config */
  1905. drm_mode_config_init(adev->ddev);
  1906. r = amdgpu_init(adev);
  1907. if (r) {
  1908. dev_err(adev->dev, "amdgpu_init failed\n");
  1909. amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
  1910. amdgpu_fini(adev);
  1911. goto failed;
  1912. }
  1913. adev->accel_working = true;
  1914. amdgpu_vm_check_compute_bug(adev);
  1915. /* Initialize the buffer migration limit. */
  1916. if (amdgpu_moverate >= 0)
  1917. max_MBps = amdgpu_moverate;
  1918. else
  1919. max_MBps = 8; /* Allow 8 MB/s. */
  1920. /* Get a log2 for easy divisions. */
  1921. adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
  1922. r = amdgpu_ib_pool_init(adev);
  1923. if (r) {
  1924. dev_err(adev->dev, "IB initialization failed (%d).\n", r);
  1925. amdgpu_vf_error_put(AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
  1926. goto failed;
  1927. }
  1928. r = amdgpu_ib_ring_tests(adev);
  1929. if (r)
  1930. DRM_ERROR("ib ring test failed (%d).\n", r);
  1931. amdgpu_fbdev_init(adev);
  1932. r = amdgpu_gem_debugfs_init(adev);
  1933. if (r)
  1934. DRM_ERROR("registering gem debugfs failed (%d).\n", r);
  1935. r = amdgpu_debugfs_regs_init(adev);
  1936. if (r)
  1937. DRM_ERROR("registering register debugfs failed (%d).\n", r);
  1938. r = amdgpu_debugfs_test_ib_ring_init(adev);
  1939. if (r)
  1940. DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
  1941. r = amdgpu_debugfs_firmware_init(adev);
  1942. if (r)
  1943. DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
  1944. if ((amdgpu_testing & 1)) {
  1945. if (adev->accel_working)
  1946. amdgpu_test_moves(adev);
  1947. else
  1948. DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
  1949. }
  1950. if (amdgpu_benchmarking) {
  1951. if (adev->accel_working)
  1952. amdgpu_benchmark(adev, amdgpu_benchmarking);
  1953. else
  1954. DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
  1955. }
  1956. /* enable clockgating, etc. after ib tests, etc. since some blocks require
  1957. * explicit gating rather than handling it automatically.
  1958. */
  1959. r = amdgpu_late_init(adev);
  1960. if (r) {
  1961. dev_err(adev->dev, "amdgpu_late_init failed\n");
  1962. amdgpu_vf_error_put(AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
  1963. goto failed;
  1964. }
  1965. return 0;
  1966. failed:
  1967. amdgpu_vf_error_trans_all(adev);
  1968. if (runtime)
  1969. vga_switcheroo_fini_domain_pm_ops(adev->dev);
  1970. return r;
  1971. }
  1972. /**
  1973. * amdgpu_device_fini - tear down the driver
  1974. *
  1975. * @adev: amdgpu_device pointer
  1976. *
  1977. * Tear down the driver info (all asics).
  1978. * Called at driver shutdown.
  1979. */
  1980. void amdgpu_device_fini(struct amdgpu_device *adev)
  1981. {
  1982. int r;
  1983. DRM_INFO("amdgpu: finishing device.\n");
  1984. adev->shutdown = true;
  1985. if (adev->mode_info.mode_config_initialized)
  1986. drm_crtc_force_disable_all(adev->ddev);
  1987. /* evict vram memory */
  1988. amdgpu_bo_evict_vram(adev);
  1989. amdgpu_ib_pool_fini(adev);
  1990. amdgpu_fence_driver_fini(adev);
  1991. amdgpu_fbdev_fini(adev);
  1992. r = amdgpu_fini(adev);
  1993. if (adev->firmware.gpu_info_fw) {
  1994. release_firmware(adev->firmware.gpu_info_fw);
  1995. adev->firmware.gpu_info_fw = NULL;
  1996. }
  1997. adev->accel_working = false;
  1998. cancel_delayed_work_sync(&adev->late_init_work);
  1999. /* free i2c buses */
  2000. amdgpu_i2c_fini(adev);
  2001. amdgpu_atombios_fini(adev);
  2002. kfree(adev->bios);
  2003. adev->bios = NULL;
  2004. if (!pci_is_thunderbolt_attached(adev->pdev))
  2005. vga_switcheroo_unregister_client(adev->pdev);
  2006. if (adev->flags & AMD_IS_PX)
  2007. vga_switcheroo_fini_domain_pm_ops(adev->dev);
  2008. vga_client_register(adev->pdev, NULL, NULL, NULL);
  2009. if (adev->rio_mem)
  2010. pci_iounmap(adev->pdev, adev->rio_mem);
  2011. adev->rio_mem = NULL;
  2012. iounmap(adev->rmmio);
  2013. adev->rmmio = NULL;
  2014. if (adev->asic_type >= CHIP_BONAIRE)
  2015. amdgpu_doorbell_fini(adev);
  2016. amdgpu_debugfs_regs_cleanup(adev);
  2017. }
  2018. /*
  2019. * Suspend & resume.
  2020. */
  2021. /**
  2022. * amdgpu_device_suspend - initiate device suspend
  2023. *
  2024. * @pdev: drm dev pointer
  2025. * @state: suspend state
  2026. *
  2027. * Puts the hw in the suspend state (all asics).
  2028. * Returns 0 for success or an error on failure.
  2029. * Called at driver suspend.
  2030. */
  2031. int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
  2032. {
  2033. struct amdgpu_device *adev;
  2034. struct drm_crtc *crtc;
  2035. struct drm_connector *connector;
  2036. int r;
  2037. if (dev == NULL || dev->dev_private == NULL) {
  2038. return -ENODEV;
  2039. }
  2040. adev = dev->dev_private;
  2041. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  2042. return 0;
  2043. drm_kms_helper_poll_disable(dev);
  2044. /* turn off display hw */
  2045. drm_modeset_lock_all(dev);
  2046. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  2047. drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  2048. }
  2049. drm_modeset_unlock_all(dev);
  2050. amdgpu_amdkfd_suspend(adev);
  2051. /* unpin the front buffers and cursors */
  2052. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2053. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2054. struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
  2055. struct amdgpu_bo *robj;
  2056. if (amdgpu_crtc->cursor_bo) {
  2057. struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
  2058. r = amdgpu_bo_reserve(aobj, true);
  2059. if (r == 0) {
  2060. amdgpu_bo_unpin(aobj);
  2061. amdgpu_bo_unreserve(aobj);
  2062. }
  2063. }
  2064. if (rfb == NULL || rfb->obj == NULL) {
  2065. continue;
  2066. }
  2067. robj = gem_to_amdgpu_bo(rfb->obj);
  2068. /* don't unpin kernel fb objects */
  2069. if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
  2070. r = amdgpu_bo_reserve(robj, true);
  2071. if (r == 0) {
  2072. amdgpu_bo_unpin(robj);
  2073. amdgpu_bo_unreserve(robj);
  2074. }
  2075. }
  2076. }
  2077. /* evict vram memory */
  2078. amdgpu_bo_evict_vram(adev);
  2079. amdgpu_fence_driver_suspend(adev);
  2080. r = amdgpu_suspend(adev);
  2081. /* evict remaining vram memory
  2082. * This second call to evict vram is to evict the gart page table
  2083. * using the CPU.
  2084. */
  2085. amdgpu_bo_evict_vram(adev);
  2086. amdgpu_atombios_scratch_regs_save(adev);
  2087. pci_save_state(dev->pdev);
  2088. if (suspend) {
  2089. /* Shut down the device */
  2090. pci_disable_device(dev->pdev);
  2091. pci_set_power_state(dev->pdev, PCI_D3hot);
  2092. } else {
  2093. r = amdgpu_asic_reset(adev);
  2094. if (r)
  2095. DRM_ERROR("amdgpu asic reset failed\n");
  2096. }
  2097. if (fbcon) {
  2098. console_lock();
  2099. amdgpu_fbdev_set_suspend(adev, 1);
  2100. console_unlock();
  2101. }
  2102. return 0;
  2103. }
  2104. /**
  2105. * amdgpu_device_resume - initiate device resume
  2106. *
  2107. * @pdev: drm dev pointer
  2108. *
  2109. * Bring the hw back to operating state (all asics).
  2110. * Returns 0 for success or an error on failure.
  2111. * Called at driver resume.
  2112. */
  2113. int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
  2114. {
  2115. struct drm_connector *connector;
  2116. struct amdgpu_device *adev = dev->dev_private;
  2117. struct drm_crtc *crtc;
  2118. int r = 0;
  2119. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  2120. return 0;
  2121. if (fbcon)
  2122. console_lock();
  2123. if (resume) {
  2124. pci_set_power_state(dev->pdev, PCI_D0);
  2125. pci_restore_state(dev->pdev);
  2126. r = pci_enable_device(dev->pdev);
  2127. if (r)
  2128. goto unlock;
  2129. }
  2130. amdgpu_atombios_scratch_regs_restore(adev);
  2131. /* post card */
  2132. if (amdgpu_need_post(adev)) {
  2133. r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
  2134. if (r)
  2135. DRM_ERROR("amdgpu asic init failed\n");
  2136. }
  2137. r = amdgpu_resume(adev);
  2138. if (r) {
  2139. DRM_ERROR("amdgpu_resume failed (%d).\n", r);
  2140. goto unlock;
  2141. }
  2142. amdgpu_fence_driver_resume(adev);
  2143. if (resume) {
  2144. r = amdgpu_ib_ring_tests(adev);
  2145. if (r)
  2146. DRM_ERROR("ib ring test failed (%d).\n", r);
  2147. }
  2148. r = amdgpu_late_init(adev);
  2149. if (r)
  2150. goto unlock;
  2151. /* pin cursors */
  2152. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2153. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2154. if (amdgpu_crtc->cursor_bo) {
  2155. struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
  2156. r = amdgpu_bo_reserve(aobj, true);
  2157. if (r == 0) {
  2158. r = amdgpu_bo_pin(aobj,
  2159. AMDGPU_GEM_DOMAIN_VRAM,
  2160. &amdgpu_crtc->cursor_addr);
  2161. if (r != 0)
  2162. DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
  2163. amdgpu_bo_unreserve(aobj);
  2164. }
  2165. }
  2166. }
  2167. r = amdgpu_amdkfd_resume(adev);
  2168. if (r)
  2169. return r;
  2170. /* blat the mode back in */
  2171. if (fbcon) {
  2172. drm_helper_resume_force_mode(dev);
  2173. /* turn on display hw */
  2174. drm_modeset_lock_all(dev);
  2175. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  2176. drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  2177. }
  2178. drm_modeset_unlock_all(dev);
  2179. }
  2180. drm_kms_helper_poll_enable(dev);
  2181. /*
  2182. * Most of the connector probing functions try to acquire runtime pm
  2183. * refs to ensure that the GPU is powered on when connector polling is
  2184. * performed. Since we're calling this from a runtime PM callback,
  2185. * trying to acquire rpm refs will cause us to deadlock.
  2186. *
  2187. * Since we're guaranteed to be holding the rpm lock, it's safe to
  2188. * temporarily disable the rpm helpers so this doesn't deadlock us.
  2189. */
  2190. #ifdef CONFIG_PM
  2191. dev->dev->power.disable_depth++;
  2192. #endif
  2193. drm_helper_hpd_irq_event(dev);
  2194. #ifdef CONFIG_PM
  2195. dev->dev->power.disable_depth--;
  2196. #endif
  2197. if (fbcon)
  2198. amdgpu_fbdev_set_suspend(adev, 0);
  2199. unlock:
  2200. if (fbcon)
  2201. console_unlock();
  2202. return r;
  2203. }
  2204. static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
  2205. {
  2206. int i;
  2207. bool asic_hang = false;
  2208. for (i = 0; i < adev->num_ip_blocks; i++) {
  2209. if (!adev->ip_blocks[i].status.valid)
  2210. continue;
  2211. if (adev->ip_blocks[i].version->funcs->check_soft_reset)
  2212. adev->ip_blocks[i].status.hang =
  2213. adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
  2214. if (adev->ip_blocks[i].status.hang) {
  2215. DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
  2216. asic_hang = true;
  2217. }
  2218. }
  2219. return asic_hang;
  2220. }
  2221. static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
  2222. {
  2223. int i, r = 0;
  2224. for (i = 0; i < adev->num_ip_blocks; i++) {
  2225. if (!adev->ip_blocks[i].status.valid)
  2226. continue;
  2227. if (adev->ip_blocks[i].status.hang &&
  2228. adev->ip_blocks[i].version->funcs->pre_soft_reset) {
  2229. r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
  2230. if (r)
  2231. return r;
  2232. }
  2233. }
  2234. return 0;
  2235. }
  2236. static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
  2237. {
  2238. int i;
  2239. for (i = 0; i < adev->num_ip_blocks; i++) {
  2240. if (!adev->ip_blocks[i].status.valid)
  2241. continue;
  2242. if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
  2243. (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
  2244. (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
  2245. (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
  2246. if (adev->ip_blocks[i].status.hang) {
  2247. DRM_INFO("Some block need full reset!\n");
  2248. return true;
  2249. }
  2250. }
  2251. }
  2252. return false;
  2253. }
  2254. static int amdgpu_soft_reset(struct amdgpu_device *adev)
  2255. {
  2256. int i, r = 0;
  2257. for (i = 0; i < adev->num_ip_blocks; i++) {
  2258. if (!adev->ip_blocks[i].status.valid)
  2259. continue;
  2260. if (adev->ip_blocks[i].status.hang &&
  2261. adev->ip_blocks[i].version->funcs->soft_reset) {
  2262. r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
  2263. if (r)
  2264. return r;
  2265. }
  2266. }
  2267. return 0;
  2268. }
  2269. static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
  2270. {
  2271. int i, r = 0;
  2272. for (i = 0; i < adev->num_ip_blocks; i++) {
  2273. if (!adev->ip_blocks[i].status.valid)
  2274. continue;
  2275. if (adev->ip_blocks[i].status.hang &&
  2276. adev->ip_blocks[i].version->funcs->post_soft_reset)
  2277. r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
  2278. if (r)
  2279. return r;
  2280. }
  2281. return 0;
  2282. }
  2283. bool amdgpu_need_backup(struct amdgpu_device *adev)
  2284. {
  2285. if (adev->flags & AMD_IS_APU)
  2286. return false;
  2287. return amdgpu_lockup_timeout > 0 ? true : false;
  2288. }
  2289. static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
  2290. struct amdgpu_ring *ring,
  2291. struct amdgpu_bo *bo,
  2292. struct dma_fence **fence)
  2293. {
  2294. uint32_t domain;
  2295. int r;
  2296. if (!bo->shadow)
  2297. return 0;
  2298. r = amdgpu_bo_reserve(bo, true);
  2299. if (r)
  2300. return r;
  2301. domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
  2302. /* if bo has been evicted, then no need to recover */
  2303. if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
  2304. r = amdgpu_bo_validate(bo->shadow);
  2305. if (r) {
  2306. DRM_ERROR("bo validate failed!\n");
  2307. goto err;
  2308. }
  2309. r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
  2310. NULL, fence, true);
  2311. if (r) {
  2312. DRM_ERROR("recover page table failed!\n");
  2313. goto err;
  2314. }
  2315. }
  2316. err:
  2317. amdgpu_bo_unreserve(bo);
  2318. return r;
  2319. }
  2320. /**
  2321. * amdgpu_sriov_gpu_reset - reset the asic
  2322. *
  2323. * @adev: amdgpu device pointer
  2324. * @job: which job trigger hang
  2325. *
  2326. * Attempt the reset the GPU if it has hung (all asics).
  2327. * for SRIOV case.
  2328. * Returns 0 for success or an error on failure.
  2329. */
  2330. int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
  2331. {
  2332. int i, j, r = 0;
  2333. int resched;
  2334. struct amdgpu_bo *bo, *tmp;
  2335. struct amdgpu_ring *ring;
  2336. struct dma_fence *fence = NULL, *next = NULL;
  2337. mutex_lock(&adev->virt.lock_reset);
  2338. atomic_inc(&adev->gpu_reset_counter);
  2339. adev->gfx.in_reset = true;
  2340. /* block TTM */
  2341. resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
  2342. /* we start from the ring trigger GPU hang */
  2343. j = job ? job->ring->idx : 0;
  2344. /* block scheduler */
  2345. for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
  2346. ring = adev->rings[i % AMDGPU_MAX_RINGS];
  2347. if (!ring || !ring->sched.thread)
  2348. continue;
  2349. kthread_park(ring->sched.thread);
  2350. if (job && j != i)
  2351. continue;
  2352. /* here give the last chance to check if job removed from mirror-list
  2353. * since we already pay some time on kthread_park */
  2354. if (job && list_empty(&job->base.node)) {
  2355. kthread_unpark(ring->sched.thread);
  2356. goto give_up_reset;
  2357. }
  2358. if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))
  2359. amd_sched_job_kickout(&job->base);
  2360. /* only do job_reset on the hang ring if @job not NULL */
  2361. amd_sched_hw_job_reset(&ring->sched);
  2362. /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
  2363. amdgpu_fence_driver_force_completion_ring(ring);
  2364. }
  2365. /* request to take full control of GPU before re-initialization */
  2366. if (job)
  2367. amdgpu_virt_reset_gpu(adev);
  2368. else
  2369. amdgpu_virt_request_full_gpu(adev, true);
  2370. /* Resume IP prior to SMC */
  2371. amdgpu_sriov_reinit_early(adev);
  2372. /* we need recover gart prior to run SMC/CP/SDMA resume */
  2373. amdgpu_ttm_recover_gart(adev);
  2374. /* now we are okay to resume SMC/CP/SDMA */
  2375. amdgpu_sriov_reinit_late(adev);
  2376. amdgpu_irq_gpu_reset_resume_helper(adev);
  2377. if (amdgpu_ib_ring_tests(adev))
  2378. dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
  2379. /* release full control of GPU after ib test */
  2380. amdgpu_virt_release_full_gpu(adev, true);
  2381. DRM_INFO("recover vram bo from shadow\n");
  2382. ring = adev->mman.buffer_funcs_ring;
  2383. mutex_lock(&adev->shadow_list_lock);
  2384. list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
  2385. next = NULL;
  2386. amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
  2387. if (fence) {
  2388. r = dma_fence_wait(fence, false);
  2389. if (r) {
  2390. WARN(r, "recovery from shadow isn't completed\n");
  2391. break;
  2392. }
  2393. }
  2394. dma_fence_put(fence);
  2395. fence = next;
  2396. }
  2397. mutex_unlock(&adev->shadow_list_lock);
  2398. if (fence) {
  2399. r = dma_fence_wait(fence, false);
  2400. if (r)
  2401. WARN(r, "recovery from shadow isn't completed\n");
  2402. }
  2403. dma_fence_put(fence);
  2404. for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
  2405. ring = adev->rings[i % AMDGPU_MAX_RINGS];
  2406. if (!ring || !ring->sched.thread)
  2407. continue;
  2408. if (job && j != i) {
  2409. kthread_unpark(ring->sched.thread);
  2410. continue;
  2411. }
  2412. amd_sched_job_recovery(&ring->sched);
  2413. kthread_unpark(ring->sched.thread);
  2414. }
  2415. drm_helper_resume_force_mode(adev->ddev);
  2416. give_up_reset:
  2417. ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
  2418. if (r) {
  2419. /* bad news, how to tell it to userspace ? */
  2420. dev_info(adev->dev, "GPU reset failed\n");
  2421. } else {
  2422. dev_info(adev->dev, "GPU reset successed!\n");
  2423. }
  2424. adev->gfx.in_reset = false;
  2425. mutex_unlock(&adev->virt.lock_reset);
  2426. return r;
  2427. }
  2428. /**
  2429. * amdgpu_gpu_reset - reset the asic
  2430. *
  2431. * @adev: amdgpu device pointer
  2432. *
  2433. * Attempt the reset the GPU if it has hung (all asics).
  2434. * Returns 0 for success or an error on failure.
  2435. */
  2436. int amdgpu_gpu_reset(struct amdgpu_device *adev)
  2437. {
  2438. int i, r;
  2439. int resched;
  2440. bool need_full_reset, vram_lost = false;
  2441. if (!amdgpu_check_soft_reset(adev)) {
  2442. DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
  2443. return 0;
  2444. }
  2445. atomic_inc(&adev->gpu_reset_counter);
  2446. /* block TTM */
  2447. resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
  2448. /* block scheduler */
  2449. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  2450. struct amdgpu_ring *ring = adev->rings[i];
  2451. if (!ring || !ring->sched.thread)
  2452. continue;
  2453. kthread_park(ring->sched.thread);
  2454. amd_sched_hw_job_reset(&ring->sched);
  2455. }
  2456. /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
  2457. amdgpu_fence_driver_force_completion(adev);
  2458. need_full_reset = amdgpu_need_full_reset(adev);
  2459. if (!need_full_reset) {
  2460. amdgpu_pre_soft_reset(adev);
  2461. r = amdgpu_soft_reset(adev);
  2462. amdgpu_post_soft_reset(adev);
  2463. if (r || amdgpu_check_soft_reset(adev)) {
  2464. DRM_INFO("soft reset failed, will fallback to full reset!\n");
  2465. need_full_reset = true;
  2466. }
  2467. }
  2468. if (need_full_reset) {
  2469. r = amdgpu_suspend(adev);
  2470. retry:
  2471. amdgpu_atombios_scratch_regs_save(adev);
  2472. r = amdgpu_asic_reset(adev);
  2473. amdgpu_atombios_scratch_regs_restore(adev);
  2474. /* post card */
  2475. amdgpu_atom_asic_init(adev->mode_info.atom_context);
  2476. if (!r) {
  2477. dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
  2478. r = amdgpu_resume_phase1(adev);
  2479. if (r)
  2480. goto out;
  2481. vram_lost = amdgpu_check_vram_lost(adev);
  2482. if (vram_lost) {
  2483. DRM_ERROR("VRAM is lost!\n");
  2484. atomic_inc(&adev->vram_lost_counter);
  2485. }
  2486. r = amdgpu_ttm_recover_gart(adev);
  2487. if (r)
  2488. goto out;
  2489. r = amdgpu_resume_phase2(adev);
  2490. if (r)
  2491. goto out;
  2492. if (vram_lost)
  2493. amdgpu_fill_reset_magic(adev);
  2494. }
  2495. }
  2496. out:
  2497. if (!r) {
  2498. amdgpu_irq_gpu_reset_resume_helper(adev);
  2499. r = amdgpu_ib_ring_tests(adev);
  2500. if (r) {
  2501. dev_err(adev->dev, "ib ring test failed (%d).\n", r);
  2502. r = amdgpu_suspend(adev);
  2503. need_full_reset = true;
  2504. goto retry;
  2505. }
  2506. /**
  2507. * recovery vm page tables, since we cannot depend on VRAM is
  2508. * consistent after gpu full reset.
  2509. */
  2510. if (need_full_reset && amdgpu_need_backup(adev)) {
  2511. struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
  2512. struct amdgpu_bo *bo, *tmp;
  2513. struct dma_fence *fence = NULL, *next = NULL;
  2514. DRM_INFO("recover vram bo from shadow\n");
  2515. mutex_lock(&adev->shadow_list_lock);
  2516. list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
  2517. next = NULL;
  2518. amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
  2519. if (fence) {
  2520. r = dma_fence_wait(fence, false);
  2521. if (r) {
  2522. WARN(r, "recovery from shadow isn't completed\n");
  2523. break;
  2524. }
  2525. }
  2526. dma_fence_put(fence);
  2527. fence = next;
  2528. }
  2529. mutex_unlock(&adev->shadow_list_lock);
  2530. if (fence) {
  2531. r = dma_fence_wait(fence, false);
  2532. if (r)
  2533. WARN(r, "recovery from shadow isn't completed\n");
  2534. }
  2535. dma_fence_put(fence);
  2536. }
  2537. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  2538. struct amdgpu_ring *ring = adev->rings[i];
  2539. if (!ring || !ring->sched.thread)
  2540. continue;
  2541. amd_sched_job_recovery(&ring->sched);
  2542. kthread_unpark(ring->sched.thread);
  2543. }
  2544. } else {
  2545. dev_err(adev->dev, "asic resume failed (%d).\n", r);
  2546. amdgpu_vf_error_put(AMDGIM_ERROR_VF_ASIC_RESUME_FAIL, 0, r);
  2547. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  2548. if (adev->rings[i] && adev->rings[i]->sched.thread) {
  2549. kthread_unpark(adev->rings[i]->sched.thread);
  2550. }
  2551. }
  2552. }
  2553. drm_helper_resume_force_mode(adev->ddev);
  2554. ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
  2555. if (r) {
  2556. /* bad news, how to tell it to userspace ? */
  2557. dev_info(adev->dev, "GPU reset failed\n");
  2558. amdgpu_vf_error_put(AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
  2559. }
  2560. else {
  2561. dev_info(adev->dev, "GPU reset successed!\n");
  2562. }
  2563. amdgpu_vf_error_trans_all(adev);
  2564. return r;
  2565. }
  2566. void amdgpu_get_pcie_info(struct amdgpu_device *adev)
  2567. {
  2568. u32 mask;
  2569. int ret;
  2570. if (amdgpu_pcie_gen_cap)
  2571. adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
  2572. if (amdgpu_pcie_lane_cap)
  2573. adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
  2574. /* covers APUs as well */
  2575. if (pci_is_root_bus(adev->pdev->bus)) {
  2576. if (adev->pm.pcie_gen_mask == 0)
  2577. adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
  2578. if (adev->pm.pcie_mlw_mask == 0)
  2579. adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
  2580. return;
  2581. }
  2582. if (adev->pm.pcie_gen_mask == 0) {
  2583. ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
  2584. if (!ret) {
  2585. adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
  2586. CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
  2587. CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
  2588. if (mask & DRM_PCIE_SPEED_25)
  2589. adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
  2590. if (mask & DRM_PCIE_SPEED_50)
  2591. adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
  2592. if (mask & DRM_PCIE_SPEED_80)
  2593. adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
  2594. } else {
  2595. adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
  2596. }
  2597. }
  2598. if (adev->pm.pcie_mlw_mask == 0) {
  2599. ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
  2600. if (!ret) {
  2601. switch (mask) {
  2602. case 32:
  2603. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
  2604. CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
  2605. CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
  2606. CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  2607. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  2608. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  2609. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  2610. break;
  2611. case 16:
  2612. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
  2613. CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
  2614. CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  2615. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  2616. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  2617. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  2618. break;
  2619. case 12:
  2620. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
  2621. CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  2622. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  2623. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  2624. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  2625. break;
  2626. case 8:
  2627. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
  2628. CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  2629. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  2630. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  2631. break;
  2632. case 4:
  2633. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
  2634. CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  2635. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  2636. break;
  2637. case 2:
  2638. adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
  2639. CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
  2640. break;
  2641. case 1:
  2642. adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
  2643. break;
  2644. default:
  2645. break;
  2646. }
  2647. } else {
  2648. adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
  2649. }
  2650. }
  2651. }
  2652. /*
  2653. * Debugfs
  2654. */
  2655. int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
  2656. const struct drm_info_list *files,
  2657. unsigned nfiles)
  2658. {
  2659. unsigned i;
  2660. for (i = 0; i < adev->debugfs_count; i++) {
  2661. if (adev->debugfs[i].files == files) {
  2662. /* Already registered */
  2663. return 0;
  2664. }
  2665. }
  2666. i = adev->debugfs_count + 1;
  2667. if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
  2668. DRM_ERROR("Reached maximum number of debugfs components.\n");
  2669. DRM_ERROR("Report so we increase "
  2670. "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
  2671. return -EINVAL;
  2672. }
  2673. adev->debugfs[adev->debugfs_count].files = files;
  2674. adev->debugfs[adev->debugfs_count].num_files = nfiles;
  2675. adev->debugfs_count = i;
  2676. #if defined(CONFIG_DEBUG_FS)
  2677. drm_debugfs_create_files(files, nfiles,
  2678. adev->ddev->primary->debugfs_root,
  2679. adev->ddev->primary);
  2680. #endif
  2681. return 0;
  2682. }
  2683. #if defined(CONFIG_DEBUG_FS)
  2684. static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
  2685. size_t size, loff_t *pos)
  2686. {
  2687. struct amdgpu_device *adev = file_inode(f)->i_private;
  2688. ssize_t result = 0;
  2689. int r;
  2690. bool pm_pg_lock, use_bank;
  2691. unsigned instance_bank, sh_bank, se_bank;
  2692. if (size & 0x3 || *pos & 0x3)
  2693. return -EINVAL;
  2694. /* are we reading registers for which a PG lock is necessary? */
  2695. pm_pg_lock = (*pos >> 23) & 1;
  2696. if (*pos & (1ULL << 62)) {
  2697. se_bank = (*pos >> 24) & 0x3FF;
  2698. sh_bank = (*pos >> 34) & 0x3FF;
  2699. instance_bank = (*pos >> 44) & 0x3FF;
  2700. if (se_bank == 0x3FF)
  2701. se_bank = 0xFFFFFFFF;
  2702. if (sh_bank == 0x3FF)
  2703. sh_bank = 0xFFFFFFFF;
  2704. if (instance_bank == 0x3FF)
  2705. instance_bank = 0xFFFFFFFF;
  2706. use_bank = 1;
  2707. } else {
  2708. use_bank = 0;
  2709. }
  2710. *pos &= (1UL << 22) - 1;
  2711. if (use_bank) {
  2712. if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
  2713. (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
  2714. return -EINVAL;
  2715. mutex_lock(&adev->grbm_idx_mutex);
  2716. amdgpu_gfx_select_se_sh(adev, se_bank,
  2717. sh_bank, instance_bank);
  2718. }
  2719. if (pm_pg_lock)
  2720. mutex_lock(&adev->pm.mutex);
  2721. while (size) {
  2722. uint32_t value;
  2723. if (*pos > adev->rmmio_size)
  2724. goto end;
  2725. value = RREG32(*pos >> 2);
  2726. r = put_user(value, (uint32_t *)buf);
  2727. if (r) {
  2728. result = r;
  2729. goto end;
  2730. }
  2731. result += 4;
  2732. buf += 4;
  2733. *pos += 4;
  2734. size -= 4;
  2735. }
  2736. end:
  2737. if (use_bank) {
  2738. amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  2739. mutex_unlock(&adev->grbm_idx_mutex);
  2740. }
  2741. if (pm_pg_lock)
  2742. mutex_unlock(&adev->pm.mutex);
  2743. return result;
  2744. }
  2745. static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
  2746. size_t size, loff_t *pos)
  2747. {
  2748. struct amdgpu_device *adev = file_inode(f)->i_private;
  2749. ssize_t result = 0;
  2750. int r;
  2751. bool pm_pg_lock, use_bank;
  2752. unsigned instance_bank, sh_bank, se_bank;
  2753. if (size & 0x3 || *pos & 0x3)
  2754. return -EINVAL;
  2755. /* are we reading registers for which a PG lock is necessary? */
  2756. pm_pg_lock = (*pos >> 23) & 1;
  2757. if (*pos & (1ULL << 62)) {
  2758. se_bank = (*pos >> 24) & 0x3FF;
  2759. sh_bank = (*pos >> 34) & 0x3FF;
  2760. instance_bank = (*pos >> 44) & 0x3FF;
  2761. if (se_bank == 0x3FF)
  2762. se_bank = 0xFFFFFFFF;
  2763. if (sh_bank == 0x3FF)
  2764. sh_bank = 0xFFFFFFFF;
  2765. if (instance_bank == 0x3FF)
  2766. instance_bank = 0xFFFFFFFF;
  2767. use_bank = 1;
  2768. } else {
  2769. use_bank = 0;
  2770. }
  2771. *pos &= (1UL << 22) - 1;
  2772. if (use_bank) {
  2773. if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
  2774. (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
  2775. return -EINVAL;
  2776. mutex_lock(&adev->grbm_idx_mutex);
  2777. amdgpu_gfx_select_se_sh(adev, se_bank,
  2778. sh_bank, instance_bank);
  2779. }
  2780. if (pm_pg_lock)
  2781. mutex_lock(&adev->pm.mutex);
  2782. while (size) {
  2783. uint32_t value;
  2784. if (*pos > adev->rmmio_size)
  2785. return result;
  2786. r = get_user(value, (uint32_t *)buf);
  2787. if (r)
  2788. return r;
  2789. WREG32(*pos >> 2, value);
  2790. result += 4;
  2791. buf += 4;
  2792. *pos += 4;
  2793. size -= 4;
  2794. }
  2795. if (use_bank) {
  2796. amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  2797. mutex_unlock(&adev->grbm_idx_mutex);
  2798. }
  2799. if (pm_pg_lock)
  2800. mutex_unlock(&adev->pm.mutex);
  2801. return result;
  2802. }
  2803. static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
  2804. size_t size, loff_t *pos)
  2805. {
  2806. struct amdgpu_device *adev = file_inode(f)->i_private;
  2807. ssize_t result = 0;
  2808. int r;
  2809. if (size & 0x3 || *pos & 0x3)
  2810. return -EINVAL;
  2811. while (size) {
  2812. uint32_t value;
  2813. value = RREG32_PCIE(*pos >> 2);
  2814. r = put_user(value, (uint32_t *)buf);
  2815. if (r)
  2816. return r;
  2817. result += 4;
  2818. buf += 4;
  2819. *pos += 4;
  2820. size -= 4;
  2821. }
  2822. return result;
  2823. }
  2824. static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
  2825. size_t size, loff_t *pos)
  2826. {
  2827. struct amdgpu_device *adev = file_inode(f)->i_private;
  2828. ssize_t result = 0;
  2829. int r;
  2830. if (size & 0x3 || *pos & 0x3)
  2831. return -EINVAL;
  2832. while (size) {
  2833. uint32_t value;
  2834. r = get_user(value, (uint32_t *)buf);
  2835. if (r)
  2836. return r;
  2837. WREG32_PCIE(*pos >> 2, value);
  2838. result += 4;
  2839. buf += 4;
  2840. *pos += 4;
  2841. size -= 4;
  2842. }
  2843. return result;
  2844. }
  2845. static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
  2846. size_t size, loff_t *pos)
  2847. {
  2848. struct amdgpu_device *adev = file_inode(f)->i_private;
  2849. ssize_t result = 0;
  2850. int r;
  2851. if (size & 0x3 || *pos & 0x3)
  2852. return -EINVAL;
  2853. while (size) {
  2854. uint32_t value;
  2855. value = RREG32_DIDT(*pos >> 2);
  2856. r = put_user(value, (uint32_t *)buf);
  2857. if (r)
  2858. return r;
  2859. result += 4;
  2860. buf += 4;
  2861. *pos += 4;
  2862. size -= 4;
  2863. }
  2864. return result;
  2865. }
  2866. static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
  2867. size_t size, loff_t *pos)
  2868. {
  2869. struct amdgpu_device *adev = file_inode(f)->i_private;
  2870. ssize_t result = 0;
  2871. int r;
  2872. if (size & 0x3 || *pos & 0x3)
  2873. return -EINVAL;
  2874. while (size) {
  2875. uint32_t value;
  2876. r = get_user(value, (uint32_t *)buf);
  2877. if (r)
  2878. return r;
  2879. WREG32_DIDT(*pos >> 2, value);
  2880. result += 4;
  2881. buf += 4;
  2882. *pos += 4;
  2883. size -= 4;
  2884. }
  2885. return result;
  2886. }
  2887. static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
  2888. size_t size, loff_t *pos)
  2889. {
  2890. struct amdgpu_device *adev = file_inode(f)->i_private;
  2891. ssize_t result = 0;
  2892. int r;
  2893. if (size & 0x3 || *pos & 0x3)
  2894. return -EINVAL;
  2895. while (size) {
  2896. uint32_t value;
  2897. value = RREG32_SMC(*pos);
  2898. r = put_user(value, (uint32_t *)buf);
  2899. if (r)
  2900. return r;
  2901. result += 4;
  2902. buf += 4;
  2903. *pos += 4;
  2904. size -= 4;
  2905. }
  2906. return result;
  2907. }
  2908. static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
  2909. size_t size, loff_t *pos)
  2910. {
  2911. struct amdgpu_device *adev = file_inode(f)->i_private;
  2912. ssize_t result = 0;
  2913. int r;
  2914. if (size & 0x3 || *pos & 0x3)
  2915. return -EINVAL;
  2916. while (size) {
  2917. uint32_t value;
  2918. r = get_user(value, (uint32_t *)buf);
  2919. if (r)
  2920. return r;
  2921. WREG32_SMC(*pos, value);
  2922. result += 4;
  2923. buf += 4;
  2924. *pos += 4;
  2925. size -= 4;
  2926. }
  2927. return result;
  2928. }
  2929. static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
  2930. size_t size, loff_t *pos)
  2931. {
  2932. struct amdgpu_device *adev = file_inode(f)->i_private;
  2933. ssize_t result = 0;
  2934. int r;
  2935. uint32_t *config, no_regs = 0;
  2936. if (size & 0x3 || *pos & 0x3)
  2937. return -EINVAL;
  2938. config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
  2939. if (!config)
  2940. return -ENOMEM;
  2941. /* version, increment each time something is added */
  2942. config[no_regs++] = 3;
  2943. config[no_regs++] = adev->gfx.config.max_shader_engines;
  2944. config[no_regs++] = adev->gfx.config.max_tile_pipes;
  2945. config[no_regs++] = adev->gfx.config.max_cu_per_sh;
  2946. config[no_regs++] = adev->gfx.config.max_sh_per_se;
  2947. config[no_regs++] = adev->gfx.config.max_backends_per_se;
  2948. config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
  2949. config[no_regs++] = adev->gfx.config.max_gprs;
  2950. config[no_regs++] = adev->gfx.config.max_gs_threads;
  2951. config[no_regs++] = adev->gfx.config.max_hw_contexts;
  2952. config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
  2953. config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
  2954. config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
  2955. config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
  2956. config[no_regs++] = adev->gfx.config.num_tile_pipes;
  2957. config[no_regs++] = adev->gfx.config.backend_enable_mask;
  2958. config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
  2959. config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
  2960. config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
  2961. config[no_regs++] = adev->gfx.config.num_gpus;
  2962. config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
  2963. config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
  2964. config[no_regs++] = adev->gfx.config.gb_addr_config;
  2965. config[no_regs++] = adev->gfx.config.num_rbs;
  2966. /* rev==1 */
  2967. config[no_regs++] = adev->rev_id;
  2968. config[no_regs++] = adev->pg_flags;
  2969. config[no_regs++] = adev->cg_flags;
  2970. /* rev==2 */
  2971. config[no_regs++] = adev->family;
  2972. config[no_regs++] = adev->external_rev_id;
  2973. /* rev==3 */
  2974. config[no_regs++] = adev->pdev->device;
  2975. config[no_regs++] = adev->pdev->revision;
  2976. config[no_regs++] = adev->pdev->subsystem_device;
  2977. config[no_regs++] = adev->pdev->subsystem_vendor;
  2978. while (size && (*pos < no_regs * 4)) {
  2979. uint32_t value;
  2980. value = config[*pos >> 2];
  2981. r = put_user(value, (uint32_t *)buf);
  2982. if (r) {
  2983. kfree(config);
  2984. return r;
  2985. }
  2986. result += 4;
  2987. buf += 4;
  2988. *pos += 4;
  2989. size -= 4;
  2990. }
  2991. kfree(config);
  2992. return result;
  2993. }
  2994. static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
  2995. size_t size, loff_t *pos)
  2996. {
  2997. struct amdgpu_device *adev = file_inode(f)->i_private;
  2998. int idx, x, outsize, r, valuesize;
  2999. uint32_t values[16];
  3000. if (size & 3 || *pos & 0x3)
  3001. return -EINVAL;
  3002. if (amdgpu_dpm == 0)
  3003. return -EINVAL;
  3004. /* convert offset to sensor number */
  3005. idx = *pos >> 2;
  3006. valuesize = sizeof(values);
  3007. if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
  3008. r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
  3009. else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
  3010. r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
  3011. &valuesize);
  3012. else
  3013. return -EINVAL;
  3014. if (size > valuesize)
  3015. return -EINVAL;
  3016. outsize = 0;
  3017. x = 0;
  3018. if (!r) {
  3019. while (size) {
  3020. r = put_user(values[x++], (int32_t *)buf);
  3021. buf += 4;
  3022. size -= 4;
  3023. outsize += 4;
  3024. }
  3025. }
  3026. return !r ? outsize : r;
  3027. }
  3028. static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
  3029. size_t size, loff_t *pos)
  3030. {
  3031. struct amdgpu_device *adev = f->f_inode->i_private;
  3032. int r, x;
  3033. ssize_t result=0;
  3034. uint32_t offset, se, sh, cu, wave, simd, data[32];
  3035. if (size & 3 || *pos & 3)
  3036. return -EINVAL;
  3037. /* decode offset */
  3038. offset = (*pos & 0x7F);
  3039. se = ((*pos >> 7) & 0xFF);
  3040. sh = ((*pos >> 15) & 0xFF);
  3041. cu = ((*pos >> 23) & 0xFF);
  3042. wave = ((*pos >> 31) & 0xFF);
  3043. simd = ((*pos >> 37) & 0xFF);
  3044. /* switch to the specific se/sh/cu */
  3045. mutex_lock(&adev->grbm_idx_mutex);
  3046. amdgpu_gfx_select_se_sh(adev, se, sh, cu);
  3047. x = 0;
  3048. if (adev->gfx.funcs->read_wave_data)
  3049. adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
  3050. amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
  3051. mutex_unlock(&adev->grbm_idx_mutex);
  3052. if (!x)
  3053. return -EINVAL;
  3054. while (size && (offset < x * 4)) {
  3055. uint32_t value;
  3056. value = data[offset >> 2];
  3057. r = put_user(value, (uint32_t *)buf);
  3058. if (r)
  3059. return r;
  3060. result += 4;
  3061. buf += 4;
  3062. offset += 4;
  3063. size -= 4;
  3064. }
  3065. return result;
  3066. }
  3067. static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
  3068. size_t size, loff_t *pos)
  3069. {
  3070. struct amdgpu_device *adev = f->f_inode->i_private;
  3071. int r;
  3072. ssize_t result = 0;
  3073. uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
  3074. if (size & 3 || *pos & 3)
  3075. return -EINVAL;
  3076. /* decode offset */
  3077. offset = (*pos & 0xFFF); /* in dwords */
  3078. se = ((*pos >> 12) & 0xFF);
  3079. sh = ((*pos >> 20) & 0xFF);
  3080. cu = ((*pos >> 28) & 0xFF);
  3081. wave = ((*pos >> 36) & 0xFF);
  3082. simd = ((*pos >> 44) & 0xFF);
  3083. thread = ((*pos >> 52) & 0xFF);
  3084. bank = ((*pos >> 60) & 1);
  3085. data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
  3086. if (!data)
  3087. return -ENOMEM;
  3088. /* switch to the specific se/sh/cu */
  3089. mutex_lock(&adev->grbm_idx_mutex);
  3090. amdgpu_gfx_select_se_sh(adev, se, sh, cu);
  3091. if (bank == 0) {
  3092. if (adev->gfx.funcs->read_wave_vgprs)
  3093. adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
  3094. } else {
  3095. if (adev->gfx.funcs->read_wave_sgprs)
  3096. adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
  3097. }
  3098. amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
  3099. mutex_unlock(&adev->grbm_idx_mutex);
  3100. while (size) {
  3101. uint32_t value;
  3102. value = data[offset++];
  3103. r = put_user(value, (uint32_t *)buf);
  3104. if (r) {
  3105. result = r;
  3106. goto err;
  3107. }
  3108. result += 4;
  3109. buf += 4;
  3110. size -= 4;
  3111. }
  3112. err:
  3113. kfree(data);
  3114. return result;
  3115. }
  3116. static const struct file_operations amdgpu_debugfs_regs_fops = {
  3117. .owner = THIS_MODULE,
  3118. .read = amdgpu_debugfs_regs_read,
  3119. .write = amdgpu_debugfs_regs_write,
  3120. .llseek = default_llseek
  3121. };
  3122. static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
  3123. .owner = THIS_MODULE,
  3124. .read = amdgpu_debugfs_regs_didt_read,
  3125. .write = amdgpu_debugfs_regs_didt_write,
  3126. .llseek = default_llseek
  3127. };
  3128. static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
  3129. .owner = THIS_MODULE,
  3130. .read = amdgpu_debugfs_regs_pcie_read,
  3131. .write = amdgpu_debugfs_regs_pcie_write,
  3132. .llseek = default_llseek
  3133. };
  3134. static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
  3135. .owner = THIS_MODULE,
  3136. .read = amdgpu_debugfs_regs_smc_read,
  3137. .write = amdgpu_debugfs_regs_smc_write,
  3138. .llseek = default_llseek
  3139. };
  3140. static const struct file_operations amdgpu_debugfs_gca_config_fops = {
  3141. .owner = THIS_MODULE,
  3142. .read = amdgpu_debugfs_gca_config_read,
  3143. .llseek = default_llseek
  3144. };
  3145. static const struct file_operations amdgpu_debugfs_sensors_fops = {
  3146. .owner = THIS_MODULE,
  3147. .read = amdgpu_debugfs_sensor_read,
  3148. .llseek = default_llseek
  3149. };
  3150. static const struct file_operations amdgpu_debugfs_wave_fops = {
  3151. .owner = THIS_MODULE,
  3152. .read = amdgpu_debugfs_wave_read,
  3153. .llseek = default_llseek
  3154. };
  3155. static const struct file_operations amdgpu_debugfs_gpr_fops = {
  3156. .owner = THIS_MODULE,
  3157. .read = amdgpu_debugfs_gpr_read,
  3158. .llseek = default_llseek
  3159. };
  3160. static const struct file_operations *debugfs_regs[] = {
  3161. &amdgpu_debugfs_regs_fops,
  3162. &amdgpu_debugfs_regs_didt_fops,
  3163. &amdgpu_debugfs_regs_pcie_fops,
  3164. &amdgpu_debugfs_regs_smc_fops,
  3165. &amdgpu_debugfs_gca_config_fops,
  3166. &amdgpu_debugfs_sensors_fops,
  3167. &amdgpu_debugfs_wave_fops,
  3168. &amdgpu_debugfs_gpr_fops,
  3169. };
  3170. static const char *debugfs_regs_names[] = {
  3171. "amdgpu_regs",
  3172. "amdgpu_regs_didt",
  3173. "amdgpu_regs_pcie",
  3174. "amdgpu_regs_smc",
  3175. "amdgpu_gca_config",
  3176. "amdgpu_sensors",
  3177. "amdgpu_wave",
  3178. "amdgpu_gpr",
  3179. };
  3180. static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
  3181. {
  3182. struct drm_minor *minor = adev->ddev->primary;
  3183. struct dentry *ent, *root = minor->debugfs_root;
  3184. unsigned i, j;
  3185. for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
  3186. ent = debugfs_create_file(debugfs_regs_names[i],
  3187. S_IFREG | S_IRUGO, root,
  3188. adev, debugfs_regs[i]);
  3189. if (IS_ERR(ent)) {
  3190. for (j = 0; j < i; j++) {
  3191. debugfs_remove(adev->debugfs_regs[i]);
  3192. adev->debugfs_regs[i] = NULL;
  3193. }
  3194. return PTR_ERR(ent);
  3195. }
  3196. if (!i)
  3197. i_size_write(ent->d_inode, adev->rmmio_size);
  3198. adev->debugfs_regs[i] = ent;
  3199. }
  3200. return 0;
  3201. }
  3202. static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
  3203. {
  3204. unsigned i;
  3205. for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
  3206. if (adev->debugfs_regs[i]) {
  3207. debugfs_remove(adev->debugfs_regs[i]);
  3208. adev->debugfs_regs[i] = NULL;
  3209. }
  3210. }
  3211. }
  3212. static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
  3213. {
  3214. struct drm_info_node *node = (struct drm_info_node *) m->private;
  3215. struct drm_device *dev = node->minor->dev;
  3216. struct amdgpu_device *adev = dev->dev_private;
  3217. int r = 0, i;
  3218. /* hold on the scheduler */
  3219. for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
  3220. struct amdgpu_ring *ring = adev->rings[i];
  3221. if (!ring || !ring->sched.thread)
  3222. continue;
  3223. kthread_park(ring->sched.thread);
  3224. }
  3225. seq_printf(m, "run ib test:\n");
  3226. r = amdgpu_ib_ring_tests(adev);
  3227. if (r)
  3228. seq_printf(m, "ib ring tests failed (%d).\n", r);
  3229. else
  3230. seq_printf(m, "ib ring tests passed.\n");
  3231. /* go on the scheduler */
  3232. for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
  3233. struct amdgpu_ring *ring = adev->rings[i];
  3234. if (!ring || !ring->sched.thread)
  3235. continue;
  3236. kthread_unpark(ring->sched.thread);
  3237. }
  3238. return 0;
  3239. }
  3240. static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
  3241. {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
  3242. };
  3243. static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
  3244. {
  3245. return amdgpu_debugfs_add_files(adev,
  3246. amdgpu_debugfs_test_ib_ring_list, 1);
  3247. }
  3248. int amdgpu_debugfs_init(struct drm_minor *minor)
  3249. {
  3250. return 0;
  3251. }
  3252. #else
  3253. static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
  3254. {
  3255. return 0;
  3256. }
  3257. static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
  3258. {
  3259. return 0;
  3260. }
  3261. static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
  3262. #endif