stm32-hash.c 37 KB

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  1. /*
  2. * This file is part of STM32 Crypto driver for Linux.
  3. *
  4. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  5. * Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics.
  6. *
  7. * License terms: GPL V2.0.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published by
  11. * the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  16. * details.
  17. *
  18. * You should have received a copy of the GNU General Public License along with
  19. * this program. If not, see <http://www.gnu.org/licenses/>.
  20. *
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/crypto.h>
  24. #include <linux/delay.h>
  25. #include <linux/dmaengine.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/iopoll.h>
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/of_device.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/reset.h>
  34. #include <crypto/engine.h>
  35. #include <crypto/hash.h>
  36. #include <crypto/md5.h>
  37. #include <crypto/scatterwalk.h>
  38. #include <crypto/sha.h>
  39. #include <crypto/internal/hash.h>
  40. #define HASH_CR 0x00
  41. #define HASH_DIN 0x04
  42. #define HASH_STR 0x08
  43. #define HASH_IMR 0x20
  44. #define HASH_SR 0x24
  45. #define HASH_CSR(x) (0x0F8 + ((x) * 0x04))
  46. #define HASH_HREG(x) (0x310 + ((x) * 0x04))
  47. #define HASH_HWCFGR 0x3F0
  48. #define HASH_VER 0x3F4
  49. #define HASH_ID 0x3F8
  50. /* Control Register */
  51. #define HASH_CR_INIT BIT(2)
  52. #define HASH_CR_DMAE BIT(3)
  53. #define HASH_CR_DATATYPE_POS 4
  54. #define HASH_CR_MODE BIT(6)
  55. #define HASH_CR_MDMAT BIT(13)
  56. #define HASH_CR_DMAA BIT(14)
  57. #define HASH_CR_LKEY BIT(16)
  58. #define HASH_CR_ALGO_SHA1 0x0
  59. #define HASH_CR_ALGO_MD5 0x80
  60. #define HASH_CR_ALGO_SHA224 0x40000
  61. #define HASH_CR_ALGO_SHA256 0x40080
  62. /* Interrupt */
  63. #define HASH_DINIE BIT(0)
  64. #define HASH_DCIE BIT(1)
  65. /* Interrupt Mask */
  66. #define HASH_MASK_CALC_COMPLETION BIT(0)
  67. #define HASH_MASK_DATA_INPUT BIT(1)
  68. /* Context swap register */
  69. #define HASH_CSR_REGISTER_NUMBER 53
  70. /* Status Flags */
  71. #define HASH_SR_DATA_INPUT_READY BIT(0)
  72. #define HASH_SR_OUTPUT_READY BIT(1)
  73. #define HASH_SR_DMA_ACTIVE BIT(2)
  74. #define HASH_SR_BUSY BIT(3)
  75. /* STR Register */
  76. #define HASH_STR_NBLW_MASK GENMASK(4, 0)
  77. #define HASH_STR_DCAL BIT(8)
  78. #define HASH_FLAGS_INIT BIT(0)
  79. #define HASH_FLAGS_OUTPUT_READY BIT(1)
  80. #define HASH_FLAGS_CPU BIT(2)
  81. #define HASH_FLAGS_DMA_READY BIT(3)
  82. #define HASH_FLAGS_DMA_ACTIVE BIT(4)
  83. #define HASH_FLAGS_HMAC_INIT BIT(5)
  84. #define HASH_FLAGS_HMAC_FINAL BIT(6)
  85. #define HASH_FLAGS_HMAC_KEY BIT(7)
  86. #define HASH_FLAGS_FINAL BIT(15)
  87. #define HASH_FLAGS_FINUP BIT(16)
  88. #define HASH_FLAGS_ALGO_MASK GENMASK(21, 18)
  89. #define HASH_FLAGS_MD5 BIT(18)
  90. #define HASH_FLAGS_SHA1 BIT(19)
  91. #define HASH_FLAGS_SHA224 BIT(20)
  92. #define HASH_FLAGS_SHA256 BIT(21)
  93. #define HASH_FLAGS_ERRORS BIT(22)
  94. #define HASH_FLAGS_HMAC BIT(23)
  95. #define HASH_OP_UPDATE 1
  96. #define HASH_OP_FINAL 2
  97. enum stm32_hash_data_format {
  98. HASH_DATA_32_BITS = 0x0,
  99. HASH_DATA_16_BITS = 0x1,
  100. HASH_DATA_8_BITS = 0x2,
  101. HASH_DATA_1_BIT = 0x3
  102. };
  103. #define HASH_BUFLEN 256
  104. #define HASH_LONG_KEY 64
  105. #define HASH_MAX_KEY_SIZE (SHA256_BLOCK_SIZE * 8)
  106. #define HASH_QUEUE_LENGTH 16
  107. #define HASH_DMA_THRESHOLD 50
  108. struct stm32_hash_ctx {
  109. struct stm32_hash_dev *hdev;
  110. unsigned long flags;
  111. u8 key[HASH_MAX_KEY_SIZE];
  112. int keylen;
  113. };
  114. struct stm32_hash_request_ctx {
  115. struct stm32_hash_dev *hdev;
  116. unsigned long flags;
  117. unsigned long op;
  118. u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
  119. size_t digcnt;
  120. size_t bufcnt;
  121. size_t buflen;
  122. /* DMA */
  123. struct scatterlist *sg;
  124. unsigned int offset;
  125. unsigned int total;
  126. struct scatterlist sg_key;
  127. dma_addr_t dma_addr;
  128. size_t dma_ct;
  129. int nents;
  130. u8 data_type;
  131. u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32));
  132. /* Export Context */
  133. u32 *hw_context;
  134. };
  135. struct stm32_hash_algs_info {
  136. struct ahash_alg *algs_list;
  137. size_t size;
  138. };
  139. struct stm32_hash_pdata {
  140. struct stm32_hash_algs_info *algs_info;
  141. size_t algs_info_size;
  142. };
  143. struct stm32_hash_dev {
  144. struct list_head list;
  145. struct device *dev;
  146. struct clk *clk;
  147. struct reset_control *rst;
  148. void __iomem *io_base;
  149. phys_addr_t phys_base;
  150. u32 dma_mode;
  151. u32 dma_maxburst;
  152. spinlock_t lock; /* lock to protect queue */
  153. struct ahash_request *req;
  154. struct crypto_engine *engine;
  155. int err;
  156. unsigned long flags;
  157. struct dma_chan *dma_lch;
  158. struct completion dma_completion;
  159. const struct stm32_hash_pdata *pdata;
  160. };
  161. struct stm32_hash_drv {
  162. struct list_head dev_list;
  163. spinlock_t lock; /* List protection access */
  164. };
  165. static struct stm32_hash_drv stm32_hash = {
  166. .dev_list = LIST_HEAD_INIT(stm32_hash.dev_list),
  167. .lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock),
  168. };
  169. static void stm32_hash_dma_callback(void *param);
  170. static inline u32 stm32_hash_read(struct stm32_hash_dev *hdev, u32 offset)
  171. {
  172. return readl_relaxed(hdev->io_base + offset);
  173. }
  174. static inline void stm32_hash_write(struct stm32_hash_dev *hdev,
  175. u32 offset, u32 value)
  176. {
  177. writel_relaxed(value, hdev->io_base + offset);
  178. }
  179. static inline int stm32_hash_wait_busy(struct stm32_hash_dev *hdev)
  180. {
  181. u32 status;
  182. return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
  183. !(status & HASH_SR_BUSY), 10, 10000);
  184. }
  185. static void stm32_hash_set_nblw(struct stm32_hash_dev *hdev, int length)
  186. {
  187. u32 reg;
  188. reg = stm32_hash_read(hdev, HASH_STR);
  189. reg &= ~(HASH_STR_NBLW_MASK);
  190. reg |= (8U * ((length) % 4U));
  191. stm32_hash_write(hdev, HASH_STR, reg);
  192. }
  193. static int stm32_hash_write_key(struct stm32_hash_dev *hdev)
  194. {
  195. struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
  196. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
  197. u32 reg;
  198. int keylen = ctx->keylen;
  199. void *key = ctx->key;
  200. if (keylen) {
  201. stm32_hash_set_nblw(hdev, keylen);
  202. while (keylen > 0) {
  203. stm32_hash_write(hdev, HASH_DIN, *(u32 *)key);
  204. keylen -= 4;
  205. key += 4;
  206. }
  207. reg = stm32_hash_read(hdev, HASH_STR);
  208. reg |= HASH_STR_DCAL;
  209. stm32_hash_write(hdev, HASH_STR, reg);
  210. return -EINPROGRESS;
  211. }
  212. return 0;
  213. }
  214. static void stm32_hash_write_ctrl(struct stm32_hash_dev *hdev)
  215. {
  216. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
  217. struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
  218. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
  219. u32 reg = HASH_CR_INIT;
  220. if (!(hdev->flags & HASH_FLAGS_INIT)) {
  221. switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
  222. case HASH_FLAGS_MD5:
  223. reg |= HASH_CR_ALGO_MD5;
  224. break;
  225. case HASH_FLAGS_SHA1:
  226. reg |= HASH_CR_ALGO_SHA1;
  227. break;
  228. case HASH_FLAGS_SHA224:
  229. reg |= HASH_CR_ALGO_SHA224;
  230. break;
  231. case HASH_FLAGS_SHA256:
  232. reg |= HASH_CR_ALGO_SHA256;
  233. break;
  234. default:
  235. reg |= HASH_CR_ALGO_MD5;
  236. }
  237. reg |= (rctx->data_type << HASH_CR_DATATYPE_POS);
  238. if (rctx->flags & HASH_FLAGS_HMAC) {
  239. hdev->flags |= HASH_FLAGS_HMAC;
  240. reg |= HASH_CR_MODE;
  241. if (ctx->keylen > HASH_LONG_KEY)
  242. reg |= HASH_CR_LKEY;
  243. }
  244. stm32_hash_write(hdev, HASH_IMR, HASH_DCIE);
  245. stm32_hash_write(hdev, HASH_CR, reg);
  246. hdev->flags |= HASH_FLAGS_INIT;
  247. dev_dbg(hdev->dev, "Write Control %x\n", reg);
  248. }
  249. }
  250. static void stm32_hash_append_sg(struct stm32_hash_request_ctx *rctx)
  251. {
  252. size_t count;
  253. while ((rctx->bufcnt < rctx->buflen) && rctx->total) {
  254. count = min(rctx->sg->length - rctx->offset, rctx->total);
  255. count = min(count, rctx->buflen - rctx->bufcnt);
  256. if (count <= 0) {
  257. if ((rctx->sg->length == 0) && !sg_is_last(rctx->sg)) {
  258. rctx->sg = sg_next(rctx->sg);
  259. continue;
  260. } else {
  261. break;
  262. }
  263. }
  264. scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, rctx->sg,
  265. rctx->offset, count, 0);
  266. rctx->bufcnt += count;
  267. rctx->offset += count;
  268. rctx->total -= count;
  269. if (rctx->offset == rctx->sg->length) {
  270. rctx->sg = sg_next(rctx->sg);
  271. if (rctx->sg)
  272. rctx->offset = 0;
  273. else
  274. rctx->total = 0;
  275. }
  276. }
  277. }
  278. static int stm32_hash_xmit_cpu(struct stm32_hash_dev *hdev,
  279. const u8 *buf, size_t length, int final)
  280. {
  281. unsigned int count, len32;
  282. const u32 *buffer = (const u32 *)buf;
  283. u32 reg;
  284. if (final)
  285. hdev->flags |= HASH_FLAGS_FINAL;
  286. len32 = DIV_ROUND_UP(length, sizeof(u32));
  287. dev_dbg(hdev->dev, "%s: length: %d, final: %x len32 %i\n",
  288. __func__, length, final, len32);
  289. hdev->flags |= HASH_FLAGS_CPU;
  290. stm32_hash_write_ctrl(hdev);
  291. if (stm32_hash_wait_busy(hdev))
  292. return -ETIMEDOUT;
  293. if ((hdev->flags & HASH_FLAGS_HMAC) &&
  294. (!(hdev->flags & HASH_FLAGS_HMAC_KEY))) {
  295. hdev->flags |= HASH_FLAGS_HMAC_KEY;
  296. stm32_hash_write_key(hdev);
  297. if (stm32_hash_wait_busy(hdev))
  298. return -ETIMEDOUT;
  299. }
  300. for (count = 0; count < len32; count++)
  301. stm32_hash_write(hdev, HASH_DIN, buffer[count]);
  302. if (final) {
  303. stm32_hash_set_nblw(hdev, length);
  304. reg = stm32_hash_read(hdev, HASH_STR);
  305. reg |= HASH_STR_DCAL;
  306. stm32_hash_write(hdev, HASH_STR, reg);
  307. if (hdev->flags & HASH_FLAGS_HMAC) {
  308. if (stm32_hash_wait_busy(hdev))
  309. return -ETIMEDOUT;
  310. stm32_hash_write_key(hdev);
  311. }
  312. return -EINPROGRESS;
  313. }
  314. return 0;
  315. }
  316. static int stm32_hash_update_cpu(struct stm32_hash_dev *hdev)
  317. {
  318. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
  319. int bufcnt, err = 0, final;
  320. dev_dbg(hdev->dev, "%s flags %lx\n", __func__, rctx->flags);
  321. final = (rctx->flags & HASH_FLAGS_FINUP);
  322. while ((rctx->total >= rctx->buflen) ||
  323. (rctx->bufcnt + rctx->total >= rctx->buflen)) {
  324. stm32_hash_append_sg(rctx);
  325. bufcnt = rctx->bufcnt;
  326. rctx->bufcnt = 0;
  327. err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 0);
  328. }
  329. stm32_hash_append_sg(rctx);
  330. if (final) {
  331. bufcnt = rctx->bufcnt;
  332. rctx->bufcnt = 0;
  333. err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt,
  334. (rctx->flags & HASH_FLAGS_FINUP));
  335. }
  336. return err;
  337. }
  338. static int stm32_hash_xmit_dma(struct stm32_hash_dev *hdev,
  339. struct scatterlist *sg, int length, int mdma)
  340. {
  341. struct dma_async_tx_descriptor *in_desc;
  342. dma_cookie_t cookie;
  343. u32 reg;
  344. int err;
  345. in_desc = dmaengine_prep_slave_sg(hdev->dma_lch, sg, 1,
  346. DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT |
  347. DMA_CTRL_ACK);
  348. if (!in_desc) {
  349. dev_err(hdev->dev, "dmaengine_prep_slave error\n");
  350. return -ENOMEM;
  351. }
  352. reinit_completion(&hdev->dma_completion);
  353. in_desc->callback = stm32_hash_dma_callback;
  354. in_desc->callback_param = hdev;
  355. hdev->flags |= HASH_FLAGS_FINAL;
  356. hdev->flags |= HASH_FLAGS_DMA_ACTIVE;
  357. reg = stm32_hash_read(hdev, HASH_CR);
  358. if (mdma)
  359. reg |= HASH_CR_MDMAT;
  360. else
  361. reg &= ~HASH_CR_MDMAT;
  362. reg |= HASH_CR_DMAE;
  363. stm32_hash_write(hdev, HASH_CR, reg);
  364. stm32_hash_set_nblw(hdev, length);
  365. cookie = dmaengine_submit(in_desc);
  366. err = dma_submit_error(cookie);
  367. if (err)
  368. return -ENOMEM;
  369. dma_async_issue_pending(hdev->dma_lch);
  370. if (!wait_for_completion_interruptible_timeout(&hdev->dma_completion,
  371. msecs_to_jiffies(100)))
  372. err = -ETIMEDOUT;
  373. if (dma_async_is_tx_complete(hdev->dma_lch, cookie,
  374. NULL, NULL) != DMA_COMPLETE)
  375. err = -ETIMEDOUT;
  376. if (err) {
  377. dev_err(hdev->dev, "DMA Error %i\n", err);
  378. dmaengine_terminate_all(hdev->dma_lch);
  379. return err;
  380. }
  381. return -EINPROGRESS;
  382. }
  383. static void stm32_hash_dma_callback(void *param)
  384. {
  385. struct stm32_hash_dev *hdev = param;
  386. complete(&hdev->dma_completion);
  387. hdev->flags |= HASH_FLAGS_DMA_READY;
  388. }
  389. static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev)
  390. {
  391. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
  392. struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
  393. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
  394. int err;
  395. if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) {
  396. err = stm32_hash_write_key(hdev);
  397. if (stm32_hash_wait_busy(hdev))
  398. return -ETIMEDOUT;
  399. } else {
  400. if (!(hdev->flags & HASH_FLAGS_HMAC_KEY))
  401. sg_init_one(&rctx->sg_key, ctx->key,
  402. ALIGN(ctx->keylen, sizeof(u32)));
  403. rctx->dma_ct = dma_map_sg(hdev->dev, &rctx->sg_key, 1,
  404. DMA_TO_DEVICE);
  405. if (rctx->dma_ct == 0) {
  406. dev_err(hdev->dev, "dma_map_sg error\n");
  407. return -ENOMEM;
  408. }
  409. err = stm32_hash_xmit_dma(hdev, &rctx->sg_key, ctx->keylen, 0);
  410. dma_unmap_sg(hdev->dev, &rctx->sg_key, 1, DMA_TO_DEVICE);
  411. }
  412. return err;
  413. }
  414. static int stm32_hash_dma_init(struct stm32_hash_dev *hdev)
  415. {
  416. struct dma_slave_config dma_conf;
  417. int err;
  418. memset(&dma_conf, 0, sizeof(dma_conf));
  419. dma_conf.direction = DMA_MEM_TO_DEV;
  420. dma_conf.dst_addr = hdev->phys_base + HASH_DIN;
  421. dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  422. dma_conf.src_maxburst = hdev->dma_maxburst;
  423. dma_conf.dst_maxburst = hdev->dma_maxburst;
  424. dma_conf.device_fc = false;
  425. hdev->dma_lch = dma_request_slave_channel(hdev->dev, "in");
  426. if (!hdev->dma_lch) {
  427. dev_err(hdev->dev, "Couldn't acquire a slave DMA channel.\n");
  428. return -EBUSY;
  429. }
  430. err = dmaengine_slave_config(hdev->dma_lch, &dma_conf);
  431. if (err) {
  432. dma_release_channel(hdev->dma_lch);
  433. hdev->dma_lch = NULL;
  434. dev_err(hdev->dev, "Couldn't configure DMA slave.\n");
  435. return err;
  436. }
  437. init_completion(&hdev->dma_completion);
  438. return 0;
  439. }
  440. static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
  441. {
  442. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
  443. struct scatterlist sg[1], *tsg;
  444. int err = 0, len = 0, reg, ncp = 0;
  445. unsigned int i;
  446. u32 *buffer = (void *)rctx->buffer;
  447. rctx->sg = hdev->req->src;
  448. rctx->total = hdev->req->nbytes;
  449. rctx->nents = sg_nents(rctx->sg);
  450. if (rctx->nents < 0)
  451. return -EINVAL;
  452. stm32_hash_write_ctrl(hdev);
  453. if (hdev->flags & HASH_FLAGS_HMAC) {
  454. err = stm32_hash_hmac_dma_send(hdev);
  455. if (err != -EINPROGRESS)
  456. return err;
  457. }
  458. for_each_sg(rctx->sg, tsg, rctx->nents, i) {
  459. len = sg->length;
  460. sg[0] = *tsg;
  461. if (sg_is_last(sg)) {
  462. if (hdev->dma_mode == 1) {
  463. len = (ALIGN(sg->length, 16) - 16);
  464. ncp = sg_pcopy_to_buffer(
  465. rctx->sg, rctx->nents,
  466. rctx->buffer, sg->length - len,
  467. rctx->total - sg->length + len);
  468. sg->length = len;
  469. } else {
  470. if (!(IS_ALIGNED(sg->length, sizeof(u32)))) {
  471. len = sg->length;
  472. sg->length = ALIGN(sg->length,
  473. sizeof(u32));
  474. }
  475. }
  476. }
  477. rctx->dma_ct = dma_map_sg(hdev->dev, sg, 1,
  478. DMA_TO_DEVICE);
  479. if (rctx->dma_ct == 0) {
  480. dev_err(hdev->dev, "dma_map_sg error\n");
  481. return -ENOMEM;
  482. }
  483. err = stm32_hash_xmit_dma(hdev, sg, len,
  484. !sg_is_last(sg));
  485. dma_unmap_sg(hdev->dev, sg, 1, DMA_TO_DEVICE);
  486. if (err == -ENOMEM)
  487. return err;
  488. }
  489. if (hdev->dma_mode == 1) {
  490. if (stm32_hash_wait_busy(hdev))
  491. return -ETIMEDOUT;
  492. reg = stm32_hash_read(hdev, HASH_CR);
  493. reg &= ~HASH_CR_DMAE;
  494. reg |= HASH_CR_DMAA;
  495. stm32_hash_write(hdev, HASH_CR, reg);
  496. if (ncp) {
  497. memset(buffer + ncp, 0,
  498. DIV_ROUND_UP(ncp, sizeof(u32)) - ncp);
  499. writesl(hdev->io_base + HASH_DIN, buffer,
  500. DIV_ROUND_UP(ncp, sizeof(u32)));
  501. }
  502. stm32_hash_set_nblw(hdev, DIV_ROUND_UP(ncp, sizeof(u32)));
  503. reg = stm32_hash_read(hdev, HASH_STR);
  504. reg |= HASH_STR_DCAL;
  505. stm32_hash_write(hdev, HASH_STR, reg);
  506. err = -EINPROGRESS;
  507. }
  508. if (hdev->flags & HASH_FLAGS_HMAC) {
  509. if (stm32_hash_wait_busy(hdev))
  510. return -ETIMEDOUT;
  511. err = stm32_hash_hmac_dma_send(hdev);
  512. }
  513. return err;
  514. }
  515. static struct stm32_hash_dev *stm32_hash_find_dev(struct stm32_hash_ctx *ctx)
  516. {
  517. struct stm32_hash_dev *hdev = NULL, *tmp;
  518. spin_lock_bh(&stm32_hash.lock);
  519. if (!ctx->hdev) {
  520. list_for_each_entry(tmp, &stm32_hash.dev_list, list) {
  521. hdev = tmp;
  522. break;
  523. }
  524. ctx->hdev = hdev;
  525. } else {
  526. hdev = ctx->hdev;
  527. }
  528. spin_unlock_bh(&stm32_hash.lock);
  529. return hdev;
  530. }
  531. static bool stm32_hash_dma_aligned_data(struct ahash_request *req)
  532. {
  533. struct scatterlist *sg;
  534. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
  535. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  536. int i;
  537. if (req->nbytes <= HASH_DMA_THRESHOLD)
  538. return false;
  539. if (sg_nents(req->src) > 1) {
  540. if (hdev->dma_mode == 1)
  541. return false;
  542. for_each_sg(req->src, sg, sg_nents(req->src), i) {
  543. if ((!IS_ALIGNED(sg->length, sizeof(u32))) &&
  544. (!sg_is_last(sg)))
  545. return false;
  546. }
  547. }
  548. if (req->src->offset % 4)
  549. return false;
  550. return true;
  551. }
  552. static int stm32_hash_init(struct ahash_request *req)
  553. {
  554. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  555. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
  556. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  557. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  558. rctx->hdev = hdev;
  559. rctx->flags = HASH_FLAGS_CPU;
  560. rctx->digcnt = crypto_ahash_digestsize(tfm);
  561. switch (rctx->digcnt) {
  562. case MD5_DIGEST_SIZE:
  563. rctx->flags |= HASH_FLAGS_MD5;
  564. break;
  565. case SHA1_DIGEST_SIZE:
  566. rctx->flags |= HASH_FLAGS_SHA1;
  567. break;
  568. case SHA224_DIGEST_SIZE:
  569. rctx->flags |= HASH_FLAGS_SHA224;
  570. break;
  571. case SHA256_DIGEST_SIZE:
  572. rctx->flags |= HASH_FLAGS_SHA256;
  573. break;
  574. default:
  575. return -EINVAL;
  576. }
  577. rctx->bufcnt = 0;
  578. rctx->buflen = HASH_BUFLEN;
  579. rctx->total = 0;
  580. rctx->offset = 0;
  581. rctx->data_type = HASH_DATA_8_BITS;
  582. memset(rctx->buffer, 0, HASH_BUFLEN);
  583. if (ctx->flags & HASH_FLAGS_HMAC)
  584. rctx->flags |= HASH_FLAGS_HMAC;
  585. dev_dbg(hdev->dev, "%s Flags %lx\n", __func__, rctx->flags);
  586. return 0;
  587. }
  588. static int stm32_hash_update_req(struct stm32_hash_dev *hdev)
  589. {
  590. return stm32_hash_update_cpu(hdev);
  591. }
  592. static int stm32_hash_final_req(struct stm32_hash_dev *hdev)
  593. {
  594. struct ahash_request *req = hdev->req;
  595. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  596. int err;
  597. if (!(rctx->flags & HASH_FLAGS_CPU))
  598. err = stm32_hash_dma_send(hdev);
  599. else
  600. err = stm32_hash_xmit_cpu(hdev, rctx->buffer, rctx->bufcnt, 1);
  601. rctx->bufcnt = 0;
  602. return err;
  603. }
  604. static void stm32_hash_copy_hash(struct ahash_request *req)
  605. {
  606. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  607. u32 *hash = (u32 *)rctx->digest;
  608. unsigned int i, hashsize;
  609. switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
  610. case HASH_FLAGS_MD5:
  611. hashsize = MD5_DIGEST_SIZE;
  612. break;
  613. case HASH_FLAGS_SHA1:
  614. hashsize = SHA1_DIGEST_SIZE;
  615. break;
  616. case HASH_FLAGS_SHA224:
  617. hashsize = SHA224_DIGEST_SIZE;
  618. break;
  619. case HASH_FLAGS_SHA256:
  620. hashsize = SHA256_DIGEST_SIZE;
  621. break;
  622. default:
  623. return;
  624. }
  625. for (i = 0; i < hashsize / sizeof(u32); i++)
  626. hash[i] = be32_to_cpu(stm32_hash_read(rctx->hdev,
  627. HASH_HREG(i)));
  628. }
  629. static int stm32_hash_finish(struct ahash_request *req)
  630. {
  631. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  632. if (!req->result)
  633. return -EINVAL;
  634. memcpy(req->result, rctx->digest, rctx->digcnt);
  635. return 0;
  636. }
  637. static void stm32_hash_finish_req(struct ahash_request *req, int err)
  638. {
  639. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  640. struct stm32_hash_dev *hdev = rctx->hdev;
  641. if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {
  642. stm32_hash_copy_hash(req);
  643. err = stm32_hash_finish(req);
  644. hdev->flags &= ~(HASH_FLAGS_FINAL | HASH_FLAGS_CPU |
  645. HASH_FLAGS_INIT | HASH_FLAGS_DMA_READY |
  646. HASH_FLAGS_OUTPUT_READY | HASH_FLAGS_HMAC |
  647. HASH_FLAGS_HMAC_INIT | HASH_FLAGS_HMAC_FINAL |
  648. HASH_FLAGS_HMAC_KEY);
  649. } else {
  650. rctx->flags |= HASH_FLAGS_ERRORS;
  651. }
  652. crypto_finalize_hash_request(hdev->engine, req, err);
  653. }
  654. static int stm32_hash_hw_init(struct stm32_hash_dev *hdev,
  655. struct stm32_hash_request_ctx *rctx)
  656. {
  657. if (!(HASH_FLAGS_INIT & hdev->flags)) {
  658. stm32_hash_write(hdev, HASH_CR, HASH_CR_INIT);
  659. stm32_hash_write(hdev, HASH_STR, 0);
  660. stm32_hash_write(hdev, HASH_DIN, 0);
  661. stm32_hash_write(hdev, HASH_IMR, 0);
  662. hdev->err = 0;
  663. }
  664. return 0;
  665. }
  666. static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
  667. struct ahash_request *req)
  668. {
  669. return crypto_transfer_hash_request_to_engine(hdev->engine, req);
  670. }
  671. static int stm32_hash_prepare_req(struct crypto_engine *engine,
  672. struct ahash_request *req)
  673. {
  674. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
  675. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  676. struct stm32_hash_request_ctx *rctx;
  677. if (!hdev)
  678. return -ENODEV;
  679. hdev->req = req;
  680. rctx = ahash_request_ctx(req);
  681. dev_dbg(hdev->dev, "processing new req, op: %lu, nbytes %d\n",
  682. rctx->op, req->nbytes);
  683. return stm32_hash_hw_init(hdev, rctx);
  684. }
  685. static int stm32_hash_one_request(struct crypto_engine *engine,
  686. struct ahash_request *req)
  687. {
  688. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
  689. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  690. struct stm32_hash_request_ctx *rctx;
  691. int err = 0;
  692. if (!hdev)
  693. return -ENODEV;
  694. hdev->req = req;
  695. rctx = ahash_request_ctx(req);
  696. if (rctx->op == HASH_OP_UPDATE)
  697. err = stm32_hash_update_req(hdev);
  698. else if (rctx->op == HASH_OP_FINAL)
  699. err = stm32_hash_final_req(hdev);
  700. if (err != -EINPROGRESS)
  701. /* done task will not finish it, so do it here */
  702. stm32_hash_finish_req(req, err);
  703. return 0;
  704. }
  705. static int stm32_hash_enqueue(struct ahash_request *req, unsigned int op)
  706. {
  707. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  708. struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
  709. struct stm32_hash_dev *hdev = ctx->hdev;
  710. rctx->op = op;
  711. return stm32_hash_handle_queue(hdev, req);
  712. }
  713. static int stm32_hash_update(struct ahash_request *req)
  714. {
  715. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  716. int ret;
  717. if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
  718. return 0;
  719. rctx->total = req->nbytes;
  720. rctx->sg = req->src;
  721. rctx->offset = 0;
  722. if ((rctx->bufcnt + rctx->total < rctx->buflen)) {
  723. stm32_hash_append_sg(rctx);
  724. return 0;
  725. }
  726. ret = stm32_hash_enqueue(req, HASH_OP_UPDATE);
  727. if (rctx->flags & HASH_FLAGS_FINUP)
  728. return ret;
  729. return 0;
  730. }
  731. static int stm32_hash_final(struct ahash_request *req)
  732. {
  733. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  734. rctx->flags |= HASH_FLAGS_FINUP;
  735. return stm32_hash_enqueue(req, HASH_OP_FINAL);
  736. }
  737. static int stm32_hash_finup(struct ahash_request *req)
  738. {
  739. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  740. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
  741. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  742. int err1, err2;
  743. rctx->flags |= HASH_FLAGS_FINUP;
  744. if (hdev->dma_lch && stm32_hash_dma_aligned_data(req))
  745. rctx->flags &= ~HASH_FLAGS_CPU;
  746. err1 = stm32_hash_update(req);
  747. if (err1 == -EINPROGRESS || err1 == -EBUSY)
  748. return err1;
  749. /*
  750. * final() has to be always called to cleanup resources
  751. * even if update() failed, except EINPROGRESS
  752. */
  753. err2 = stm32_hash_final(req);
  754. return err1 ?: err2;
  755. }
  756. static int stm32_hash_digest(struct ahash_request *req)
  757. {
  758. return stm32_hash_init(req) ?: stm32_hash_finup(req);
  759. }
  760. static int stm32_hash_export(struct ahash_request *req, void *out)
  761. {
  762. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  763. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
  764. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  765. u32 *preg;
  766. unsigned int i;
  767. while (!(stm32_hash_read(hdev, HASH_SR) & HASH_SR_DATA_INPUT_READY))
  768. cpu_relax();
  769. rctx->hw_context = kmalloc(sizeof(u32) * (3 + HASH_CSR_REGISTER_NUMBER),
  770. GFP_KERNEL);
  771. preg = rctx->hw_context;
  772. *preg++ = stm32_hash_read(hdev, HASH_IMR);
  773. *preg++ = stm32_hash_read(hdev, HASH_STR);
  774. *preg++ = stm32_hash_read(hdev, HASH_CR);
  775. for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
  776. *preg++ = stm32_hash_read(hdev, HASH_CSR(i));
  777. memcpy(out, rctx, sizeof(*rctx));
  778. return 0;
  779. }
  780. static int stm32_hash_import(struct ahash_request *req, const void *in)
  781. {
  782. struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
  783. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
  784. struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
  785. const u32 *preg = in;
  786. u32 reg;
  787. unsigned int i;
  788. memcpy(rctx, in, sizeof(*rctx));
  789. preg = rctx->hw_context;
  790. stm32_hash_write(hdev, HASH_IMR, *preg++);
  791. stm32_hash_write(hdev, HASH_STR, *preg++);
  792. stm32_hash_write(hdev, HASH_CR, *preg);
  793. reg = *preg++ | HASH_CR_INIT;
  794. stm32_hash_write(hdev, HASH_CR, reg);
  795. for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
  796. stm32_hash_write(hdev, HASH_CSR(i), *preg++);
  797. kfree(rctx->hw_context);
  798. return 0;
  799. }
  800. static int stm32_hash_setkey(struct crypto_ahash *tfm,
  801. const u8 *key, unsigned int keylen)
  802. {
  803. struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
  804. if (keylen <= HASH_MAX_KEY_SIZE) {
  805. memcpy(ctx->key, key, keylen);
  806. ctx->keylen = keylen;
  807. } else {
  808. return -ENOMEM;
  809. }
  810. return 0;
  811. }
  812. static int stm32_hash_cra_init_algs(struct crypto_tfm *tfm,
  813. const char *algs_hmac_name)
  814. {
  815. struct stm32_hash_ctx *ctx = crypto_tfm_ctx(tfm);
  816. crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
  817. sizeof(struct stm32_hash_request_ctx));
  818. ctx->keylen = 0;
  819. if (algs_hmac_name)
  820. ctx->flags |= HASH_FLAGS_HMAC;
  821. return 0;
  822. }
  823. static int stm32_hash_cra_init(struct crypto_tfm *tfm)
  824. {
  825. return stm32_hash_cra_init_algs(tfm, NULL);
  826. }
  827. static int stm32_hash_cra_md5_init(struct crypto_tfm *tfm)
  828. {
  829. return stm32_hash_cra_init_algs(tfm, "md5");
  830. }
  831. static int stm32_hash_cra_sha1_init(struct crypto_tfm *tfm)
  832. {
  833. return stm32_hash_cra_init_algs(tfm, "sha1");
  834. }
  835. static int stm32_hash_cra_sha224_init(struct crypto_tfm *tfm)
  836. {
  837. return stm32_hash_cra_init_algs(tfm, "sha224");
  838. }
  839. static int stm32_hash_cra_sha256_init(struct crypto_tfm *tfm)
  840. {
  841. return stm32_hash_cra_init_algs(tfm, "sha256");
  842. }
  843. static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
  844. {
  845. struct stm32_hash_dev *hdev = dev_id;
  846. int err;
  847. if (HASH_FLAGS_CPU & hdev->flags) {
  848. if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
  849. hdev->flags &= ~HASH_FLAGS_OUTPUT_READY;
  850. goto finish;
  851. }
  852. } else if (HASH_FLAGS_DMA_READY & hdev->flags) {
  853. if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) {
  854. hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE;
  855. goto finish;
  856. }
  857. }
  858. return IRQ_HANDLED;
  859. finish:
  860. /*Finish current request */
  861. stm32_hash_finish_req(hdev->req, err);
  862. return IRQ_HANDLED;
  863. }
  864. static irqreturn_t stm32_hash_irq_handler(int irq, void *dev_id)
  865. {
  866. struct stm32_hash_dev *hdev = dev_id;
  867. u32 reg;
  868. reg = stm32_hash_read(hdev, HASH_SR);
  869. if (reg & HASH_SR_OUTPUT_READY) {
  870. reg &= ~HASH_SR_OUTPUT_READY;
  871. stm32_hash_write(hdev, HASH_SR, reg);
  872. hdev->flags |= HASH_FLAGS_OUTPUT_READY;
  873. return IRQ_WAKE_THREAD;
  874. }
  875. return IRQ_NONE;
  876. }
  877. static struct ahash_alg algs_md5_sha1[] = {
  878. {
  879. .init = stm32_hash_init,
  880. .update = stm32_hash_update,
  881. .final = stm32_hash_final,
  882. .finup = stm32_hash_finup,
  883. .digest = stm32_hash_digest,
  884. .export = stm32_hash_export,
  885. .import = stm32_hash_import,
  886. .halg = {
  887. .digestsize = MD5_DIGEST_SIZE,
  888. .statesize = sizeof(struct stm32_hash_request_ctx),
  889. .base = {
  890. .cra_name = "md5",
  891. .cra_driver_name = "stm32-md5",
  892. .cra_priority = 200,
  893. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  894. CRYPTO_ALG_ASYNC |
  895. CRYPTO_ALG_KERN_DRIVER_ONLY,
  896. .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  897. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  898. .cra_alignmask = 3,
  899. .cra_init = stm32_hash_cra_init,
  900. .cra_module = THIS_MODULE,
  901. }
  902. }
  903. },
  904. {
  905. .init = stm32_hash_init,
  906. .update = stm32_hash_update,
  907. .final = stm32_hash_final,
  908. .finup = stm32_hash_finup,
  909. .digest = stm32_hash_digest,
  910. .export = stm32_hash_export,
  911. .import = stm32_hash_import,
  912. .setkey = stm32_hash_setkey,
  913. .halg = {
  914. .digestsize = MD5_DIGEST_SIZE,
  915. .statesize = sizeof(struct stm32_hash_request_ctx),
  916. .base = {
  917. .cra_name = "hmac(md5)",
  918. .cra_driver_name = "stm32-hmac-md5",
  919. .cra_priority = 200,
  920. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  921. CRYPTO_ALG_ASYNC |
  922. CRYPTO_ALG_KERN_DRIVER_ONLY,
  923. .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  924. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  925. .cra_alignmask = 3,
  926. .cra_init = stm32_hash_cra_md5_init,
  927. .cra_module = THIS_MODULE,
  928. }
  929. }
  930. },
  931. {
  932. .init = stm32_hash_init,
  933. .update = stm32_hash_update,
  934. .final = stm32_hash_final,
  935. .finup = stm32_hash_finup,
  936. .digest = stm32_hash_digest,
  937. .export = stm32_hash_export,
  938. .import = stm32_hash_import,
  939. .halg = {
  940. .digestsize = SHA1_DIGEST_SIZE,
  941. .statesize = sizeof(struct stm32_hash_request_ctx),
  942. .base = {
  943. .cra_name = "sha1",
  944. .cra_driver_name = "stm32-sha1",
  945. .cra_priority = 200,
  946. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  947. CRYPTO_ALG_ASYNC |
  948. CRYPTO_ALG_KERN_DRIVER_ONLY,
  949. .cra_blocksize = SHA1_BLOCK_SIZE,
  950. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  951. .cra_alignmask = 3,
  952. .cra_init = stm32_hash_cra_init,
  953. .cra_module = THIS_MODULE,
  954. }
  955. }
  956. },
  957. {
  958. .init = stm32_hash_init,
  959. .update = stm32_hash_update,
  960. .final = stm32_hash_final,
  961. .finup = stm32_hash_finup,
  962. .digest = stm32_hash_digest,
  963. .export = stm32_hash_export,
  964. .import = stm32_hash_import,
  965. .setkey = stm32_hash_setkey,
  966. .halg = {
  967. .digestsize = SHA1_DIGEST_SIZE,
  968. .statesize = sizeof(struct stm32_hash_request_ctx),
  969. .base = {
  970. .cra_name = "hmac(sha1)",
  971. .cra_driver_name = "stm32-hmac-sha1",
  972. .cra_priority = 200,
  973. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  974. CRYPTO_ALG_ASYNC |
  975. CRYPTO_ALG_KERN_DRIVER_ONLY,
  976. .cra_blocksize = SHA1_BLOCK_SIZE,
  977. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  978. .cra_alignmask = 3,
  979. .cra_init = stm32_hash_cra_sha1_init,
  980. .cra_module = THIS_MODULE,
  981. }
  982. }
  983. },
  984. };
  985. static struct ahash_alg algs_sha224_sha256[] = {
  986. {
  987. .init = stm32_hash_init,
  988. .update = stm32_hash_update,
  989. .final = stm32_hash_final,
  990. .finup = stm32_hash_finup,
  991. .digest = stm32_hash_digest,
  992. .export = stm32_hash_export,
  993. .import = stm32_hash_import,
  994. .halg = {
  995. .digestsize = SHA224_DIGEST_SIZE,
  996. .statesize = sizeof(struct stm32_hash_request_ctx),
  997. .base = {
  998. .cra_name = "sha224",
  999. .cra_driver_name = "stm32-sha224",
  1000. .cra_priority = 200,
  1001. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1002. CRYPTO_ALG_ASYNC |
  1003. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1004. .cra_blocksize = SHA224_BLOCK_SIZE,
  1005. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  1006. .cra_alignmask = 3,
  1007. .cra_init = stm32_hash_cra_init,
  1008. .cra_module = THIS_MODULE,
  1009. }
  1010. }
  1011. },
  1012. {
  1013. .init = stm32_hash_init,
  1014. .update = stm32_hash_update,
  1015. .final = stm32_hash_final,
  1016. .finup = stm32_hash_finup,
  1017. .digest = stm32_hash_digest,
  1018. .setkey = stm32_hash_setkey,
  1019. .export = stm32_hash_export,
  1020. .import = stm32_hash_import,
  1021. .halg = {
  1022. .digestsize = SHA224_DIGEST_SIZE,
  1023. .statesize = sizeof(struct stm32_hash_request_ctx),
  1024. .base = {
  1025. .cra_name = "hmac(sha224)",
  1026. .cra_driver_name = "stm32-hmac-sha224",
  1027. .cra_priority = 200,
  1028. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1029. CRYPTO_ALG_ASYNC |
  1030. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1031. .cra_blocksize = SHA224_BLOCK_SIZE,
  1032. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  1033. .cra_alignmask = 3,
  1034. .cra_init = stm32_hash_cra_sha224_init,
  1035. .cra_module = THIS_MODULE,
  1036. }
  1037. }
  1038. },
  1039. {
  1040. .init = stm32_hash_init,
  1041. .update = stm32_hash_update,
  1042. .final = stm32_hash_final,
  1043. .finup = stm32_hash_finup,
  1044. .digest = stm32_hash_digest,
  1045. .export = stm32_hash_export,
  1046. .import = stm32_hash_import,
  1047. .halg = {
  1048. .digestsize = SHA256_DIGEST_SIZE,
  1049. .statesize = sizeof(struct stm32_hash_request_ctx),
  1050. .base = {
  1051. .cra_name = "sha256",
  1052. .cra_driver_name = "stm32-sha256",
  1053. .cra_priority = 200,
  1054. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1055. CRYPTO_ALG_ASYNC |
  1056. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1057. .cra_blocksize = SHA256_BLOCK_SIZE,
  1058. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  1059. .cra_alignmask = 3,
  1060. .cra_init = stm32_hash_cra_init,
  1061. .cra_module = THIS_MODULE,
  1062. }
  1063. }
  1064. },
  1065. {
  1066. .init = stm32_hash_init,
  1067. .update = stm32_hash_update,
  1068. .final = stm32_hash_final,
  1069. .finup = stm32_hash_finup,
  1070. .digest = stm32_hash_digest,
  1071. .export = stm32_hash_export,
  1072. .import = stm32_hash_import,
  1073. .setkey = stm32_hash_setkey,
  1074. .halg = {
  1075. .digestsize = SHA256_DIGEST_SIZE,
  1076. .statesize = sizeof(struct stm32_hash_request_ctx),
  1077. .base = {
  1078. .cra_name = "hmac(sha256)",
  1079. .cra_driver_name = "stm32-hmac-sha256",
  1080. .cra_priority = 200,
  1081. .cra_flags = CRYPTO_ALG_TYPE_AHASH |
  1082. CRYPTO_ALG_ASYNC |
  1083. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1084. .cra_blocksize = SHA256_BLOCK_SIZE,
  1085. .cra_ctxsize = sizeof(struct stm32_hash_ctx),
  1086. .cra_alignmask = 3,
  1087. .cra_init = stm32_hash_cra_sha256_init,
  1088. .cra_module = THIS_MODULE,
  1089. }
  1090. }
  1091. },
  1092. };
  1093. static int stm32_hash_register_algs(struct stm32_hash_dev *hdev)
  1094. {
  1095. unsigned int i, j;
  1096. int err;
  1097. for (i = 0; i < hdev->pdata->algs_info_size; i++) {
  1098. for (j = 0; j < hdev->pdata->algs_info[i].size; j++) {
  1099. err = crypto_register_ahash(
  1100. &hdev->pdata->algs_info[i].algs_list[j]);
  1101. if (err)
  1102. goto err_algs;
  1103. }
  1104. }
  1105. return 0;
  1106. err_algs:
  1107. dev_err(hdev->dev, "Algo %d : %d failed\n", i, j);
  1108. for (; i--; ) {
  1109. for (; j--;)
  1110. crypto_unregister_ahash(
  1111. &hdev->pdata->algs_info[i].algs_list[j]);
  1112. }
  1113. return err;
  1114. }
  1115. static int stm32_hash_unregister_algs(struct stm32_hash_dev *hdev)
  1116. {
  1117. unsigned int i, j;
  1118. for (i = 0; i < hdev->pdata->algs_info_size; i++) {
  1119. for (j = 0; j < hdev->pdata->algs_info[i].size; j++)
  1120. crypto_unregister_ahash(
  1121. &hdev->pdata->algs_info[i].algs_list[j]);
  1122. }
  1123. return 0;
  1124. }
  1125. static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f4[] = {
  1126. {
  1127. .algs_list = algs_md5_sha1,
  1128. .size = ARRAY_SIZE(algs_md5_sha1),
  1129. },
  1130. };
  1131. static const struct stm32_hash_pdata stm32_hash_pdata_stm32f4 = {
  1132. .algs_info = stm32_hash_algs_info_stm32f4,
  1133. .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f4),
  1134. };
  1135. static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f7[] = {
  1136. {
  1137. .algs_list = algs_md5_sha1,
  1138. .size = ARRAY_SIZE(algs_md5_sha1),
  1139. },
  1140. {
  1141. .algs_list = algs_sha224_sha256,
  1142. .size = ARRAY_SIZE(algs_sha224_sha256),
  1143. },
  1144. };
  1145. static const struct stm32_hash_pdata stm32_hash_pdata_stm32f7 = {
  1146. .algs_info = stm32_hash_algs_info_stm32f7,
  1147. .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f7),
  1148. };
  1149. static const struct of_device_id stm32_hash_of_match[] = {
  1150. {
  1151. .compatible = "st,stm32f456-hash",
  1152. .data = &stm32_hash_pdata_stm32f4,
  1153. },
  1154. {
  1155. .compatible = "st,stm32f756-hash",
  1156. .data = &stm32_hash_pdata_stm32f7,
  1157. },
  1158. {},
  1159. };
  1160. MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
  1161. static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
  1162. struct device *dev)
  1163. {
  1164. const struct of_device_id *match;
  1165. int err;
  1166. match = of_match_device(stm32_hash_of_match, dev);
  1167. if (!match) {
  1168. dev_err(dev, "no compatible OF match\n");
  1169. return -EINVAL;
  1170. }
  1171. err = of_property_read_u32(dev->of_node, "dma-maxburst",
  1172. &hdev->dma_maxburst);
  1173. hdev->pdata = match->data;
  1174. return err;
  1175. }
  1176. static int stm32_hash_probe(struct platform_device *pdev)
  1177. {
  1178. struct stm32_hash_dev *hdev;
  1179. struct device *dev = &pdev->dev;
  1180. struct resource *res;
  1181. int ret, irq;
  1182. hdev = devm_kzalloc(dev, sizeof(*hdev), GFP_KERNEL);
  1183. if (!hdev)
  1184. return -ENOMEM;
  1185. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1186. hdev->io_base = devm_ioremap_resource(dev, res);
  1187. if (IS_ERR(hdev->io_base))
  1188. return PTR_ERR(hdev->io_base);
  1189. hdev->phys_base = res->start;
  1190. ret = stm32_hash_get_of_match(hdev, dev);
  1191. if (ret)
  1192. return ret;
  1193. irq = platform_get_irq(pdev, 0);
  1194. if (irq < 0) {
  1195. dev_err(dev, "Cannot get IRQ resource\n");
  1196. return irq;
  1197. }
  1198. ret = devm_request_threaded_irq(dev, irq, stm32_hash_irq_handler,
  1199. stm32_hash_irq_thread, IRQF_ONESHOT,
  1200. dev_name(dev), hdev);
  1201. if (ret) {
  1202. dev_err(dev, "Cannot grab IRQ\n");
  1203. return ret;
  1204. }
  1205. hdev->clk = devm_clk_get(&pdev->dev, NULL);
  1206. if (IS_ERR(hdev->clk)) {
  1207. dev_err(dev, "failed to get clock for hash (%lu)\n",
  1208. PTR_ERR(hdev->clk));
  1209. return PTR_ERR(hdev->clk);
  1210. }
  1211. ret = clk_prepare_enable(hdev->clk);
  1212. if (ret) {
  1213. dev_err(dev, "failed to enable hash clock (%d)\n", ret);
  1214. return ret;
  1215. }
  1216. hdev->rst = devm_reset_control_get(&pdev->dev, NULL);
  1217. if (!IS_ERR(hdev->rst)) {
  1218. reset_control_assert(hdev->rst);
  1219. udelay(2);
  1220. reset_control_deassert(hdev->rst);
  1221. }
  1222. hdev->dev = dev;
  1223. platform_set_drvdata(pdev, hdev);
  1224. ret = stm32_hash_dma_init(hdev);
  1225. if (ret)
  1226. dev_dbg(dev, "DMA mode not available\n");
  1227. spin_lock(&stm32_hash.lock);
  1228. list_add_tail(&hdev->list, &stm32_hash.dev_list);
  1229. spin_unlock(&stm32_hash.lock);
  1230. /* Initialize crypto engine */
  1231. hdev->engine = crypto_engine_alloc_init(dev, 1);
  1232. if (!hdev->engine) {
  1233. ret = -ENOMEM;
  1234. goto err_engine;
  1235. }
  1236. hdev->engine->prepare_hash_request = stm32_hash_prepare_req;
  1237. hdev->engine->hash_one_request = stm32_hash_one_request;
  1238. ret = crypto_engine_start(hdev->engine);
  1239. if (ret)
  1240. goto err_engine_start;
  1241. hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR);
  1242. /* Register algos */
  1243. ret = stm32_hash_register_algs(hdev);
  1244. if (ret)
  1245. goto err_algs;
  1246. dev_info(dev, "Init HASH done HW ver %x DMA mode %u\n",
  1247. stm32_hash_read(hdev, HASH_VER), hdev->dma_mode);
  1248. return 0;
  1249. err_algs:
  1250. err_engine_start:
  1251. crypto_engine_exit(hdev->engine);
  1252. err_engine:
  1253. spin_lock(&stm32_hash.lock);
  1254. list_del(&hdev->list);
  1255. spin_unlock(&stm32_hash.lock);
  1256. if (hdev->dma_lch)
  1257. dma_release_channel(hdev->dma_lch);
  1258. clk_disable_unprepare(hdev->clk);
  1259. return ret;
  1260. }
  1261. static int stm32_hash_remove(struct platform_device *pdev)
  1262. {
  1263. static struct stm32_hash_dev *hdev;
  1264. hdev = platform_get_drvdata(pdev);
  1265. if (!hdev)
  1266. return -ENODEV;
  1267. stm32_hash_unregister_algs(hdev);
  1268. crypto_engine_exit(hdev->engine);
  1269. spin_lock(&stm32_hash.lock);
  1270. list_del(&hdev->list);
  1271. spin_unlock(&stm32_hash.lock);
  1272. if (hdev->dma_lch)
  1273. dma_release_channel(hdev->dma_lch);
  1274. clk_disable_unprepare(hdev->clk);
  1275. return 0;
  1276. }
  1277. static struct platform_driver stm32_hash_driver = {
  1278. .probe = stm32_hash_probe,
  1279. .remove = stm32_hash_remove,
  1280. .driver = {
  1281. .name = "stm32-hash",
  1282. .of_match_table = stm32_hash_of_match,
  1283. }
  1284. };
  1285. module_platform_driver(stm32_hash_driver);
  1286. MODULE_DESCRIPTION("STM32 SHA1/224/256 & MD5 (HMAC) hw accelerator driver");
  1287. MODULE_AUTHOR("Lionel Debieve <lionel.debieve@st.com>");
  1288. MODULE_LICENSE("GPL v2");