qi.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * CAAM/SEC 4.x QI transport/backend driver
  4. * Queue Interface backend functionality
  5. *
  6. * Copyright 2013-2016 Freescale Semiconductor, Inc.
  7. * Copyright 2016-2017 NXP
  8. */
  9. #include <linux/cpumask.h>
  10. #include <linux/kthread.h>
  11. #include <soc/fsl/qman.h>
  12. #include "regs.h"
  13. #include "qi.h"
  14. #include "desc.h"
  15. #include "intern.h"
  16. #include "desc_constr.h"
  17. #define PREHDR_RSLS_SHIFT 31
  18. /*
  19. * Use a reasonable backlog of frames (per CPU) as congestion threshold,
  20. * so that resources used by the in-flight buffers do not become a memory hog.
  21. */
  22. #define MAX_RSP_FQ_BACKLOG_PER_CPU 256
  23. #define CAAM_QI_ENQUEUE_RETRIES 10000
  24. #define CAAM_NAPI_WEIGHT 63
  25. /*
  26. * caam_napi - struct holding CAAM NAPI-related params
  27. * @irqtask: IRQ task for QI backend
  28. * @p: QMan portal
  29. */
  30. struct caam_napi {
  31. struct napi_struct irqtask;
  32. struct qman_portal *p;
  33. };
  34. /*
  35. * caam_qi_pcpu_priv - percpu private data structure to main list of pending
  36. * responses expected on each cpu.
  37. * @caam_napi: CAAM NAPI params
  38. * @net_dev: netdev used by NAPI
  39. * @rsp_fq: response FQ from CAAM
  40. */
  41. struct caam_qi_pcpu_priv {
  42. struct caam_napi caam_napi;
  43. struct net_device net_dev;
  44. struct qman_fq *rsp_fq;
  45. } ____cacheline_aligned;
  46. static DEFINE_PER_CPU(struct caam_qi_pcpu_priv, pcpu_qipriv);
  47. static DEFINE_PER_CPU(int, last_cpu);
  48. /*
  49. * caam_qi_priv - CAAM QI backend private params
  50. * @cgr: QMan congestion group
  51. * @qi_pdev: platform device for QI backend
  52. */
  53. struct caam_qi_priv {
  54. struct qman_cgr cgr;
  55. struct platform_device *qi_pdev;
  56. };
  57. static struct caam_qi_priv qipriv ____cacheline_aligned;
  58. /*
  59. * This is written by only one core - the one that initialized the CGR - and
  60. * read by multiple cores (all the others).
  61. */
  62. bool caam_congested __read_mostly;
  63. EXPORT_SYMBOL(caam_congested);
  64. #ifdef CONFIG_DEBUG_FS
  65. /*
  66. * This is a counter for the number of times the congestion group (where all
  67. * the request and response queueus are) reached congestion. Incremented
  68. * each time the congestion callback is called with congested == true.
  69. */
  70. static u64 times_congested;
  71. #endif
  72. /*
  73. * CPU from where the module initialised. This is required because QMan driver
  74. * requires CGRs to be removed from same CPU from where they were originally
  75. * allocated.
  76. */
  77. static int mod_init_cpu;
  78. /*
  79. * This is a a cache of buffers, from which the users of CAAM QI driver
  80. * can allocate short (CAAM_QI_MEMCACHE_SIZE) buffers. It's faster than
  81. * doing malloc on the hotpath.
  82. * NOTE: A more elegant solution would be to have some headroom in the frames
  83. * being processed. This could be added by the dpaa-ethernet driver.
  84. * This would pose a problem for userspace application processing which
  85. * cannot know of this limitation. So for now, this will work.
  86. * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
  87. */
  88. static struct kmem_cache *qi_cache;
  89. int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req)
  90. {
  91. struct qm_fd fd;
  92. dma_addr_t addr;
  93. int ret;
  94. int num_retries = 0;
  95. qm_fd_clear_fd(&fd);
  96. qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1]));
  97. addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt),
  98. DMA_BIDIRECTIONAL);
  99. if (dma_mapping_error(qidev, addr)) {
  100. dev_err(qidev, "DMA mapping error for QI enqueue request\n");
  101. return -EIO;
  102. }
  103. qm_fd_addr_set64(&fd, addr);
  104. do {
  105. ret = qman_enqueue(req->drv_ctx->req_fq, &fd);
  106. if (likely(!ret))
  107. return 0;
  108. if (ret != -EBUSY)
  109. break;
  110. num_retries++;
  111. } while (num_retries < CAAM_QI_ENQUEUE_RETRIES);
  112. dev_err(qidev, "qman_enqueue failed: %d\n", ret);
  113. return ret;
  114. }
  115. EXPORT_SYMBOL(caam_qi_enqueue);
  116. static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,
  117. const union qm_mr_entry *msg)
  118. {
  119. const struct qm_fd *fd;
  120. struct caam_drv_req *drv_req;
  121. struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
  122. fd = &msg->ern.fd;
  123. if (qm_fd_get_format(fd) != qm_fd_compound) {
  124. dev_err(qidev, "Non-compound FD from CAAM\n");
  125. return;
  126. }
  127. drv_req = (struct caam_drv_req *)phys_to_virt(qm_fd_addr_get64(fd));
  128. if (!drv_req) {
  129. dev_err(qidev,
  130. "Can't find original request for CAAM response\n");
  131. return;
  132. }
  133. dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
  134. sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
  135. drv_req->cbk(drv_req, -EIO);
  136. }
  137. static struct qman_fq *create_caam_req_fq(struct device *qidev,
  138. struct qman_fq *rsp_fq,
  139. dma_addr_t hwdesc,
  140. int fq_sched_flag)
  141. {
  142. int ret;
  143. struct qman_fq *req_fq;
  144. struct qm_mcc_initfq opts;
  145. req_fq = kzalloc(sizeof(*req_fq), GFP_ATOMIC);
  146. if (!req_fq)
  147. return ERR_PTR(-ENOMEM);
  148. req_fq->cb.ern = caam_fq_ern_cb;
  149. req_fq->cb.fqs = NULL;
  150. ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
  151. QMAN_FQ_FLAG_TO_DCPORTAL, req_fq);
  152. if (ret) {
  153. dev_err(qidev, "Failed to create session req FQ\n");
  154. goto create_req_fq_fail;
  155. }
  156. memset(&opts, 0, sizeof(opts));
  157. opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
  158. QM_INITFQ_WE_CONTEXTB |
  159. QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
  160. opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
  161. qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2);
  162. opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq));
  163. qm_fqd_context_a_set64(&opts.fqd, hwdesc);
  164. opts.fqd.cgid = qipriv.cgr.cgrid;
  165. ret = qman_init_fq(req_fq, fq_sched_flag, &opts);
  166. if (ret) {
  167. dev_err(qidev, "Failed to init session req FQ\n");
  168. goto init_req_fq_fail;
  169. }
  170. dev_dbg(qidev, "Allocated request FQ %u for CPU %u\n", req_fq->fqid,
  171. smp_processor_id());
  172. return req_fq;
  173. init_req_fq_fail:
  174. qman_destroy_fq(req_fq);
  175. create_req_fq_fail:
  176. kfree(req_fq);
  177. return ERR_PTR(ret);
  178. }
  179. static int empty_retired_fq(struct device *qidev, struct qman_fq *fq)
  180. {
  181. int ret;
  182. ret = qman_volatile_dequeue(fq, QMAN_VOLATILE_FLAG_WAIT_INT |
  183. QMAN_VOLATILE_FLAG_FINISH,
  184. QM_VDQCR_PRECEDENCE_VDQCR |
  185. QM_VDQCR_NUMFRAMES_TILLEMPTY);
  186. if (ret) {
  187. dev_err(qidev, "Volatile dequeue fail for FQ: %u\n", fq->fqid);
  188. return ret;
  189. }
  190. do {
  191. struct qman_portal *p;
  192. p = qman_get_affine_portal(smp_processor_id());
  193. qman_p_poll_dqrr(p, 16);
  194. } while (fq->flags & QMAN_FQ_STATE_NE);
  195. return 0;
  196. }
  197. static int kill_fq(struct device *qidev, struct qman_fq *fq)
  198. {
  199. u32 flags;
  200. int ret;
  201. ret = qman_retire_fq(fq, &flags);
  202. if (ret < 0) {
  203. dev_err(qidev, "qman_retire_fq failed: %d\n", ret);
  204. return ret;
  205. }
  206. if (!ret)
  207. goto empty_fq;
  208. /* Async FQ retirement condition */
  209. if (ret == 1) {
  210. /* Retry till FQ gets in retired state */
  211. do {
  212. msleep(20);
  213. } while (fq->state != qman_fq_state_retired);
  214. WARN_ON(fq->flags & QMAN_FQ_STATE_BLOCKOOS);
  215. WARN_ON(fq->flags & QMAN_FQ_STATE_ORL);
  216. }
  217. empty_fq:
  218. if (fq->flags & QMAN_FQ_STATE_NE) {
  219. ret = empty_retired_fq(qidev, fq);
  220. if (ret) {
  221. dev_err(qidev, "empty_retired_fq fail for FQ: %u\n",
  222. fq->fqid);
  223. return ret;
  224. }
  225. }
  226. ret = qman_oos_fq(fq);
  227. if (ret)
  228. dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid);
  229. qman_destroy_fq(fq);
  230. kfree(fq);
  231. return ret;
  232. }
  233. static int empty_caam_fq(struct qman_fq *fq)
  234. {
  235. int ret;
  236. struct qm_mcr_queryfq_np np;
  237. /* Wait till the older CAAM FQ get empty */
  238. do {
  239. ret = qman_query_fq_np(fq, &np);
  240. if (ret)
  241. return ret;
  242. if (!qm_mcr_np_get(&np, frm_cnt))
  243. break;
  244. msleep(20);
  245. } while (1);
  246. /*
  247. * Give extra time for pending jobs from this FQ in holding tanks
  248. * to get processed
  249. */
  250. msleep(20);
  251. return 0;
  252. }
  253. int caam_drv_ctx_update(struct caam_drv_ctx *drv_ctx, u32 *sh_desc)
  254. {
  255. int ret;
  256. u32 num_words;
  257. struct qman_fq *new_fq, *old_fq;
  258. struct device *qidev = drv_ctx->qidev;
  259. num_words = desc_len(sh_desc);
  260. if (num_words > MAX_SDLEN) {
  261. dev_err(qidev, "Invalid descriptor len: %d words\n", num_words);
  262. return -EINVAL;
  263. }
  264. /* Note down older req FQ */
  265. old_fq = drv_ctx->req_fq;
  266. /* Create a new req FQ in parked state */
  267. new_fq = create_caam_req_fq(drv_ctx->qidev, drv_ctx->rsp_fq,
  268. drv_ctx->context_a, 0);
  269. if (unlikely(IS_ERR_OR_NULL(new_fq))) {
  270. dev_err(qidev, "FQ allocation for shdesc update failed\n");
  271. return PTR_ERR(new_fq);
  272. }
  273. /* Hook up new FQ to context so that new requests keep queuing */
  274. drv_ctx->req_fq = new_fq;
  275. /* Empty and remove the older FQ */
  276. ret = empty_caam_fq(old_fq);
  277. if (ret) {
  278. dev_err(qidev, "Old CAAM FQ empty failed: %d\n", ret);
  279. /* We can revert to older FQ */
  280. drv_ctx->req_fq = old_fq;
  281. if (kill_fq(qidev, new_fq))
  282. dev_warn(qidev, "New CAAM FQ kill failed\n");
  283. return ret;
  284. }
  285. /*
  286. * Re-initialise pre-header. Set RSLS and SDLEN.
  287. * Update the shared descriptor for driver context.
  288. */
  289. drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
  290. num_words);
  291. memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
  292. dma_sync_single_for_device(qidev, drv_ctx->context_a,
  293. sizeof(drv_ctx->sh_desc) +
  294. sizeof(drv_ctx->prehdr),
  295. DMA_BIDIRECTIONAL);
  296. /* Put the new FQ in scheduled state */
  297. ret = qman_schedule_fq(new_fq);
  298. if (ret) {
  299. dev_err(qidev, "Fail to sched new CAAM FQ, ecode = %d\n", ret);
  300. /*
  301. * We can kill new FQ and revert to old FQ.
  302. * Since the desc is already modified, it is success case
  303. */
  304. drv_ctx->req_fq = old_fq;
  305. if (kill_fq(qidev, new_fq))
  306. dev_warn(qidev, "New CAAM FQ kill failed\n");
  307. } else if (kill_fq(qidev, old_fq)) {
  308. dev_warn(qidev, "Old CAAM FQ kill failed\n");
  309. }
  310. return 0;
  311. }
  312. EXPORT_SYMBOL(caam_drv_ctx_update);
  313. struct caam_drv_ctx *caam_drv_ctx_init(struct device *qidev,
  314. int *cpu,
  315. u32 *sh_desc)
  316. {
  317. size_t size;
  318. u32 num_words;
  319. dma_addr_t hwdesc;
  320. struct caam_drv_ctx *drv_ctx;
  321. const cpumask_t *cpus = qman_affine_cpus();
  322. num_words = desc_len(sh_desc);
  323. if (num_words > MAX_SDLEN) {
  324. dev_err(qidev, "Invalid descriptor len: %d words\n",
  325. num_words);
  326. return ERR_PTR(-EINVAL);
  327. }
  328. drv_ctx = kzalloc(sizeof(*drv_ctx), GFP_ATOMIC);
  329. if (!drv_ctx)
  330. return ERR_PTR(-ENOMEM);
  331. /*
  332. * Initialise pre-header - set RSLS and SDLEN - and shared descriptor
  333. * and dma-map them.
  334. */
  335. drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
  336. num_words);
  337. memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
  338. size = sizeof(drv_ctx->prehdr) + sizeof(drv_ctx->sh_desc);
  339. hwdesc = dma_map_single(qidev, drv_ctx->prehdr, size,
  340. DMA_BIDIRECTIONAL);
  341. if (dma_mapping_error(qidev, hwdesc)) {
  342. dev_err(qidev, "DMA map error for preheader + shdesc\n");
  343. kfree(drv_ctx);
  344. return ERR_PTR(-ENOMEM);
  345. }
  346. drv_ctx->context_a = hwdesc;
  347. /* If given CPU does not own the portal, choose another one that does */
  348. if (!cpumask_test_cpu(*cpu, cpus)) {
  349. int *pcpu = &get_cpu_var(last_cpu);
  350. *pcpu = cpumask_next(*pcpu, cpus);
  351. if (*pcpu >= nr_cpu_ids)
  352. *pcpu = cpumask_first(cpus);
  353. *cpu = *pcpu;
  354. put_cpu_var(last_cpu);
  355. }
  356. drv_ctx->cpu = *cpu;
  357. /* Find response FQ hooked with this CPU */
  358. drv_ctx->rsp_fq = per_cpu(pcpu_qipriv.rsp_fq, drv_ctx->cpu);
  359. /* Attach request FQ */
  360. drv_ctx->req_fq = create_caam_req_fq(qidev, drv_ctx->rsp_fq, hwdesc,
  361. QMAN_INITFQ_FLAG_SCHED);
  362. if (unlikely(IS_ERR_OR_NULL(drv_ctx->req_fq))) {
  363. dev_err(qidev, "create_caam_req_fq failed\n");
  364. dma_unmap_single(qidev, hwdesc, size, DMA_BIDIRECTIONAL);
  365. kfree(drv_ctx);
  366. return ERR_PTR(-ENOMEM);
  367. }
  368. drv_ctx->qidev = qidev;
  369. return drv_ctx;
  370. }
  371. EXPORT_SYMBOL(caam_drv_ctx_init);
  372. void *qi_cache_alloc(gfp_t flags)
  373. {
  374. return kmem_cache_alloc(qi_cache, flags);
  375. }
  376. EXPORT_SYMBOL(qi_cache_alloc);
  377. void qi_cache_free(void *obj)
  378. {
  379. kmem_cache_free(qi_cache, obj);
  380. }
  381. EXPORT_SYMBOL(qi_cache_free);
  382. static int caam_qi_poll(struct napi_struct *napi, int budget)
  383. {
  384. struct caam_napi *np = container_of(napi, struct caam_napi, irqtask);
  385. int cleaned = qman_p_poll_dqrr(np->p, budget);
  386. if (cleaned < budget) {
  387. napi_complete(napi);
  388. qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
  389. }
  390. return cleaned;
  391. }
  392. void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx)
  393. {
  394. if (IS_ERR_OR_NULL(drv_ctx))
  395. return;
  396. /* Remove request FQ */
  397. if (kill_fq(drv_ctx->qidev, drv_ctx->req_fq))
  398. dev_err(drv_ctx->qidev, "Crypto session req FQ kill failed\n");
  399. dma_unmap_single(drv_ctx->qidev, drv_ctx->context_a,
  400. sizeof(drv_ctx->sh_desc) + sizeof(drv_ctx->prehdr),
  401. DMA_BIDIRECTIONAL);
  402. kfree(drv_ctx);
  403. }
  404. EXPORT_SYMBOL(caam_drv_ctx_rel);
  405. int caam_qi_shutdown(struct device *qidev)
  406. {
  407. int i, ret;
  408. struct caam_qi_priv *priv = dev_get_drvdata(qidev);
  409. const cpumask_t *cpus = qman_affine_cpus();
  410. struct cpumask old_cpumask = current->cpus_allowed;
  411. for_each_cpu(i, cpus) {
  412. struct napi_struct *irqtask;
  413. irqtask = &per_cpu_ptr(&pcpu_qipriv.caam_napi, i)->irqtask;
  414. napi_disable(irqtask);
  415. netif_napi_del(irqtask);
  416. if (kill_fq(qidev, per_cpu(pcpu_qipriv.rsp_fq, i)))
  417. dev_err(qidev, "Rsp FQ kill failed, cpu: %d\n", i);
  418. }
  419. /*
  420. * QMan driver requires CGRs to be deleted from same CPU from where they
  421. * were instantiated. Hence we get the module removal execute from the
  422. * same CPU from where it was originally inserted.
  423. */
  424. set_cpus_allowed_ptr(current, get_cpu_mask(mod_init_cpu));
  425. ret = qman_delete_cgr(&priv->cgr);
  426. if (ret)
  427. dev_err(qidev, "Deletion of CGR failed: %d\n", ret);
  428. else
  429. qman_release_cgrid(priv->cgr.cgrid);
  430. kmem_cache_destroy(qi_cache);
  431. /* Now that we're done with the CGRs, restore the cpus allowed mask */
  432. set_cpus_allowed_ptr(current, &old_cpumask);
  433. platform_device_unregister(priv->qi_pdev);
  434. return ret;
  435. }
  436. static void cgr_cb(struct qman_portal *qm, struct qman_cgr *cgr, int congested)
  437. {
  438. caam_congested = congested;
  439. if (congested) {
  440. #ifdef CONFIG_DEBUG_FS
  441. times_congested++;
  442. #endif
  443. pr_debug_ratelimited("CAAM entered congestion\n");
  444. } else {
  445. pr_debug_ratelimited("CAAM exited congestion\n");
  446. }
  447. }
  448. static int caam_qi_napi_schedule(struct qman_portal *p, struct caam_napi *np)
  449. {
  450. /*
  451. * In case of threaded ISR, for RT kernels in_irq() does not return
  452. * appropriate value, so use in_serving_softirq to distinguish between
  453. * softirq and irq contexts.
  454. */
  455. if (unlikely(in_irq() || !in_serving_softirq())) {
  456. /* Disable QMan IRQ source and invoke NAPI */
  457. qman_p_irqsource_remove(p, QM_PIRQ_DQRI);
  458. np->p = p;
  459. napi_schedule(&np->irqtask);
  460. return 1;
  461. }
  462. return 0;
  463. }
  464. static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p,
  465. struct qman_fq *rsp_fq,
  466. const struct qm_dqrr_entry *dqrr)
  467. {
  468. struct caam_napi *caam_napi = raw_cpu_ptr(&pcpu_qipriv.caam_napi);
  469. struct caam_drv_req *drv_req;
  470. const struct qm_fd *fd;
  471. struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
  472. u32 status;
  473. if (caam_qi_napi_schedule(p, caam_napi))
  474. return qman_cb_dqrr_stop;
  475. fd = &dqrr->fd;
  476. status = be32_to_cpu(fd->status);
  477. if (unlikely(status))
  478. dev_err(qidev, "Error: %#x in CAAM response FD\n", status);
  479. if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) {
  480. dev_err(qidev, "Non-compound FD from CAAM\n");
  481. return qman_cb_dqrr_consume;
  482. }
  483. drv_req = (struct caam_drv_req *)phys_to_virt(qm_fd_addr_get64(fd));
  484. if (unlikely(!drv_req)) {
  485. dev_err(qidev,
  486. "Can't find original request for caam response\n");
  487. return qman_cb_dqrr_consume;
  488. }
  489. dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
  490. sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
  491. drv_req->cbk(drv_req, status);
  492. return qman_cb_dqrr_consume;
  493. }
  494. static int alloc_rsp_fq_cpu(struct device *qidev, unsigned int cpu)
  495. {
  496. struct qm_mcc_initfq opts;
  497. struct qman_fq *fq;
  498. int ret;
  499. fq = kzalloc(sizeof(*fq), GFP_KERNEL | GFP_DMA);
  500. if (!fq)
  501. return -ENOMEM;
  502. fq->cb.dqrr = caam_rsp_fq_dqrr_cb;
  503. ret = qman_create_fq(0, QMAN_FQ_FLAG_NO_ENQUEUE |
  504. QMAN_FQ_FLAG_DYNAMIC_FQID, fq);
  505. if (ret) {
  506. dev_err(qidev, "Rsp FQ create failed\n");
  507. kfree(fq);
  508. return -ENODEV;
  509. }
  510. memset(&opts, 0, sizeof(opts));
  511. opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
  512. QM_INITFQ_WE_CONTEXTB |
  513. QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
  514. opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING |
  515. QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
  516. qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3);
  517. opts.fqd.cgid = qipriv.cgr.cgrid;
  518. opts.fqd.context_a.stashing.exclusive = QM_STASHING_EXCL_CTX |
  519. QM_STASHING_EXCL_DATA;
  520. qm_fqd_set_stashing(&opts.fqd, 0, 1, 1);
  521. ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
  522. if (ret) {
  523. dev_err(qidev, "Rsp FQ init failed\n");
  524. kfree(fq);
  525. return -ENODEV;
  526. }
  527. per_cpu(pcpu_qipriv.rsp_fq, cpu) = fq;
  528. dev_dbg(qidev, "Allocated response FQ %u for CPU %u", fq->fqid, cpu);
  529. return 0;
  530. }
  531. static int init_cgr(struct device *qidev)
  532. {
  533. int ret;
  534. struct qm_mcc_initcgr opts;
  535. const u64 cpus = *(u64 *)qman_affine_cpus();
  536. const int num_cpus = hweight64(cpus);
  537. const u64 val = num_cpus * MAX_RSP_FQ_BACKLOG_PER_CPU;
  538. ret = qman_alloc_cgrid(&qipriv.cgr.cgrid);
  539. if (ret) {
  540. dev_err(qidev, "CGR alloc failed for rsp FQs: %d\n", ret);
  541. return ret;
  542. }
  543. qipriv.cgr.cb = cgr_cb;
  544. memset(&opts, 0, sizeof(opts));
  545. opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES |
  546. QM_CGR_WE_MODE);
  547. opts.cgr.cscn_en = QM_CGR_EN;
  548. opts.cgr.mode = QMAN_CGR_MODE_FRAME;
  549. qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1);
  550. ret = qman_create_cgr(&qipriv.cgr, QMAN_CGR_FLAG_USE_INIT, &opts);
  551. if (ret) {
  552. dev_err(qidev, "Error %d creating CAAM CGRID: %u\n", ret,
  553. qipriv.cgr.cgrid);
  554. return ret;
  555. }
  556. dev_dbg(qidev, "Congestion threshold set to %llu\n", val);
  557. return 0;
  558. }
  559. static int alloc_rsp_fqs(struct device *qidev)
  560. {
  561. int ret, i;
  562. const cpumask_t *cpus = qman_affine_cpus();
  563. /*Now create response FQs*/
  564. for_each_cpu(i, cpus) {
  565. ret = alloc_rsp_fq_cpu(qidev, i);
  566. if (ret) {
  567. dev_err(qidev, "CAAM rsp FQ alloc failed, cpu: %u", i);
  568. return ret;
  569. }
  570. }
  571. return 0;
  572. }
  573. static void free_rsp_fqs(void)
  574. {
  575. int i;
  576. const cpumask_t *cpus = qman_affine_cpus();
  577. for_each_cpu(i, cpus)
  578. kfree(per_cpu(pcpu_qipriv.rsp_fq, i));
  579. }
  580. int caam_qi_init(struct platform_device *caam_pdev)
  581. {
  582. int err, i;
  583. struct platform_device *qi_pdev;
  584. struct device *ctrldev = &caam_pdev->dev, *qidev;
  585. struct caam_drv_private *ctrlpriv;
  586. const cpumask_t *cpus = qman_affine_cpus();
  587. struct cpumask old_cpumask = current->cpus_allowed;
  588. static struct platform_device_info qi_pdev_info = {
  589. .name = "caam_qi",
  590. .id = PLATFORM_DEVID_NONE
  591. };
  592. /*
  593. * QMAN requires CGRs to be removed from same CPU+portal from where it
  594. * was originally allocated. Hence we need to note down the
  595. * initialisation CPU and use the same CPU for module exit.
  596. * We select the first CPU to from the list of portal owning CPUs.
  597. * Then we pin module init to this CPU.
  598. */
  599. mod_init_cpu = cpumask_first(cpus);
  600. set_cpus_allowed_ptr(current, get_cpu_mask(mod_init_cpu));
  601. qi_pdev_info.parent = ctrldev;
  602. qi_pdev_info.dma_mask = dma_get_mask(ctrldev);
  603. qi_pdev = platform_device_register_full(&qi_pdev_info);
  604. if (IS_ERR(qi_pdev))
  605. return PTR_ERR(qi_pdev);
  606. set_dma_ops(&qi_pdev->dev, get_dma_ops(ctrldev));
  607. ctrlpriv = dev_get_drvdata(ctrldev);
  608. qidev = &qi_pdev->dev;
  609. qipriv.qi_pdev = qi_pdev;
  610. dev_set_drvdata(qidev, &qipriv);
  611. /* Initialize the congestion detection */
  612. err = init_cgr(qidev);
  613. if (err) {
  614. dev_err(qidev, "CGR initialization failed: %d\n", err);
  615. platform_device_unregister(qi_pdev);
  616. return err;
  617. }
  618. /* Initialise response FQs */
  619. err = alloc_rsp_fqs(qidev);
  620. if (err) {
  621. dev_err(qidev, "Can't allocate CAAM response FQs: %d\n", err);
  622. free_rsp_fqs();
  623. platform_device_unregister(qi_pdev);
  624. return err;
  625. }
  626. /*
  627. * Enable the NAPI contexts on each of the core which has an affine
  628. * portal.
  629. */
  630. for_each_cpu(i, cpus) {
  631. struct caam_qi_pcpu_priv *priv = per_cpu_ptr(&pcpu_qipriv, i);
  632. struct caam_napi *caam_napi = &priv->caam_napi;
  633. struct napi_struct *irqtask = &caam_napi->irqtask;
  634. struct net_device *net_dev = &priv->net_dev;
  635. net_dev->dev = *qidev;
  636. INIT_LIST_HEAD(&net_dev->napi_list);
  637. netif_napi_add(net_dev, irqtask, caam_qi_poll,
  638. CAAM_NAPI_WEIGHT);
  639. napi_enable(irqtask);
  640. }
  641. /* Hook up QI device to parent controlling caam device */
  642. ctrlpriv->qidev = qidev;
  643. qi_cache = kmem_cache_create("caamqicache", CAAM_QI_MEMCACHE_SIZE, 0,
  644. SLAB_CACHE_DMA, NULL);
  645. if (!qi_cache) {
  646. dev_err(qidev, "Can't allocate CAAM cache\n");
  647. free_rsp_fqs();
  648. platform_device_unregister(qi_pdev);
  649. return -ENOMEM;
  650. }
  651. /* Done with the CGRs; restore the cpus allowed mask */
  652. set_cpus_allowed_ptr(current, &old_cpumask);
  653. #ifdef CONFIG_DEBUG_FS
  654. debugfs_create_file("qi_congested", 0444, ctrlpriv->ctl,
  655. &times_congested, &caam_fops_u64_ro);
  656. #endif
  657. dev_info(qidev, "Linux CAAM Queue I/F driver initialised\n");
  658. return 0;
  659. }