ymfpci_main.c 71 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/firmware.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/sched.h>
  26. #include <linux/slab.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <linux/io.h>
  30. #include <sound/core.h>
  31. #include <sound/control.h>
  32. #include <sound/info.h>
  33. #include <sound/tlv.h>
  34. #include "ymfpci.h"
  35. #include <sound/asoundef.h>
  36. #include <sound/mpu401.h>
  37. #include <asm/byteorder.h>
  38. /*
  39. * common I/O routines
  40. */
  41. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  42. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  43. {
  44. return readb(chip->reg_area_virt + offset);
  45. }
  46. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  47. {
  48. writeb(val, chip->reg_area_virt + offset);
  49. }
  50. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  51. {
  52. return readw(chip->reg_area_virt + offset);
  53. }
  54. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  55. {
  56. writew(val, chip->reg_area_virt + offset);
  57. }
  58. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  59. {
  60. return readl(chip->reg_area_virt + offset);
  61. }
  62. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  63. {
  64. writel(val, chip->reg_area_virt + offset);
  65. }
  66. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  67. {
  68. unsigned long end_time;
  69. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  70. end_time = jiffies + msecs_to_jiffies(750);
  71. do {
  72. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  73. return 0;
  74. schedule_timeout_uninterruptible(1);
  75. } while (time_before(jiffies, end_time));
  76. dev_err(chip->card->dev,
  77. "codec_ready: codec %i is not ready [0x%x]\n",
  78. secondary, snd_ymfpci_readw(chip, reg));
  79. return -EBUSY;
  80. }
  81. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  82. {
  83. struct snd_ymfpci *chip = ac97->private_data;
  84. u32 cmd;
  85. snd_ymfpci_codec_ready(chip, 0);
  86. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  87. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  88. }
  89. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  90. {
  91. struct snd_ymfpci *chip = ac97->private_data;
  92. if (snd_ymfpci_codec_ready(chip, 0))
  93. return ~0;
  94. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  95. if (snd_ymfpci_codec_ready(chip, 0))
  96. return ~0;
  97. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  98. int i;
  99. for (i = 0; i < 600; i++)
  100. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  101. }
  102. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  103. }
  104. /*
  105. * Misc routines
  106. */
  107. static u32 snd_ymfpci_calc_delta(u32 rate)
  108. {
  109. switch (rate) {
  110. case 8000: return 0x02aaab00;
  111. case 11025: return 0x03accd00;
  112. case 16000: return 0x05555500;
  113. case 22050: return 0x07599a00;
  114. case 32000: return 0x0aaaab00;
  115. case 44100: return 0x0eb33300;
  116. default: return ((rate << 16) / 375) << 5;
  117. }
  118. }
  119. static u32 def_rate[8] = {
  120. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  121. };
  122. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  123. {
  124. u32 i;
  125. static u32 val[8] = {
  126. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  127. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  128. };
  129. if (rate == 44100)
  130. return 0x40000000; /* FIXME: What's the right value? */
  131. for (i = 0; i < 8; i++)
  132. if (rate <= def_rate[i])
  133. return val[i];
  134. return val[0];
  135. }
  136. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  137. {
  138. u32 i;
  139. static u32 val[8] = {
  140. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  141. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  142. };
  143. if (rate == 44100)
  144. return 0x370A0000;
  145. for (i = 0; i < 8; i++)
  146. if (rate <= def_rate[i])
  147. return val[i];
  148. return val[0];
  149. }
  150. /*
  151. * Hardware start management
  152. */
  153. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  154. {
  155. unsigned long flags;
  156. spin_lock_irqsave(&chip->reg_lock, flags);
  157. if (chip->start_count++ > 0)
  158. goto __end;
  159. snd_ymfpci_writel(chip, YDSXGR_MODE,
  160. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  161. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  162. __end:
  163. spin_unlock_irqrestore(&chip->reg_lock, flags);
  164. }
  165. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  166. {
  167. unsigned long flags;
  168. long timeout = 1000;
  169. spin_lock_irqsave(&chip->reg_lock, flags);
  170. if (--chip->start_count > 0)
  171. goto __end;
  172. snd_ymfpci_writel(chip, YDSXGR_MODE,
  173. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  174. while (timeout-- > 0) {
  175. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  176. break;
  177. }
  178. if (atomic_read(&chip->interrupt_sleep_count)) {
  179. atomic_set(&chip->interrupt_sleep_count, 0);
  180. wake_up(&chip->interrupt_sleep);
  181. }
  182. __end:
  183. spin_unlock_irqrestore(&chip->reg_lock, flags);
  184. }
  185. /*
  186. * Playback voice management
  187. */
  188. static int voice_alloc(struct snd_ymfpci *chip,
  189. enum snd_ymfpci_voice_type type, int pair,
  190. struct snd_ymfpci_voice **rvoice)
  191. {
  192. struct snd_ymfpci_voice *voice, *voice2;
  193. int idx;
  194. *rvoice = NULL;
  195. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  196. voice = &chip->voices[idx];
  197. voice2 = pair ? &chip->voices[idx+1] : NULL;
  198. if (voice->use || (voice2 && voice2->use))
  199. continue;
  200. voice->use = 1;
  201. if (voice2)
  202. voice2->use = 1;
  203. switch (type) {
  204. case YMFPCI_PCM:
  205. voice->pcm = 1;
  206. if (voice2)
  207. voice2->pcm = 1;
  208. break;
  209. case YMFPCI_SYNTH:
  210. voice->synth = 1;
  211. break;
  212. case YMFPCI_MIDI:
  213. voice->midi = 1;
  214. break;
  215. }
  216. snd_ymfpci_hw_start(chip);
  217. if (voice2)
  218. snd_ymfpci_hw_start(chip);
  219. *rvoice = voice;
  220. return 0;
  221. }
  222. return -ENOMEM;
  223. }
  224. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  225. enum snd_ymfpci_voice_type type, int pair,
  226. struct snd_ymfpci_voice **rvoice)
  227. {
  228. unsigned long flags;
  229. int result;
  230. if (snd_BUG_ON(!rvoice))
  231. return -EINVAL;
  232. if (snd_BUG_ON(pair && type != YMFPCI_PCM))
  233. return -EINVAL;
  234. spin_lock_irqsave(&chip->voice_lock, flags);
  235. for (;;) {
  236. result = voice_alloc(chip, type, pair, rvoice);
  237. if (result == 0 || type != YMFPCI_PCM)
  238. break;
  239. /* TODO: synth/midi voice deallocation */
  240. break;
  241. }
  242. spin_unlock_irqrestore(&chip->voice_lock, flags);
  243. return result;
  244. }
  245. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  246. {
  247. unsigned long flags;
  248. if (snd_BUG_ON(!pvoice))
  249. return -EINVAL;
  250. snd_ymfpci_hw_stop(chip);
  251. spin_lock_irqsave(&chip->voice_lock, flags);
  252. if (pvoice->number == chip->src441_used) {
  253. chip->src441_used = -1;
  254. pvoice->ypcm->use_441_slot = 0;
  255. }
  256. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  257. pvoice->ypcm = NULL;
  258. pvoice->interrupt = NULL;
  259. spin_unlock_irqrestore(&chip->voice_lock, flags);
  260. return 0;
  261. }
  262. /*
  263. * PCM part
  264. */
  265. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  266. {
  267. struct snd_ymfpci_pcm *ypcm;
  268. u32 pos, delta;
  269. if ((ypcm = voice->ypcm) == NULL)
  270. return;
  271. if (ypcm->substream == NULL)
  272. return;
  273. spin_lock(&chip->reg_lock);
  274. if (ypcm->running) {
  275. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  276. if (pos < ypcm->last_pos)
  277. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  278. else
  279. delta = pos - ypcm->last_pos;
  280. ypcm->period_pos += delta;
  281. ypcm->last_pos = pos;
  282. if (ypcm->period_pos >= ypcm->period_size) {
  283. /*
  284. dev_dbg(chip->card->dev,
  285. "done - active_bank = 0x%x, start = 0x%x\n",
  286. chip->active_bank,
  287. voice->bank[chip->active_bank].start);
  288. */
  289. ypcm->period_pos %= ypcm->period_size;
  290. spin_unlock(&chip->reg_lock);
  291. snd_pcm_period_elapsed(ypcm->substream);
  292. spin_lock(&chip->reg_lock);
  293. }
  294. if (unlikely(ypcm->update_pcm_vol)) {
  295. unsigned int subs = ypcm->substream->number;
  296. unsigned int next_bank = 1 - chip->active_bank;
  297. struct snd_ymfpci_playback_bank *bank;
  298. u32 volume;
  299. bank = &voice->bank[next_bank];
  300. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  301. bank->left_gain_end = volume;
  302. if (ypcm->output_rear)
  303. bank->eff2_gain_end = volume;
  304. if (ypcm->voices[1])
  305. bank = &ypcm->voices[1]->bank[next_bank];
  306. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  307. bank->right_gain_end = volume;
  308. if (ypcm->output_rear)
  309. bank->eff3_gain_end = volume;
  310. ypcm->update_pcm_vol--;
  311. }
  312. }
  313. spin_unlock(&chip->reg_lock);
  314. }
  315. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  316. {
  317. struct snd_pcm_runtime *runtime = substream->runtime;
  318. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  319. struct snd_ymfpci *chip = ypcm->chip;
  320. u32 pos, delta;
  321. spin_lock(&chip->reg_lock);
  322. if (ypcm->running) {
  323. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  324. if (pos < ypcm->last_pos)
  325. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  326. else
  327. delta = pos - ypcm->last_pos;
  328. ypcm->period_pos += delta;
  329. ypcm->last_pos = pos;
  330. if (ypcm->period_pos >= ypcm->period_size) {
  331. ypcm->period_pos %= ypcm->period_size;
  332. /*
  333. dev_dbg(chip->card->dev,
  334. "done - active_bank = 0x%x, start = 0x%x\n",
  335. chip->active_bank,
  336. voice->bank[chip->active_bank].start);
  337. */
  338. spin_unlock(&chip->reg_lock);
  339. snd_pcm_period_elapsed(substream);
  340. spin_lock(&chip->reg_lock);
  341. }
  342. }
  343. spin_unlock(&chip->reg_lock);
  344. }
  345. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  346. int cmd)
  347. {
  348. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  349. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  350. struct snd_kcontrol *kctl = NULL;
  351. int result = 0;
  352. spin_lock(&chip->reg_lock);
  353. if (ypcm->voices[0] == NULL) {
  354. result = -EINVAL;
  355. goto __unlock;
  356. }
  357. switch (cmd) {
  358. case SNDRV_PCM_TRIGGER_START:
  359. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  360. case SNDRV_PCM_TRIGGER_RESUME:
  361. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  362. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  363. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  364. ypcm->running = 1;
  365. break;
  366. case SNDRV_PCM_TRIGGER_STOP:
  367. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  368. kctl = chip->pcm_mixer[substream->number].ctl;
  369. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  370. }
  371. /* fall through */
  372. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  373. case SNDRV_PCM_TRIGGER_SUSPEND:
  374. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  375. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  376. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  377. ypcm->running = 0;
  378. break;
  379. default:
  380. result = -EINVAL;
  381. break;
  382. }
  383. __unlock:
  384. spin_unlock(&chip->reg_lock);
  385. if (kctl)
  386. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  387. return result;
  388. }
  389. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  390. int cmd)
  391. {
  392. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  393. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  394. int result = 0;
  395. u32 tmp;
  396. spin_lock(&chip->reg_lock);
  397. switch (cmd) {
  398. case SNDRV_PCM_TRIGGER_START:
  399. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  400. case SNDRV_PCM_TRIGGER_RESUME:
  401. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  402. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  403. ypcm->running = 1;
  404. break;
  405. case SNDRV_PCM_TRIGGER_STOP:
  406. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  407. case SNDRV_PCM_TRIGGER_SUSPEND:
  408. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  409. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  410. ypcm->running = 0;
  411. break;
  412. default:
  413. result = -EINVAL;
  414. break;
  415. }
  416. spin_unlock(&chip->reg_lock);
  417. return result;
  418. }
  419. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  420. {
  421. int err;
  422. if (ypcm->voices[1] != NULL && voices < 2) {
  423. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  424. ypcm->voices[1] = NULL;
  425. }
  426. if (voices == 1 && ypcm->voices[0] != NULL)
  427. return 0; /* already allocated */
  428. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  429. return 0; /* already allocated */
  430. if (voices > 1) {
  431. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  432. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  433. ypcm->voices[0] = NULL;
  434. }
  435. }
  436. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  437. if (err < 0)
  438. return err;
  439. ypcm->voices[0]->ypcm = ypcm;
  440. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  441. if (voices > 1) {
  442. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  443. ypcm->voices[1]->ypcm = ypcm;
  444. }
  445. return 0;
  446. }
  447. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  448. struct snd_pcm_runtime *runtime,
  449. int has_pcm_volume)
  450. {
  451. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  452. u32 format;
  453. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  454. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  455. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  456. struct snd_ymfpci_playback_bank *bank;
  457. unsigned int nbank;
  458. u32 vol_left, vol_right;
  459. u8 use_left, use_right;
  460. unsigned long flags;
  461. if (snd_BUG_ON(!voice))
  462. return;
  463. if (runtime->channels == 1) {
  464. use_left = 1;
  465. use_right = 1;
  466. } else {
  467. use_left = (voiceidx & 1) == 0;
  468. use_right = !use_left;
  469. }
  470. if (has_pcm_volume) {
  471. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  472. [ypcm->substream->number].left << 15);
  473. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  474. [ypcm->substream->number].right << 15);
  475. } else {
  476. vol_left = cpu_to_le32(0x40000000);
  477. vol_right = cpu_to_le32(0x40000000);
  478. }
  479. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  480. format = runtime->channels == 2 ? 0x00010000 : 0;
  481. if (snd_pcm_format_width(runtime->format) == 8)
  482. format |= 0x80000000;
  483. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  484. runtime->rate == 44100 && runtime->channels == 2 &&
  485. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  486. ypcm->chip->src441_used == voice->number)) {
  487. ypcm->chip->src441_used = voice->number;
  488. ypcm->use_441_slot = 1;
  489. format |= 0x10000000;
  490. }
  491. if (ypcm->chip->src441_used == voice->number &&
  492. (format & 0x10000000) == 0) {
  493. ypcm->chip->src441_used = -1;
  494. ypcm->use_441_slot = 0;
  495. }
  496. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  497. format |= 1;
  498. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  499. for (nbank = 0; nbank < 2; nbank++) {
  500. bank = &voice->bank[nbank];
  501. memset(bank, 0, sizeof(*bank));
  502. bank->format = cpu_to_le32(format);
  503. bank->base = cpu_to_le32(runtime->dma_addr);
  504. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  505. bank->lpfQ = cpu_to_le32(lpfQ);
  506. bank->delta =
  507. bank->delta_end = cpu_to_le32(delta);
  508. bank->lpfK =
  509. bank->lpfK_end = cpu_to_le32(lpfK);
  510. bank->eg_gain =
  511. bank->eg_gain_end = cpu_to_le32(0x40000000);
  512. if (ypcm->output_front) {
  513. if (use_left) {
  514. bank->left_gain =
  515. bank->left_gain_end = vol_left;
  516. }
  517. if (use_right) {
  518. bank->right_gain =
  519. bank->right_gain_end = vol_right;
  520. }
  521. }
  522. if (ypcm->output_rear) {
  523. if (!ypcm->swap_rear) {
  524. if (use_left) {
  525. bank->eff2_gain =
  526. bank->eff2_gain_end = vol_left;
  527. }
  528. if (use_right) {
  529. bank->eff3_gain =
  530. bank->eff3_gain_end = vol_right;
  531. }
  532. } else {
  533. /* The SPDIF out channels seem to be swapped, so we have
  534. * to swap them here, too. The rear analog out channels
  535. * will be wrong, but otherwise AC3 would not work.
  536. */
  537. if (use_left) {
  538. bank->eff3_gain =
  539. bank->eff3_gain_end = vol_left;
  540. }
  541. if (use_right) {
  542. bank->eff2_gain =
  543. bank->eff2_gain_end = vol_right;
  544. }
  545. }
  546. }
  547. }
  548. }
  549. static int snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  550. {
  551. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  552. 4096, &chip->ac3_tmp_base) < 0)
  553. return -ENOMEM;
  554. chip->bank_effect[3][0]->base =
  555. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  556. chip->bank_effect[3][0]->loop_end =
  557. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  558. chip->bank_effect[4][0]->base =
  559. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  560. chip->bank_effect[4][0]->loop_end =
  561. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  562. spin_lock_irq(&chip->reg_lock);
  563. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  564. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  565. spin_unlock_irq(&chip->reg_lock);
  566. return 0;
  567. }
  568. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  569. {
  570. spin_lock_irq(&chip->reg_lock);
  571. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  572. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  573. spin_unlock_irq(&chip->reg_lock);
  574. // snd_ymfpci_irq_wait(chip);
  575. if (chip->ac3_tmp_base.area) {
  576. snd_dma_free_pages(&chip->ac3_tmp_base);
  577. chip->ac3_tmp_base.area = NULL;
  578. }
  579. return 0;
  580. }
  581. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  582. struct snd_pcm_hw_params *hw_params)
  583. {
  584. struct snd_pcm_runtime *runtime = substream->runtime;
  585. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  586. int err;
  587. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  588. return err;
  589. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  590. return err;
  591. return 0;
  592. }
  593. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  594. {
  595. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  596. struct snd_pcm_runtime *runtime = substream->runtime;
  597. struct snd_ymfpci_pcm *ypcm;
  598. if (runtime->private_data == NULL)
  599. return 0;
  600. ypcm = runtime->private_data;
  601. /* wait, until the PCI operations are not finished */
  602. snd_ymfpci_irq_wait(chip);
  603. snd_pcm_lib_free_pages(substream);
  604. if (ypcm->voices[1]) {
  605. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  606. ypcm->voices[1] = NULL;
  607. }
  608. if (ypcm->voices[0]) {
  609. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  610. ypcm->voices[0] = NULL;
  611. }
  612. return 0;
  613. }
  614. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  615. {
  616. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  617. struct snd_pcm_runtime *runtime = substream->runtime;
  618. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  619. struct snd_kcontrol *kctl;
  620. unsigned int nvoice;
  621. ypcm->period_size = runtime->period_size;
  622. ypcm->buffer_size = runtime->buffer_size;
  623. ypcm->period_pos = 0;
  624. ypcm->last_pos = 0;
  625. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  626. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  627. substream->pcm == chip->pcm);
  628. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  629. kctl = chip->pcm_mixer[substream->number].ctl;
  630. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  631. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  632. }
  633. return 0;
  634. }
  635. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  636. struct snd_pcm_hw_params *hw_params)
  637. {
  638. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  639. }
  640. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  641. {
  642. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  643. /* wait, until the PCI operations are not finished */
  644. snd_ymfpci_irq_wait(chip);
  645. return snd_pcm_lib_free_pages(substream);
  646. }
  647. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  648. {
  649. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  650. struct snd_pcm_runtime *runtime = substream->runtime;
  651. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  652. struct snd_ymfpci_capture_bank * bank;
  653. int nbank;
  654. u32 rate, format;
  655. ypcm->period_size = runtime->period_size;
  656. ypcm->buffer_size = runtime->buffer_size;
  657. ypcm->period_pos = 0;
  658. ypcm->last_pos = 0;
  659. ypcm->shift = 0;
  660. rate = ((48000 * 4096) / runtime->rate) - 1;
  661. format = 0;
  662. if (runtime->channels == 2) {
  663. format |= 2;
  664. ypcm->shift++;
  665. }
  666. if (snd_pcm_format_width(runtime->format) == 8)
  667. format |= 1;
  668. else
  669. ypcm->shift++;
  670. switch (ypcm->capture_bank_number) {
  671. case 0:
  672. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  673. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  674. break;
  675. case 1:
  676. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  677. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  678. break;
  679. }
  680. for (nbank = 0; nbank < 2; nbank++) {
  681. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  682. bank->base = cpu_to_le32(runtime->dma_addr);
  683. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  684. bank->start = 0;
  685. bank->num_of_loops = 0;
  686. }
  687. return 0;
  688. }
  689. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  690. {
  691. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  692. struct snd_pcm_runtime *runtime = substream->runtime;
  693. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  694. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  695. if (!(ypcm->running && voice))
  696. return 0;
  697. return le32_to_cpu(voice->bank[chip->active_bank].start);
  698. }
  699. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  700. {
  701. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  702. struct snd_pcm_runtime *runtime = substream->runtime;
  703. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  704. if (!ypcm->running)
  705. return 0;
  706. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  707. }
  708. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  709. {
  710. wait_queue_entry_t wait;
  711. int loops = 4;
  712. while (loops-- > 0) {
  713. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  714. continue;
  715. init_waitqueue_entry(&wait, current);
  716. add_wait_queue(&chip->interrupt_sleep, &wait);
  717. atomic_inc(&chip->interrupt_sleep_count);
  718. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  719. remove_wait_queue(&chip->interrupt_sleep, &wait);
  720. }
  721. }
  722. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  723. {
  724. struct snd_ymfpci *chip = dev_id;
  725. u32 status, nvoice, mode;
  726. struct snd_ymfpci_voice *voice;
  727. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  728. if (status & 0x80000000) {
  729. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  730. spin_lock(&chip->voice_lock);
  731. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  732. voice = &chip->voices[nvoice];
  733. if (voice->interrupt)
  734. voice->interrupt(chip, voice);
  735. }
  736. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  737. if (chip->capture_substream[nvoice])
  738. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  739. }
  740. #if 0
  741. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  742. if (chip->effect_substream[nvoice])
  743. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  744. }
  745. #endif
  746. spin_unlock(&chip->voice_lock);
  747. spin_lock(&chip->reg_lock);
  748. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  749. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  750. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  751. spin_unlock(&chip->reg_lock);
  752. if (atomic_read(&chip->interrupt_sleep_count)) {
  753. atomic_set(&chip->interrupt_sleep_count, 0);
  754. wake_up(&chip->interrupt_sleep);
  755. }
  756. }
  757. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  758. if (status & 1) {
  759. if (chip->timer)
  760. snd_timer_interrupt(chip->timer, chip->timer_ticks);
  761. }
  762. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  763. if (chip->rawmidi)
  764. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  765. return IRQ_HANDLED;
  766. }
  767. static const struct snd_pcm_hardware snd_ymfpci_playback =
  768. {
  769. .info = (SNDRV_PCM_INFO_MMAP |
  770. SNDRV_PCM_INFO_MMAP_VALID |
  771. SNDRV_PCM_INFO_INTERLEAVED |
  772. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  773. SNDRV_PCM_INFO_PAUSE |
  774. SNDRV_PCM_INFO_RESUME),
  775. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  776. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  777. .rate_min = 8000,
  778. .rate_max = 48000,
  779. .channels_min = 1,
  780. .channels_max = 2,
  781. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  782. .period_bytes_min = 64,
  783. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  784. .periods_min = 3,
  785. .periods_max = 1024,
  786. .fifo_size = 0,
  787. };
  788. static const struct snd_pcm_hardware snd_ymfpci_capture =
  789. {
  790. .info = (SNDRV_PCM_INFO_MMAP |
  791. SNDRV_PCM_INFO_MMAP_VALID |
  792. SNDRV_PCM_INFO_INTERLEAVED |
  793. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  794. SNDRV_PCM_INFO_PAUSE |
  795. SNDRV_PCM_INFO_RESUME),
  796. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  797. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  798. .rate_min = 8000,
  799. .rate_max = 48000,
  800. .channels_min = 1,
  801. .channels_max = 2,
  802. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  803. .period_bytes_min = 64,
  804. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  805. .periods_min = 3,
  806. .periods_max = 1024,
  807. .fifo_size = 0,
  808. };
  809. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  810. {
  811. kfree(runtime->private_data);
  812. }
  813. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  814. {
  815. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  816. struct snd_pcm_runtime *runtime = substream->runtime;
  817. struct snd_ymfpci_pcm *ypcm;
  818. int err;
  819. runtime->hw = snd_ymfpci_playback;
  820. /* FIXME? True value is 256/48 = 5.33333 ms */
  821. err = snd_pcm_hw_constraint_minmax(runtime,
  822. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  823. 5334, UINT_MAX);
  824. if (err < 0)
  825. return err;
  826. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  827. if (err < 0)
  828. return err;
  829. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  830. if (ypcm == NULL)
  831. return -ENOMEM;
  832. ypcm->chip = chip;
  833. ypcm->type = PLAYBACK_VOICE;
  834. ypcm->substream = substream;
  835. runtime->private_data = ypcm;
  836. runtime->private_free = snd_ymfpci_pcm_free_substream;
  837. return 0;
  838. }
  839. /* call with spinlock held */
  840. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  841. {
  842. if (! chip->rear_opened) {
  843. if (! chip->spdif_opened) /* set AC3 */
  844. snd_ymfpci_writel(chip, YDSXGR_MODE,
  845. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  846. /* enable second codec (4CHEN) */
  847. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  848. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  849. }
  850. }
  851. /* call with spinlock held */
  852. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  853. {
  854. if (! chip->rear_opened) {
  855. if (! chip->spdif_opened)
  856. snd_ymfpci_writel(chip, YDSXGR_MODE,
  857. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  858. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  859. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  860. }
  861. }
  862. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  863. {
  864. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  865. struct snd_pcm_runtime *runtime = substream->runtime;
  866. struct snd_ymfpci_pcm *ypcm;
  867. int err;
  868. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  869. return err;
  870. ypcm = runtime->private_data;
  871. ypcm->output_front = 1;
  872. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  873. ypcm->swap_rear = 0;
  874. spin_lock_irq(&chip->reg_lock);
  875. if (ypcm->output_rear) {
  876. ymfpci_open_extension(chip);
  877. chip->rear_opened++;
  878. }
  879. spin_unlock_irq(&chip->reg_lock);
  880. return 0;
  881. }
  882. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  883. {
  884. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  885. struct snd_pcm_runtime *runtime = substream->runtime;
  886. struct snd_ymfpci_pcm *ypcm;
  887. int err;
  888. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  889. return err;
  890. ypcm = runtime->private_data;
  891. ypcm->output_front = 0;
  892. ypcm->output_rear = 1;
  893. ypcm->swap_rear = 1;
  894. spin_lock_irq(&chip->reg_lock);
  895. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  896. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  897. ymfpci_open_extension(chip);
  898. chip->spdif_pcm_bits = chip->spdif_bits;
  899. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  900. chip->spdif_opened++;
  901. spin_unlock_irq(&chip->reg_lock);
  902. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  903. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  904. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  905. return 0;
  906. }
  907. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  908. {
  909. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  910. struct snd_pcm_runtime *runtime = substream->runtime;
  911. struct snd_ymfpci_pcm *ypcm;
  912. int err;
  913. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  914. return err;
  915. ypcm = runtime->private_data;
  916. ypcm->output_front = 0;
  917. ypcm->output_rear = 1;
  918. ypcm->swap_rear = 0;
  919. spin_lock_irq(&chip->reg_lock);
  920. ymfpci_open_extension(chip);
  921. chip->rear_opened++;
  922. spin_unlock_irq(&chip->reg_lock);
  923. return 0;
  924. }
  925. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  926. u32 capture_bank_number)
  927. {
  928. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  929. struct snd_pcm_runtime *runtime = substream->runtime;
  930. struct snd_ymfpci_pcm *ypcm;
  931. int err;
  932. runtime->hw = snd_ymfpci_capture;
  933. /* FIXME? True value is 256/48 = 5.33333 ms */
  934. err = snd_pcm_hw_constraint_minmax(runtime,
  935. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  936. 5334, UINT_MAX);
  937. if (err < 0)
  938. return err;
  939. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  940. if (err < 0)
  941. return err;
  942. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  943. if (ypcm == NULL)
  944. return -ENOMEM;
  945. ypcm->chip = chip;
  946. ypcm->type = capture_bank_number + CAPTURE_REC;
  947. ypcm->substream = substream;
  948. ypcm->capture_bank_number = capture_bank_number;
  949. chip->capture_substream[capture_bank_number] = substream;
  950. runtime->private_data = ypcm;
  951. runtime->private_free = snd_ymfpci_pcm_free_substream;
  952. snd_ymfpci_hw_start(chip);
  953. return 0;
  954. }
  955. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  956. {
  957. return snd_ymfpci_capture_open(substream, 0);
  958. }
  959. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  960. {
  961. return snd_ymfpci_capture_open(substream, 1);
  962. }
  963. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  964. {
  965. return 0;
  966. }
  967. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  968. {
  969. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  970. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  971. spin_lock_irq(&chip->reg_lock);
  972. if (ypcm->output_rear && chip->rear_opened > 0) {
  973. chip->rear_opened--;
  974. ymfpci_close_extension(chip);
  975. }
  976. spin_unlock_irq(&chip->reg_lock);
  977. return snd_ymfpci_playback_close_1(substream);
  978. }
  979. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  980. {
  981. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  982. spin_lock_irq(&chip->reg_lock);
  983. chip->spdif_opened = 0;
  984. ymfpci_close_extension(chip);
  985. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  986. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  987. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  988. spin_unlock_irq(&chip->reg_lock);
  989. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  990. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  991. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  992. return snd_ymfpci_playback_close_1(substream);
  993. }
  994. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  995. {
  996. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  997. spin_lock_irq(&chip->reg_lock);
  998. if (chip->rear_opened > 0) {
  999. chip->rear_opened--;
  1000. ymfpci_close_extension(chip);
  1001. }
  1002. spin_unlock_irq(&chip->reg_lock);
  1003. return snd_ymfpci_playback_close_1(substream);
  1004. }
  1005. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  1006. {
  1007. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  1008. struct snd_pcm_runtime *runtime = substream->runtime;
  1009. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  1010. if (ypcm != NULL) {
  1011. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  1012. snd_ymfpci_hw_stop(chip);
  1013. }
  1014. return 0;
  1015. }
  1016. static const struct snd_pcm_ops snd_ymfpci_playback_ops = {
  1017. .open = snd_ymfpci_playback_open,
  1018. .close = snd_ymfpci_playback_close,
  1019. .ioctl = snd_pcm_lib_ioctl,
  1020. .hw_params = snd_ymfpci_playback_hw_params,
  1021. .hw_free = snd_ymfpci_playback_hw_free,
  1022. .prepare = snd_ymfpci_playback_prepare,
  1023. .trigger = snd_ymfpci_playback_trigger,
  1024. .pointer = snd_ymfpci_playback_pointer,
  1025. };
  1026. static const struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  1027. .open = snd_ymfpci_capture_rec_open,
  1028. .close = snd_ymfpci_capture_close,
  1029. .ioctl = snd_pcm_lib_ioctl,
  1030. .hw_params = snd_ymfpci_capture_hw_params,
  1031. .hw_free = snd_ymfpci_capture_hw_free,
  1032. .prepare = snd_ymfpci_capture_prepare,
  1033. .trigger = snd_ymfpci_capture_trigger,
  1034. .pointer = snd_ymfpci_capture_pointer,
  1035. };
  1036. int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device)
  1037. {
  1038. struct snd_pcm *pcm;
  1039. int err;
  1040. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  1041. return err;
  1042. pcm->private_data = chip;
  1043. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1044. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1045. /* global setup */
  1046. pcm->info_flags = 0;
  1047. strcpy(pcm->name, "YMFPCI");
  1048. chip->pcm = pcm;
  1049. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1050. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1051. return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1052. snd_pcm_std_chmaps, 2, 0, NULL);
  1053. }
  1054. static const struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1055. .open = snd_ymfpci_capture_ac97_open,
  1056. .close = snd_ymfpci_capture_close,
  1057. .ioctl = snd_pcm_lib_ioctl,
  1058. .hw_params = snd_ymfpci_capture_hw_params,
  1059. .hw_free = snd_ymfpci_capture_hw_free,
  1060. .prepare = snd_ymfpci_capture_prepare,
  1061. .trigger = snd_ymfpci_capture_trigger,
  1062. .pointer = snd_ymfpci_capture_pointer,
  1063. };
  1064. int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device)
  1065. {
  1066. struct snd_pcm *pcm;
  1067. int err;
  1068. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1069. return err;
  1070. pcm->private_data = chip;
  1071. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1072. /* global setup */
  1073. pcm->info_flags = 0;
  1074. sprintf(pcm->name, "YMFPCI - %s",
  1075. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1076. chip->pcm2 = pcm;
  1077. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1078. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1079. return 0;
  1080. }
  1081. static const struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1082. .open = snd_ymfpci_playback_spdif_open,
  1083. .close = snd_ymfpci_playback_spdif_close,
  1084. .ioctl = snd_pcm_lib_ioctl,
  1085. .hw_params = snd_ymfpci_playback_hw_params,
  1086. .hw_free = snd_ymfpci_playback_hw_free,
  1087. .prepare = snd_ymfpci_playback_prepare,
  1088. .trigger = snd_ymfpci_playback_trigger,
  1089. .pointer = snd_ymfpci_playback_pointer,
  1090. };
  1091. int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device)
  1092. {
  1093. struct snd_pcm *pcm;
  1094. int err;
  1095. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1096. return err;
  1097. pcm->private_data = chip;
  1098. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1099. /* global setup */
  1100. pcm->info_flags = 0;
  1101. strcpy(pcm->name, "YMFPCI - IEC958");
  1102. chip->pcm_spdif = pcm;
  1103. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1104. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1105. return 0;
  1106. }
  1107. static const struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1108. .open = snd_ymfpci_playback_4ch_open,
  1109. .close = snd_ymfpci_playback_4ch_close,
  1110. .ioctl = snd_pcm_lib_ioctl,
  1111. .hw_params = snd_ymfpci_playback_hw_params,
  1112. .hw_free = snd_ymfpci_playback_hw_free,
  1113. .prepare = snd_ymfpci_playback_prepare,
  1114. .trigger = snd_ymfpci_playback_trigger,
  1115. .pointer = snd_ymfpci_playback_pointer,
  1116. };
  1117. static const struct snd_pcm_chmap_elem surround_map[] = {
  1118. { .channels = 1,
  1119. .map = { SNDRV_CHMAP_MONO } },
  1120. { .channels = 2,
  1121. .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
  1122. { }
  1123. };
  1124. int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device)
  1125. {
  1126. struct snd_pcm *pcm;
  1127. int err;
  1128. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1129. return err;
  1130. pcm->private_data = chip;
  1131. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1132. /* global setup */
  1133. pcm->info_flags = 0;
  1134. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1135. chip->pcm_4ch = pcm;
  1136. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1137. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1138. return snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1139. surround_map, 2, 0, NULL);
  1140. }
  1141. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1142. {
  1143. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1144. uinfo->count = 1;
  1145. return 0;
  1146. }
  1147. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1148. struct snd_ctl_elem_value *ucontrol)
  1149. {
  1150. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1151. spin_lock_irq(&chip->reg_lock);
  1152. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1153. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1154. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1155. spin_unlock_irq(&chip->reg_lock);
  1156. return 0;
  1157. }
  1158. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1159. struct snd_ctl_elem_value *ucontrol)
  1160. {
  1161. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1162. unsigned int val;
  1163. int change;
  1164. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1165. (ucontrol->value.iec958.status[1] << 8);
  1166. spin_lock_irq(&chip->reg_lock);
  1167. change = chip->spdif_bits != val;
  1168. chip->spdif_bits = val;
  1169. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1170. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1171. spin_unlock_irq(&chip->reg_lock);
  1172. return change;
  1173. }
  1174. static const struct snd_kcontrol_new snd_ymfpci_spdif_default =
  1175. {
  1176. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1177. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1178. .info = snd_ymfpci_spdif_default_info,
  1179. .get = snd_ymfpci_spdif_default_get,
  1180. .put = snd_ymfpci_spdif_default_put
  1181. };
  1182. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1183. {
  1184. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1185. uinfo->count = 1;
  1186. return 0;
  1187. }
  1188. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1189. struct snd_ctl_elem_value *ucontrol)
  1190. {
  1191. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1192. spin_lock_irq(&chip->reg_lock);
  1193. ucontrol->value.iec958.status[0] = 0x3e;
  1194. ucontrol->value.iec958.status[1] = 0xff;
  1195. spin_unlock_irq(&chip->reg_lock);
  1196. return 0;
  1197. }
  1198. static const struct snd_kcontrol_new snd_ymfpci_spdif_mask =
  1199. {
  1200. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1201. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1202. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1203. .info = snd_ymfpci_spdif_mask_info,
  1204. .get = snd_ymfpci_spdif_mask_get,
  1205. };
  1206. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1207. {
  1208. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1209. uinfo->count = 1;
  1210. return 0;
  1211. }
  1212. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1213. struct snd_ctl_elem_value *ucontrol)
  1214. {
  1215. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1216. spin_lock_irq(&chip->reg_lock);
  1217. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1218. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1219. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1220. spin_unlock_irq(&chip->reg_lock);
  1221. return 0;
  1222. }
  1223. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1224. struct snd_ctl_elem_value *ucontrol)
  1225. {
  1226. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1227. unsigned int val;
  1228. int change;
  1229. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1230. (ucontrol->value.iec958.status[1] << 8);
  1231. spin_lock_irq(&chip->reg_lock);
  1232. change = chip->spdif_pcm_bits != val;
  1233. chip->spdif_pcm_bits = val;
  1234. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1235. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1236. spin_unlock_irq(&chip->reg_lock);
  1237. return change;
  1238. }
  1239. static const struct snd_kcontrol_new snd_ymfpci_spdif_stream =
  1240. {
  1241. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1242. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1243. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1244. .info = snd_ymfpci_spdif_stream_info,
  1245. .get = snd_ymfpci_spdif_stream_get,
  1246. .put = snd_ymfpci_spdif_stream_put
  1247. };
  1248. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1249. {
  1250. static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1251. return snd_ctl_enum_info(info, 1, 3, texts);
  1252. }
  1253. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1254. {
  1255. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1256. u16 reg;
  1257. spin_lock_irq(&chip->reg_lock);
  1258. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1259. spin_unlock_irq(&chip->reg_lock);
  1260. if (!(reg & 0x100))
  1261. value->value.enumerated.item[0] = 0;
  1262. else
  1263. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1264. return 0;
  1265. }
  1266. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1267. {
  1268. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1269. u16 reg, old_reg;
  1270. spin_lock_irq(&chip->reg_lock);
  1271. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1272. if (value->value.enumerated.item[0] == 0)
  1273. reg = old_reg & ~0x100;
  1274. else
  1275. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1276. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1277. spin_unlock_irq(&chip->reg_lock);
  1278. return reg != old_reg;
  1279. }
  1280. static const struct snd_kcontrol_new snd_ymfpci_drec_source = {
  1281. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1282. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1283. .name = "Direct Recording Source",
  1284. .info = snd_ymfpci_drec_source_info,
  1285. .get = snd_ymfpci_drec_source_get,
  1286. .put = snd_ymfpci_drec_source_put
  1287. };
  1288. /*
  1289. * Mixer controls
  1290. */
  1291. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1292. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1293. .info = snd_ymfpci_info_single, \
  1294. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1295. .private_value = ((reg) | ((shift) << 16)) }
  1296. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1297. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1298. struct snd_ctl_elem_value *ucontrol)
  1299. {
  1300. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1301. int reg = kcontrol->private_value & 0xffff;
  1302. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1303. unsigned int mask = 1;
  1304. switch (reg) {
  1305. case YDSXGR_SPDIFOUTCTRL: break;
  1306. case YDSXGR_SPDIFINCTRL: break;
  1307. default: return -EINVAL;
  1308. }
  1309. ucontrol->value.integer.value[0] =
  1310. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1311. return 0;
  1312. }
  1313. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1314. struct snd_ctl_elem_value *ucontrol)
  1315. {
  1316. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1317. int reg = kcontrol->private_value & 0xffff;
  1318. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1319. unsigned int mask = 1;
  1320. int change;
  1321. unsigned int val, oval;
  1322. switch (reg) {
  1323. case YDSXGR_SPDIFOUTCTRL: break;
  1324. case YDSXGR_SPDIFINCTRL: break;
  1325. default: return -EINVAL;
  1326. }
  1327. val = (ucontrol->value.integer.value[0] & mask);
  1328. val <<= shift;
  1329. spin_lock_irq(&chip->reg_lock);
  1330. oval = snd_ymfpci_readl(chip, reg);
  1331. val = (oval & ~(mask << shift)) | val;
  1332. change = val != oval;
  1333. snd_ymfpci_writel(chip, reg, val);
  1334. spin_unlock_irq(&chip->reg_lock);
  1335. return change;
  1336. }
  1337. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1338. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1339. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1340. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1341. .info = snd_ymfpci_info_double, \
  1342. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1343. .private_value = reg, \
  1344. .tlv = { .p = db_scale_native } }
  1345. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1346. {
  1347. unsigned int reg = kcontrol->private_value;
  1348. if (reg < 0x80 || reg >= 0xc0)
  1349. return -EINVAL;
  1350. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1351. uinfo->count = 2;
  1352. uinfo->value.integer.min = 0;
  1353. uinfo->value.integer.max = 16383;
  1354. return 0;
  1355. }
  1356. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1357. {
  1358. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1359. unsigned int reg = kcontrol->private_value;
  1360. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1361. unsigned int val;
  1362. if (reg < 0x80 || reg >= 0xc0)
  1363. return -EINVAL;
  1364. spin_lock_irq(&chip->reg_lock);
  1365. val = snd_ymfpci_readl(chip, reg);
  1366. spin_unlock_irq(&chip->reg_lock);
  1367. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1368. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1369. return 0;
  1370. }
  1371. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1372. {
  1373. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1374. unsigned int reg = kcontrol->private_value;
  1375. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1376. int change;
  1377. unsigned int val1, val2, oval;
  1378. if (reg < 0x80 || reg >= 0xc0)
  1379. return -EINVAL;
  1380. val1 = ucontrol->value.integer.value[0] & mask;
  1381. val2 = ucontrol->value.integer.value[1] & mask;
  1382. val1 <<= shift_left;
  1383. val2 <<= shift_right;
  1384. spin_lock_irq(&chip->reg_lock);
  1385. oval = snd_ymfpci_readl(chip, reg);
  1386. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1387. change = val1 != oval;
  1388. snd_ymfpci_writel(chip, reg, val1);
  1389. spin_unlock_irq(&chip->reg_lock);
  1390. return change;
  1391. }
  1392. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1393. struct snd_ctl_elem_value *ucontrol)
  1394. {
  1395. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1396. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1397. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1398. int change;
  1399. unsigned int value, oval;
  1400. value = ucontrol->value.integer.value[0] & 0x3fff;
  1401. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1402. spin_lock_irq(&chip->reg_lock);
  1403. oval = snd_ymfpci_readl(chip, reg);
  1404. change = value != oval;
  1405. snd_ymfpci_writel(chip, reg, value);
  1406. snd_ymfpci_writel(chip, reg2, value);
  1407. spin_unlock_irq(&chip->reg_lock);
  1408. return change;
  1409. }
  1410. /*
  1411. * 4ch duplication
  1412. */
  1413. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1414. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1415. {
  1416. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1417. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1418. return 0;
  1419. }
  1420. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1421. {
  1422. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1423. int change;
  1424. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1425. if (change)
  1426. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1427. return change;
  1428. }
  1429. static const struct snd_kcontrol_new snd_ymfpci_dup4ch = {
  1430. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1431. .name = "4ch Duplication",
  1432. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1433. .info = snd_ymfpci_info_dup4ch,
  1434. .get = snd_ymfpci_get_dup4ch,
  1435. .put = snd_ymfpci_put_dup4ch,
  1436. };
  1437. static struct snd_kcontrol_new snd_ymfpci_controls[] = {
  1438. {
  1439. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1440. .name = "Wave Playback Volume",
  1441. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1442. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1443. .info = snd_ymfpci_info_double,
  1444. .get = snd_ymfpci_get_double,
  1445. .put = snd_ymfpci_put_nativedacvol,
  1446. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1447. .tlv = { .p = db_scale_native },
  1448. },
  1449. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1450. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1451. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1452. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1453. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1454. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1455. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1456. YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
  1457. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1458. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1459. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1460. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1461. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1462. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1463. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1464. };
  1465. /*
  1466. * GPIO
  1467. */
  1468. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1469. {
  1470. u16 reg, mode;
  1471. unsigned long flags;
  1472. spin_lock_irqsave(&chip->reg_lock, flags);
  1473. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1474. reg &= ~(1 << (pin + 8));
  1475. reg |= (1 << pin);
  1476. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1477. /* set the level mode for input line */
  1478. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1479. mode &= ~(3 << (pin * 2));
  1480. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1481. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1482. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1483. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1484. return (mode >> pin) & 1;
  1485. }
  1486. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1487. {
  1488. u16 reg;
  1489. unsigned long flags;
  1490. spin_lock_irqsave(&chip->reg_lock, flags);
  1491. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1492. reg &= ~(1 << pin);
  1493. reg &= ~(1 << (pin + 8));
  1494. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1495. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1496. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1497. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1498. return 0;
  1499. }
  1500. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1501. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1502. {
  1503. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1504. int pin = (int)kcontrol->private_value;
  1505. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1506. return 0;
  1507. }
  1508. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1509. {
  1510. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1511. int pin = (int)kcontrol->private_value;
  1512. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1513. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1514. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1515. return 1;
  1516. }
  1517. return 0;
  1518. }
  1519. static const struct snd_kcontrol_new snd_ymfpci_rear_shared = {
  1520. .name = "Shared Rear/Line-In Switch",
  1521. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1522. .info = snd_ymfpci_gpio_sw_info,
  1523. .get = snd_ymfpci_gpio_sw_get,
  1524. .put = snd_ymfpci_gpio_sw_put,
  1525. .private_value = 2,
  1526. };
  1527. /*
  1528. * PCM voice volume
  1529. */
  1530. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1531. struct snd_ctl_elem_info *uinfo)
  1532. {
  1533. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1534. uinfo->count = 2;
  1535. uinfo->value.integer.min = 0;
  1536. uinfo->value.integer.max = 0x8000;
  1537. return 0;
  1538. }
  1539. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1540. struct snd_ctl_elem_value *ucontrol)
  1541. {
  1542. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1543. unsigned int subs = kcontrol->id.subdevice;
  1544. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1545. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1546. return 0;
  1547. }
  1548. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1549. struct snd_ctl_elem_value *ucontrol)
  1550. {
  1551. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1552. unsigned int subs = kcontrol->id.subdevice;
  1553. struct snd_pcm_substream *substream;
  1554. unsigned long flags;
  1555. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1556. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1557. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1558. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1559. if (chip->pcm_mixer[subs].left > 0x8000)
  1560. chip->pcm_mixer[subs].left = 0x8000;
  1561. if (chip->pcm_mixer[subs].right > 0x8000)
  1562. chip->pcm_mixer[subs].right = 0x8000;
  1563. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1564. spin_lock_irqsave(&chip->voice_lock, flags);
  1565. if (substream->runtime && substream->runtime->private_data) {
  1566. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1567. if (!ypcm->use_441_slot)
  1568. ypcm->update_pcm_vol = 2;
  1569. }
  1570. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1571. return 1;
  1572. }
  1573. return 0;
  1574. }
  1575. static const struct snd_kcontrol_new snd_ymfpci_pcm_volume = {
  1576. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1577. .name = "PCM Playback Volume",
  1578. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1579. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1580. .info = snd_ymfpci_pcm_vol_info,
  1581. .get = snd_ymfpci_pcm_vol_get,
  1582. .put = snd_ymfpci_pcm_vol_put,
  1583. };
  1584. /*
  1585. * Mixer routines
  1586. */
  1587. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1588. {
  1589. struct snd_ymfpci *chip = bus->private_data;
  1590. chip->ac97_bus = NULL;
  1591. }
  1592. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1593. {
  1594. struct snd_ymfpci *chip = ac97->private_data;
  1595. chip->ac97 = NULL;
  1596. }
  1597. int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1598. {
  1599. struct snd_ac97_template ac97;
  1600. struct snd_kcontrol *kctl;
  1601. struct snd_pcm_substream *substream;
  1602. unsigned int idx;
  1603. int err;
  1604. static struct snd_ac97_bus_ops ops = {
  1605. .write = snd_ymfpci_codec_write,
  1606. .read = snd_ymfpci_codec_read,
  1607. };
  1608. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1609. return err;
  1610. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1611. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1612. memset(&ac97, 0, sizeof(ac97));
  1613. ac97.private_data = chip;
  1614. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1615. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1616. return err;
  1617. /* to be sure */
  1618. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1619. AC97_EA_VRA|AC97_EA_VRM, 0);
  1620. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1621. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1622. return err;
  1623. }
  1624. if (chip->ac97->ext_id & AC97_EI_SDAC) {
  1625. kctl = snd_ctl_new1(&snd_ymfpci_dup4ch, chip);
  1626. err = snd_ctl_add(chip->card, kctl);
  1627. if (err < 0)
  1628. return err;
  1629. }
  1630. /* add S/PDIF control */
  1631. if (snd_BUG_ON(!chip->pcm_spdif))
  1632. return -ENXIO;
  1633. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1634. return err;
  1635. kctl->id.device = chip->pcm_spdif->device;
  1636. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1637. return err;
  1638. kctl->id.device = chip->pcm_spdif->device;
  1639. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1640. return err;
  1641. kctl->id.device = chip->pcm_spdif->device;
  1642. chip->spdif_pcm_ctl = kctl;
  1643. /* direct recording source */
  1644. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1645. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1646. return err;
  1647. /*
  1648. * shared rear/line-in
  1649. */
  1650. if (rear_switch) {
  1651. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1652. return err;
  1653. }
  1654. /* per-voice volume */
  1655. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1656. for (idx = 0; idx < 32; ++idx) {
  1657. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1658. if (!kctl)
  1659. return -ENOMEM;
  1660. kctl->id.device = chip->pcm->device;
  1661. kctl->id.subdevice = idx;
  1662. kctl->private_value = (unsigned long)substream;
  1663. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1664. return err;
  1665. chip->pcm_mixer[idx].left = 0x8000;
  1666. chip->pcm_mixer[idx].right = 0x8000;
  1667. chip->pcm_mixer[idx].ctl = kctl;
  1668. substream = substream->next;
  1669. }
  1670. return 0;
  1671. }
  1672. /*
  1673. * timer
  1674. */
  1675. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1676. {
  1677. struct snd_ymfpci *chip;
  1678. unsigned long flags;
  1679. unsigned int count;
  1680. chip = snd_timer_chip(timer);
  1681. spin_lock_irqsave(&chip->reg_lock, flags);
  1682. if (timer->sticks > 1) {
  1683. chip->timer_ticks = timer->sticks;
  1684. count = timer->sticks - 1;
  1685. } else {
  1686. /*
  1687. * Divisor 1 is not allowed; fake it by using divisor 2 and
  1688. * counting two ticks for each interrupt.
  1689. */
  1690. chip->timer_ticks = 2;
  1691. count = 2 - 1;
  1692. }
  1693. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1694. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1695. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1696. return 0;
  1697. }
  1698. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1699. {
  1700. struct snd_ymfpci *chip;
  1701. unsigned long flags;
  1702. chip = snd_timer_chip(timer);
  1703. spin_lock_irqsave(&chip->reg_lock, flags);
  1704. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1705. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1706. return 0;
  1707. }
  1708. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1709. unsigned long *num, unsigned long *den)
  1710. {
  1711. *num = 1;
  1712. *den = 96000;
  1713. return 0;
  1714. }
  1715. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1716. .flags = SNDRV_TIMER_HW_AUTO,
  1717. .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
  1718. .ticks = 0x10000,
  1719. .start = snd_ymfpci_timer_start,
  1720. .stop = snd_ymfpci_timer_stop,
  1721. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1722. };
  1723. int snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1724. {
  1725. struct snd_timer *timer = NULL;
  1726. struct snd_timer_id tid;
  1727. int err;
  1728. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1729. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1730. tid.card = chip->card->number;
  1731. tid.device = device;
  1732. tid.subdevice = 0;
  1733. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1734. strcpy(timer->name, "YMFPCI timer");
  1735. timer->private_data = chip;
  1736. timer->hw = snd_ymfpci_timer_hw;
  1737. }
  1738. chip->timer = timer;
  1739. return err;
  1740. }
  1741. /*
  1742. * proc interface
  1743. */
  1744. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1745. struct snd_info_buffer *buffer)
  1746. {
  1747. struct snd_ymfpci *chip = entry->private_data;
  1748. int i;
  1749. snd_iprintf(buffer, "YMFPCI\n\n");
  1750. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1751. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1752. }
  1753. static int snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1754. {
  1755. struct snd_info_entry *entry;
  1756. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1757. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1758. return 0;
  1759. }
  1760. /*
  1761. * initialization routines
  1762. */
  1763. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1764. {
  1765. u8 cmd;
  1766. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1767. #if 0 // force to reset
  1768. if (cmd & 0x03) {
  1769. #endif
  1770. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1771. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1772. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1773. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1774. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1775. #if 0
  1776. }
  1777. #endif
  1778. }
  1779. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1780. {
  1781. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1782. }
  1783. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1784. {
  1785. u32 val;
  1786. int timeout = 1000;
  1787. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1788. if (val)
  1789. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1790. while (timeout-- > 0) {
  1791. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1792. if ((val & 0x00000002) == 0)
  1793. break;
  1794. }
  1795. }
  1796. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1797. {
  1798. int err, is_1e;
  1799. const char *name;
  1800. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1801. &chip->pci->dev);
  1802. if (err >= 0) {
  1803. if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
  1804. dev_err(chip->card->dev,
  1805. "DSP microcode has wrong size\n");
  1806. err = -EINVAL;
  1807. }
  1808. }
  1809. if (err < 0)
  1810. return err;
  1811. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1812. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1813. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1814. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1815. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1816. err = request_firmware(&chip->controller_microcode, name,
  1817. &chip->pci->dev);
  1818. if (err >= 0) {
  1819. if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
  1820. dev_err(chip->card->dev,
  1821. "controller microcode has wrong size\n");
  1822. err = -EINVAL;
  1823. }
  1824. }
  1825. if (err < 0)
  1826. return err;
  1827. return 0;
  1828. }
  1829. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1830. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1831. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1832. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1833. {
  1834. int i;
  1835. u16 ctrl;
  1836. const __le32 *inst;
  1837. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1838. snd_ymfpci_disable_dsp(chip);
  1839. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1840. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1841. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1842. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1843. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1844. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1845. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1846. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1847. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1848. /* setup DSP instruction code */
  1849. inst = (const __le32 *)chip->dsp_microcode->data;
  1850. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1851. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
  1852. le32_to_cpu(inst[i]));
  1853. /* setup control instruction code */
  1854. inst = (const __le32 *)chip->controller_microcode->data;
  1855. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1856. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
  1857. le32_to_cpu(inst[i]));
  1858. snd_ymfpci_enable_dsp(chip);
  1859. }
  1860. static int snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1861. {
  1862. long size, playback_ctrl_size;
  1863. int voice, bank, reg;
  1864. u8 *ptr;
  1865. dma_addr_t ptr_addr;
  1866. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1867. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1868. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1869. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1870. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1871. size = ALIGN(playback_ctrl_size, 0x100) +
  1872. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1873. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1874. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1875. chip->work_size;
  1876. /* work_ptr must be aligned to 256 bytes, but it's already
  1877. covered with the kernel page allocation mechanism */
  1878. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1879. size, &chip->work_ptr) < 0)
  1880. return -ENOMEM;
  1881. ptr = chip->work_ptr.area;
  1882. ptr_addr = chip->work_ptr.addr;
  1883. memset(ptr, 0, size); /* for sure */
  1884. chip->bank_base_playback = ptr;
  1885. chip->bank_base_playback_addr = ptr_addr;
  1886. chip->ctrl_playback = (u32 *)ptr;
  1887. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1888. ptr += ALIGN(playback_ctrl_size, 0x100);
  1889. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1890. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1891. chip->voices[voice].number = voice;
  1892. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1893. chip->voices[voice].bank_addr = ptr_addr;
  1894. for (bank = 0; bank < 2; bank++) {
  1895. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1896. ptr += chip->bank_size_playback;
  1897. ptr_addr += chip->bank_size_playback;
  1898. }
  1899. }
  1900. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1901. ptr_addr = ALIGN(ptr_addr, 0x100);
  1902. chip->bank_base_capture = ptr;
  1903. chip->bank_base_capture_addr = ptr_addr;
  1904. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1905. for (bank = 0; bank < 2; bank++) {
  1906. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1907. ptr += chip->bank_size_capture;
  1908. ptr_addr += chip->bank_size_capture;
  1909. }
  1910. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1911. ptr_addr = ALIGN(ptr_addr, 0x100);
  1912. chip->bank_base_effect = ptr;
  1913. chip->bank_base_effect_addr = ptr_addr;
  1914. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1915. for (bank = 0; bank < 2; bank++) {
  1916. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1917. ptr += chip->bank_size_effect;
  1918. ptr_addr += chip->bank_size_effect;
  1919. }
  1920. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1921. ptr_addr = ALIGN(ptr_addr, 0x100);
  1922. chip->work_base = ptr;
  1923. chip->work_base_addr = ptr_addr;
  1924. snd_BUG_ON(ptr + chip->work_size !=
  1925. chip->work_ptr.area + chip->work_ptr.bytes);
  1926. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1927. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1928. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1929. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1930. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1931. /* S/PDIF output initialization */
  1932. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1933. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1934. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1935. /* S/PDIF input initialization */
  1936. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1937. /* digital mixer setup */
  1938. for (reg = 0x80; reg < 0xc0; reg += 4)
  1939. snd_ymfpci_writel(chip, reg, 0);
  1940. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1941. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1942. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1943. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1944. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1945. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1946. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1947. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1948. return 0;
  1949. }
  1950. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1951. {
  1952. u16 ctrl;
  1953. if (snd_BUG_ON(!chip))
  1954. return -EINVAL;
  1955. if (chip->res_reg_area) { /* don't touch busy hardware */
  1956. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1957. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1958. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1959. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1960. snd_ymfpci_disable_dsp(chip);
  1961. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1962. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1963. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1964. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1965. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1966. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1967. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1968. }
  1969. snd_ymfpci_ac3_done(chip);
  1970. /* Set PCI device to D3 state */
  1971. #if 0
  1972. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1973. * the chip again unless reboot. ACPI bug?
  1974. */
  1975. pci_set_power_state(chip->pci, PCI_D3hot);
  1976. #endif
  1977. #ifdef CONFIG_PM_SLEEP
  1978. kfree(chip->saved_regs);
  1979. #endif
  1980. if (chip->irq >= 0)
  1981. free_irq(chip->irq, chip);
  1982. release_and_free_resource(chip->mpu_res);
  1983. release_and_free_resource(chip->fm_res);
  1984. snd_ymfpci_free_gameport(chip);
  1985. iounmap(chip->reg_area_virt);
  1986. if (chip->work_ptr.area)
  1987. snd_dma_free_pages(&chip->work_ptr);
  1988. release_and_free_resource(chip->res_reg_area);
  1989. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1990. pci_disable_device(chip->pci);
  1991. release_firmware(chip->dsp_microcode);
  1992. release_firmware(chip->controller_microcode);
  1993. kfree(chip);
  1994. return 0;
  1995. }
  1996. static int snd_ymfpci_dev_free(struct snd_device *device)
  1997. {
  1998. struct snd_ymfpci *chip = device->device_data;
  1999. return snd_ymfpci_free(chip);
  2000. }
  2001. #ifdef CONFIG_PM_SLEEP
  2002. static int saved_regs_index[] = {
  2003. /* spdif */
  2004. YDSXGR_SPDIFOUTCTRL,
  2005. YDSXGR_SPDIFOUTSTATUS,
  2006. YDSXGR_SPDIFINCTRL,
  2007. /* volumes */
  2008. YDSXGR_PRIADCLOOPVOL,
  2009. YDSXGR_NATIVEDACINVOL,
  2010. YDSXGR_NATIVEDACOUTVOL,
  2011. YDSXGR_BUF441OUTVOL,
  2012. YDSXGR_NATIVEADCINVOL,
  2013. YDSXGR_SPDIFLOOPVOL,
  2014. YDSXGR_SPDIFOUTVOL,
  2015. YDSXGR_ZVOUTVOL,
  2016. YDSXGR_LEGACYOUTVOL,
  2017. /* address bases */
  2018. YDSXGR_PLAYCTRLBASE,
  2019. YDSXGR_RECCTRLBASE,
  2020. YDSXGR_EFFCTRLBASE,
  2021. YDSXGR_WORKBASE,
  2022. /* capture set up */
  2023. YDSXGR_MAPOFREC,
  2024. YDSXGR_RECFORMAT,
  2025. YDSXGR_RECSLOTSR,
  2026. YDSXGR_ADCFORMAT,
  2027. YDSXGR_ADCSLOTSR,
  2028. };
  2029. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  2030. static int snd_ymfpci_suspend(struct device *dev)
  2031. {
  2032. struct snd_card *card = dev_get_drvdata(dev);
  2033. struct snd_ymfpci *chip = card->private_data;
  2034. unsigned int i;
  2035. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2036. snd_pcm_suspend_all(chip->pcm);
  2037. snd_pcm_suspend_all(chip->pcm2);
  2038. snd_pcm_suspend_all(chip->pcm_spdif);
  2039. snd_pcm_suspend_all(chip->pcm_4ch);
  2040. snd_ac97_suspend(chip->ac97);
  2041. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2042. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2043. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2044. pci_read_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2045. &chip->saved_dsxg_legacy);
  2046. pci_read_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2047. &chip->saved_dsxg_elegacy);
  2048. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2049. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2050. snd_ymfpci_disable_dsp(chip);
  2051. return 0;
  2052. }
  2053. static int snd_ymfpci_resume(struct device *dev)
  2054. {
  2055. struct pci_dev *pci = to_pci_dev(dev);
  2056. struct snd_card *card = dev_get_drvdata(dev);
  2057. struct snd_ymfpci *chip = card->private_data;
  2058. unsigned int i;
  2059. snd_ymfpci_aclink_reset(pci);
  2060. snd_ymfpci_codec_ready(chip, 0);
  2061. snd_ymfpci_download_image(chip);
  2062. udelay(100);
  2063. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2064. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2065. snd_ac97_resume(chip->ac97);
  2066. pci_write_config_word(chip->pci, PCIR_DSXG_LEGACY,
  2067. chip->saved_dsxg_legacy);
  2068. pci_write_config_word(chip->pci, PCIR_DSXG_ELEGACY,
  2069. chip->saved_dsxg_elegacy);
  2070. /* start hw again */
  2071. if (chip->start_count > 0) {
  2072. spin_lock_irq(&chip->reg_lock);
  2073. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2074. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2075. spin_unlock_irq(&chip->reg_lock);
  2076. }
  2077. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2078. return 0;
  2079. }
  2080. SIMPLE_DEV_PM_OPS(snd_ymfpci_pm, snd_ymfpci_suspend, snd_ymfpci_resume);
  2081. #endif /* CONFIG_PM_SLEEP */
  2082. int snd_ymfpci_create(struct snd_card *card,
  2083. struct pci_dev *pci,
  2084. unsigned short old_legacy_ctrl,
  2085. struct snd_ymfpci **rchip)
  2086. {
  2087. struct snd_ymfpci *chip;
  2088. int err;
  2089. static struct snd_device_ops ops = {
  2090. .dev_free = snd_ymfpci_dev_free,
  2091. };
  2092. *rchip = NULL;
  2093. /* enable PCI device */
  2094. if ((err = pci_enable_device(pci)) < 0)
  2095. return err;
  2096. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2097. if (chip == NULL) {
  2098. pci_disable_device(pci);
  2099. return -ENOMEM;
  2100. }
  2101. chip->old_legacy_ctrl = old_legacy_ctrl;
  2102. spin_lock_init(&chip->reg_lock);
  2103. spin_lock_init(&chip->voice_lock);
  2104. init_waitqueue_head(&chip->interrupt_sleep);
  2105. atomic_set(&chip->interrupt_sleep_count, 0);
  2106. chip->card = card;
  2107. chip->pci = pci;
  2108. chip->irq = -1;
  2109. chip->device_id = pci->device;
  2110. chip->rev = pci->revision;
  2111. chip->reg_area_phys = pci_resource_start(pci, 0);
  2112. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2113. pci_set_master(pci);
  2114. chip->src441_used = -1;
  2115. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2116. dev_err(chip->card->dev,
  2117. "unable to grab memory region 0x%lx-0x%lx\n",
  2118. chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2119. err = -EBUSY;
  2120. goto free_chip;
  2121. }
  2122. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2123. KBUILD_MODNAME, chip)) {
  2124. dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
  2125. err = -EBUSY;
  2126. goto free_chip;
  2127. }
  2128. chip->irq = pci->irq;
  2129. snd_ymfpci_aclink_reset(pci);
  2130. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2131. err = -EIO;
  2132. goto free_chip;
  2133. }
  2134. err = snd_ymfpci_request_firmware(chip);
  2135. if (err < 0) {
  2136. dev_err(chip->card->dev, "firmware request failed: %d\n", err);
  2137. goto free_chip;
  2138. }
  2139. snd_ymfpci_download_image(chip);
  2140. udelay(100); /* seems we need a delay after downloading image.. */
  2141. if (snd_ymfpci_memalloc(chip) < 0) {
  2142. err = -EIO;
  2143. goto free_chip;
  2144. }
  2145. err = snd_ymfpci_ac3_init(chip);
  2146. if (err < 0)
  2147. goto free_chip;
  2148. #ifdef CONFIG_PM_SLEEP
  2149. chip->saved_regs = kmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32),
  2150. GFP_KERNEL);
  2151. if (chip->saved_regs == NULL) {
  2152. err = -ENOMEM;
  2153. goto free_chip;
  2154. }
  2155. #endif
  2156. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  2157. if (err < 0)
  2158. goto free_chip;
  2159. snd_ymfpci_proc_init(card, chip);
  2160. *rchip = chip;
  2161. return 0;
  2162. free_chip:
  2163. snd_ymfpci_free(chip);
  2164. return err;
  2165. }