ice1724.c 79 KB

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  1. /*
  2. * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
  3. * VIA VT1720 (Envy24PT)
  4. *
  5. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  6. * 2002 James Stafford <jstafford@ampltd.com>
  7. * 2003 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/delay.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/init.h>
  27. #include <linux/pci.h>
  28. #include <linux/slab.h>
  29. #include <linux/module.h>
  30. #include <linux/mutex.h>
  31. #include <sound/core.h>
  32. #include <sound/info.h>
  33. #include <sound/rawmidi.h>
  34. #include <sound/initval.h>
  35. #include <sound/asoundef.h>
  36. #include "ice1712.h"
  37. #include "envy24ht.h"
  38. /* lowlevel routines */
  39. #include "amp.h"
  40. #include "revo.h"
  41. #include "aureon.h"
  42. #include "vt1720_mobo.h"
  43. #include "pontis.h"
  44. #include "prodigy192.h"
  45. #include "prodigy_hifi.h"
  46. #include "juli.h"
  47. #include "maya44.h"
  48. #include "phase.h"
  49. #include "wtm.h"
  50. #include "se.h"
  51. #include "quartet.h"
  52. #include "psc724.h"
  53. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  54. MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
  55. MODULE_LICENSE("GPL");
  56. MODULE_SUPPORTED_DEVICE("{"
  57. REVO_DEVICE_DESC
  58. AMP_AUDIO2000_DEVICE_DESC
  59. AUREON_DEVICE_DESC
  60. VT1720_MOBO_DEVICE_DESC
  61. PONTIS_DEVICE_DESC
  62. PRODIGY192_DEVICE_DESC
  63. PRODIGY_HIFI_DEVICE_DESC
  64. JULI_DEVICE_DESC
  65. MAYA44_DEVICE_DESC
  66. PHASE_DEVICE_DESC
  67. WTM_DEVICE_DESC
  68. SE_DEVICE_DESC
  69. QTET_DEVICE_DESC
  70. "{VIA,VT1720},"
  71. "{VIA,VT1724},"
  72. "{ICEnsemble,Generic ICE1724},"
  73. "{ICEnsemble,Generic Envy24HT}"
  74. "{ICEnsemble,Generic Envy24PT}}");
  75. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  76. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  77. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  78. static char *model[SNDRV_CARDS];
  79. module_param_array(index, int, NULL, 0444);
  80. MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
  81. module_param_array(id, charp, NULL, 0444);
  82. MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
  83. module_param_array(enable, bool, NULL, 0444);
  84. MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
  85. module_param_array(model, charp, NULL, 0444);
  86. MODULE_PARM_DESC(model, "Use the given board model.");
  87. /* Both VT1720 and VT1724 have the same PCI IDs */
  88. static const struct pci_device_id snd_vt1724_ids[] = {
  89. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
  90. { 0, }
  91. };
  92. MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
  93. static int PRO_RATE_LOCKED;
  94. static int PRO_RATE_RESET = 1;
  95. static unsigned int PRO_RATE_DEFAULT = 44100;
  96. static const char * const ext_clock_names[1] = { "IEC958 In" };
  97. /*
  98. * Basic I/O
  99. */
  100. /*
  101. * default rates, default clock routines
  102. */
  103. /* check whether the clock mode is spdif-in */
  104. static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
  105. {
  106. return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
  107. }
  108. /*
  109. * locking rate makes sense only for internal clock mode
  110. */
  111. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  112. {
  113. return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
  114. }
  115. /*
  116. * ac97 section
  117. */
  118. static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
  119. {
  120. unsigned char old_cmd;
  121. int tm;
  122. for (tm = 0; tm < 0x10000; tm++) {
  123. old_cmd = inb(ICEMT1724(ice, AC97_CMD));
  124. if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
  125. continue;
  126. if (!(old_cmd & VT1724_AC97_READY))
  127. continue;
  128. return old_cmd;
  129. }
  130. dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
  131. return old_cmd;
  132. }
  133. static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
  134. {
  135. int tm;
  136. for (tm = 0; tm < 0x10000; tm++)
  137. if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
  138. return 0;
  139. dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
  140. return -EIO;
  141. }
  142. static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
  143. unsigned short reg,
  144. unsigned short val)
  145. {
  146. struct snd_ice1712 *ice = ac97->private_data;
  147. unsigned char old_cmd;
  148. old_cmd = snd_vt1724_ac97_ready(ice);
  149. old_cmd &= ~VT1724_AC97_ID_MASK;
  150. old_cmd |= ac97->num;
  151. outb(reg, ICEMT1724(ice, AC97_INDEX));
  152. outw(val, ICEMT1724(ice, AC97_DATA));
  153. outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
  154. snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
  155. }
  156. static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  157. {
  158. struct snd_ice1712 *ice = ac97->private_data;
  159. unsigned char old_cmd;
  160. old_cmd = snd_vt1724_ac97_ready(ice);
  161. old_cmd &= ~VT1724_AC97_ID_MASK;
  162. old_cmd |= ac97->num;
  163. outb(reg, ICEMT1724(ice, AC97_INDEX));
  164. outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
  165. if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
  166. return ~0;
  167. return inw(ICEMT1724(ice, AC97_DATA));
  168. }
  169. /*
  170. * GPIO operations
  171. */
  172. /* set gpio direction 0 = read, 1 = write */
  173. static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  174. {
  175. outl(data, ICEREG1724(ice, GPIO_DIRECTION));
  176. inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
  177. }
  178. /* get gpio direction 0 = read, 1 = write */
  179. static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
  180. {
  181. return inl(ICEREG1724(ice, GPIO_DIRECTION));
  182. }
  183. /* set the gpio mask (0 = writable) */
  184. static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  185. {
  186. outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
  187. if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
  188. outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
  189. inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
  190. }
  191. static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
  192. {
  193. unsigned int mask;
  194. if (!ice->vt1720)
  195. mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
  196. else
  197. mask = 0;
  198. mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
  199. return mask;
  200. }
  201. static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
  202. {
  203. outw(data, ICEREG1724(ice, GPIO_DATA));
  204. if (!ice->vt1720)
  205. outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
  206. inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
  207. }
  208. static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
  209. {
  210. unsigned int data;
  211. if (!ice->vt1720)
  212. data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
  213. else
  214. data = 0;
  215. data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
  216. return data;
  217. }
  218. /*
  219. * MIDI
  220. */
  221. static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
  222. {
  223. unsigned int count;
  224. for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
  225. inb(ICEREG1724(ice, MPU_DATA));
  226. }
  227. static inline struct snd_rawmidi_substream *
  228. get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
  229. {
  230. return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
  231. struct snd_rawmidi_substream, list);
  232. }
  233. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
  234. static void vt1724_midi_write(struct snd_ice1712 *ice)
  235. {
  236. struct snd_rawmidi_substream *s;
  237. int count, i;
  238. u8 buffer[32];
  239. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
  240. count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
  241. if (count > 0) {
  242. count = snd_rawmidi_transmit(s, buffer, count);
  243. for (i = 0; i < count; ++i)
  244. outb(buffer[i], ICEREG1724(ice, MPU_DATA));
  245. }
  246. /* mask irq when all bytes have been transmitted.
  247. * enabled again in output_trigger when the new data comes in.
  248. */
  249. enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
  250. !snd_rawmidi_transmit_empty(s));
  251. }
  252. static void vt1724_midi_read(struct snd_ice1712 *ice)
  253. {
  254. struct snd_rawmidi_substream *s;
  255. int count, i;
  256. u8 buffer[32];
  257. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
  258. count = inb(ICEREG1724(ice, MPU_RXFIFO));
  259. if (count > 0) {
  260. count = min(count, 32);
  261. for (i = 0; i < count; ++i)
  262. buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
  263. snd_rawmidi_receive(s, buffer, count);
  264. }
  265. }
  266. /* call with ice->reg_lock */
  267. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
  268. {
  269. u8 mask = inb(ICEREG1724(ice, IRQMASK));
  270. if (enable)
  271. mask &= ~flag;
  272. else
  273. mask |= flag;
  274. outb(mask, ICEREG1724(ice, IRQMASK));
  275. }
  276. static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
  277. u8 flag, int enable)
  278. {
  279. struct snd_ice1712 *ice = substream->rmidi->private_data;
  280. spin_lock_irq(&ice->reg_lock);
  281. enable_midi_irq(ice, flag, enable);
  282. spin_unlock_irq(&ice->reg_lock);
  283. }
  284. static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
  285. {
  286. return 0;
  287. }
  288. static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
  289. {
  290. return 0;
  291. }
  292. static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
  293. {
  294. struct snd_ice1712 *ice = s->rmidi->private_data;
  295. unsigned long flags;
  296. spin_lock_irqsave(&ice->reg_lock, flags);
  297. if (up) {
  298. ice->midi_output = 1;
  299. vt1724_midi_write(ice);
  300. } else {
  301. ice->midi_output = 0;
  302. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  303. }
  304. spin_unlock_irqrestore(&ice->reg_lock, flags);
  305. }
  306. static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
  307. {
  308. struct snd_ice1712 *ice = s->rmidi->private_data;
  309. unsigned long timeout;
  310. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
  311. /* 32 bytes should be transmitted in less than about 12 ms */
  312. timeout = jiffies + msecs_to_jiffies(15);
  313. do {
  314. if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
  315. break;
  316. schedule_timeout_uninterruptible(1);
  317. } while (time_after(timeout, jiffies));
  318. }
  319. static const struct snd_rawmidi_ops vt1724_midi_output_ops = {
  320. .open = vt1724_midi_output_open,
  321. .close = vt1724_midi_output_close,
  322. .trigger = vt1724_midi_output_trigger,
  323. .drain = vt1724_midi_output_drain,
  324. };
  325. static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
  326. {
  327. vt1724_midi_clear_rx(s->rmidi->private_data);
  328. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
  329. return 0;
  330. }
  331. static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
  332. {
  333. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
  334. return 0;
  335. }
  336. static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
  337. {
  338. struct snd_ice1712 *ice = s->rmidi->private_data;
  339. unsigned long flags;
  340. spin_lock_irqsave(&ice->reg_lock, flags);
  341. if (up) {
  342. ice->midi_input = 1;
  343. vt1724_midi_read(ice);
  344. } else {
  345. ice->midi_input = 0;
  346. }
  347. spin_unlock_irqrestore(&ice->reg_lock, flags);
  348. }
  349. static const struct snd_rawmidi_ops vt1724_midi_input_ops = {
  350. .open = vt1724_midi_input_open,
  351. .close = vt1724_midi_input_close,
  352. .trigger = vt1724_midi_input_trigger,
  353. };
  354. /*
  355. * Interrupt handler
  356. */
  357. static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
  358. {
  359. struct snd_ice1712 *ice = dev_id;
  360. unsigned char status;
  361. unsigned char status_mask =
  362. VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
  363. int handled = 0;
  364. int timeout = 0;
  365. while (1) {
  366. status = inb(ICEREG1724(ice, IRQSTAT));
  367. status &= status_mask;
  368. if (status == 0)
  369. break;
  370. spin_lock(&ice->reg_lock);
  371. if (++timeout > 10) {
  372. status = inb(ICEREG1724(ice, IRQSTAT));
  373. dev_err(ice->card->dev,
  374. "Too long irq loop, status = 0x%x\n", status);
  375. if (status & VT1724_IRQ_MPU_TX) {
  376. dev_err(ice->card->dev, "Disabling MPU_TX\n");
  377. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  378. }
  379. spin_unlock(&ice->reg_lock);
  380. break;
  381. }
  382. handled = 1;
  383. if (status & VT1724_IRQ_MPU_TX) {
  384. if (ice->midi_output)
  385. vt1724_midi_write(ice);
  386. else
  387. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  388. /* Due to mysterical reasons, MPU_TX is always
  389. * generated (and can't be cleared) when a PCM
  390. * playback is going. So let's ignore at the
  391. * next loop.
  392. */
  393. status_mask &= ~VT1724_IRQ_MPU_TX;
  394. }
  395. if (status & VT1724_IRQ_MPU_RX) {
  396. if (ice->midi_input)
  397. vt1724_midi_read(ice);
  398. else
  399. vt1724_midi_clear_rx(ice);
  400. }
  401. /* ack MPU irq */
  402. outb(status, ICEREG1724(ice, IRQSTAT));
  403. spin_unlock(&ice->reg_lock);
  404. if (status & VT1724_IRQ_MTPCM) {
  405. /*
  406. * Multi-track PCM
  407. * PCM assignment are:
  408. * Playback DMA0 (M/C) = playback_pro_substream
  409. * Playback DMA1 = playback_con_substream_ds[0]
  410. * Playback DMA2 = playback_con_substream_ds[1]
  411. * Playback DMA3 = playback_con_substream_ds[2]
  412. * Playback DMA4 (SPDIF) = playback_con_substream
  413. * Record DMA0 = capture_pro_substream
  414. * Record DMA1 = capture_con_substream
  415. */
  416. unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
  417. if (mtstat & VT1724_MULTI_PDMA0) {
  418. if (ice->playback_pro_substream)
  419. snd_pcm_period_elapsed(ice->playback_pro_substream);
  420. }
  421. if (mtstat & VT1724_MULTI_RDMA0) {
  422. if (ice->capture_pro_substream)
  423. snd_pcm_period_elapsed(ice->capture_pro_substream);
  424. }
  425. if (mtstat & VT1724_MULTI_PDMA1) {
  426. if (ice->playback_con_substream_ds[0])
  427. snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
  428. }
  429. if (mtstat & VT1724_MULTI_PDMA2) {
  430. if (ice->playback_con_substream_ds[1])
  431. snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
  432. }
  433. if (mtstat & VT1724_MULTI_PDMA3) {
  434. if (ice->playback_con_substream_ds[2])
  435. snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
  436. }
  437. if (mtstat & VT1724_MULTI_PDMA4) {
  438. if (ice->playback_con_substream)
  439. snd_pcm_period_elapsed(ice->playback_con_substream);
  440. }
  441. if (mtstat & VT1724_MULTI_RDMA1) {
  442. if (ice->capture_con_substream)
  443. snd_pcm_period_elapsed(ice->capture_con_substream);
  444. }
  445. /* ack anyway to avoid freeze */
  446. outb(mtstat, ICEMT1724(ice, IRQ));
  447. /* ought to really handle this properly */
  448. if (mtstat & VT1724_MULTI_FIFO_ERR) {
  449. unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
  450. outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
  451. outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
  452. /* If I don't do this, I get machine lockup due to continual interrupts */
  453. }
  454. }
  455. }
  456. return IRQ_RETVAL(handled);
  457. }
  458. /*
  459. * PCM code - professional part (multitrack)
  460. */
  461. static const unsigned int rates[] = {
  462. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  463. 32000, 44100, 48000, 64000, 88200, 96000,
  464. 176400, 192000,
  465. };
  466. static const struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
  467. .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
  468. .list = rates,
  469. .mask = 0,
  470. };
  471. static const struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
  472. .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
  473. .list = rates,
  474. .mask = 0,
  475. };
  476. static const struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
  477. .count = ARRAY_SIZE(rates),
  478. .list = rates,
  479. .mask = 0,
  480. };
  481. struct vt1724_pcm_reg {
  482. unsigned int addr; /* ADDR register offset */
  483. unsigned int size; /* SIZE register offset */
  484. unsigned int count; /* COUNT register offset */
  485. unsigned int start; /* start & pause bit */
  486. };
  487. static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  488. {
  489. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  490. unsigned char what;
  491. unsigned char old;
  492. struct snd_pcm_substream *s;
  493. what = 0;
  494. snd_pcm_group_for_each_entry(s, substream) {
  495. if (snd_pcm_substream_chip(s) == ice) {
  496. const struct vt1724_pcm_reg *reg;
  497. reg = s->runtime->private_data;
  498. what |= reg->start;
  499. snd_pcm_trigger_done(s, substream);
  500. }
  501. }
  502. switch (cmd) {
  503. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  504. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  505. spin_lock(&ice->reg_lock);
  506. old = inb(ICEMT1724(ice, DMA_PAUSE));
  507. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  508. old |= what;
  509. else
  510. old &= ~what;
  511. outb(old, ICEMT1724(ice, DMA_PAUSE));
  512. spin_unlock(&ice->reg_lock);
  513. break;
  514. case SNDRV_PCM_TRIGGER_START:
  515. case SNDRV_PCM_TRIGGER_STOP:
  516. case SNDRV_PCM_TRIGGER_SUSPEND:
  517. spin_lock(&ice->reg_lock);
  518. old = inb(ICEMT1724(ice, DMA_CONTROL));
  519. if (cmd == SNDRV_PCM_TRIGGER_START)
  520. old |= what;
  521. else
  522. old &= ~what;
  523. outb(old, ICEMT1724(ice, DMA_CONTROL));
  524. spin_unlock(&ice->reg_lock);
  525. break;
  526. case SNDRV_PCM_TRIGGER_RESUME:
  527. /* apps will have to restart stream */
  528. break;
  529. default:
  530. return -EINVAL;
  531. }
  532. return 0;
  533. }
  534. /*
  535. */
  536. #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
  537. VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
  538. #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
  539. VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
  540. static const unsigned int stdclock_rate_list[16] = {
  541. 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
  542. 22050, 11025, 88200, 176400, 0, 192000, 64000
  543. };
  544. static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
  545. {
  546. return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
  547. }
  548. static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
  549. {
  550. int i;
  551. for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
  552. if (stdclock_rate_list[i] == rate) {
  553. outb(i, ICEMT1724(ice, RATE));
  554. return;
  555. }
  556. }
  557. }
  558. static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
  559. unsigned int rate)
  560. {
  561. unsigned char val, old;
  562. /* check MT02 */
  563. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  564. val = old = inb(ICEMT1724(ice, I2S_FORMAT));
  565. if (rate > 96000)
  566. val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
  567. else
  568. val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
  569. if (val != old) {
  570. outb(val, ICEMT1724(ice, I2S_FORMAT));
  571. /* master clock changed */
  572. return 1;
  573. }
  574. }
  575. /* no change in master clock */
  576. return 0;
  577. }
  578. static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
  579. int force)
  580. {
  581. unsigned long flags;
  582. unsigned char mclk_change;
  583. unsigned int i, old_rate;
  584. bool call_set_rate = false;
  585. if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
  586. return -EINVAL;
  587. spin_lock_irqsave(&ice->reg_lock, flags);
  588. if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
  589. (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
  590. /* running? we cannot change the rate now... */
  591. spin_unlock_irqrestore(&ice->reg_lock, flags);
  592. return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
  593. }
  594. if (!force && is_pro_rate_locked(ice)) {
  595. /* comparing required and current rate - makes sense for
  596. * internal clock only */
  597. spin_unlock_irqrestore(&ice->reg_lock, flags);
  598. return (rate == ice->cur_rate) ? 0 : -EBUSY;
  599. }
  600. if (force || !ice->is_spdif_master(ice)) {
  601. /* force means the rate was switched by ucontrol, otherwise
  602. * setting clock rate for internal clock mode */
  603. old_rate = ice->get_rate(ice);
  604. if (force || (old_rate != rate))
  605. call_set_rate = true;
  606. else if (rate == ice->cur_rate) {
  607. spin_unlock_irqrestore(&ice->reg_lock, flags);
  608. return 0;
  609. }
  610. }
  611. ice->cur_rate = rate;
  612. spin_unlock_irqrestore(&ice->reg_lock, flags);
  613. if (call_set_rate)
  614. ice->set_rate(ice, rate);
  615. /* setting master clock */
  616. mclk_change = ice->set_mclk(ice, rate);
  617. if (mclk_change && ice->gpio.i2s_mclk_changed)
  618. ice->gpio.i2s_mclk_changed(ice);
  619. if (ice->gpio.set_pro_rate)
  620. ice->gpio.set_pro_rate(ice, rate);
  621. /* set up codecs */
  622. for (i = 0; i < ice->akm_codecs; i++) {
  623. if (ice->akm[i].ops.set_rate_val)
  624. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  625. }
  626. if (ice->spdif.ops.setup_rate)
  627. ice->spdif.ops.setup_rate(ice, rate);
  628. return 0;
  629. }
  630. static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
  631. struct snd_pcm_hw_params *hw_params)
  632. {
  633. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  634. int i, chs, err;
  635. chs = params_channels(hw_params);
  636. mutex_lock(&ice->open_mutex);
  637. /* mark surround channels */
  638. if (substream == ice->playback_pro_substream) {
  639. /* PDMA0 can be multi-channel up to 8 */
  640. chs = chs / 2 - 1;
  641. for (i = 0; i < chs; i++) {
  642. if (ice->pcm_reserved[i] &&
  643. ice->pcm_reserved[i] != substream) {
  644. mutex_unlock(&ice->open_mutex);
  645. return -EBUSY;
  646. }
  647. ice->pcm_reserved[i] = substream;
  648. }
  649. for (; i < 3; i++) {
  650. if (ice->pcm_reserved[i] == substream)
  651. ice->pcm_reserved[i] = NULL;
  652. }
  653. } else {
  654. for (i = 0; i < 3; i++) {
  655. /* check individual playback stream */
  656. if (ice->playback_con_substream_ds[i] == substream) {
  657. if (ice->pcm_reserved[i] &&
  658. ice->pcm_reserved[i] != substream) {
  659. mutex_unlock(&ice->open_mutex);
  660. return -EBUSY;
  661. }
  662. ice->pcm_reserved[i] = substream;
  663. break;
  664. }
  665. }
  666. }
  667. mutex_unlock(&ice->open_mutex);
  668. err = snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
  669. if (err < 0)
  670. return err;
  671. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  672. }
  673. static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
  674. {
  675. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  676. int i;
  677. mutex_lock(&ice->open_mutex);
  678. /* unmark surround channels */
  679. for (i = 0; i < 3; i++)
  680. if (ice->pcm_reserved[i] == substream)
  681. ice->pcm_reserved[i] = NULL;
  682. mutex_unlock(&ice->open_mutex);
  683. return snd_pcm_lib_free_pages(substream);
  684. }
  685. static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
  686. {
  687. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  688. unsigned char val;
  689. unsigned int size;
  690. spin_lock_irq(&ice->reg_lock);
  691. val = (8 - substream->runtime->channels) >> 1;
  692. outb(val, ICEMT1724(ice, BURST));
  693. outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
  694. size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
  695. /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
  696. outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
  697. outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
  698. size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  699. /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
  700. outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
  701. outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
  702. spin_unlock_irq(&ice->reg_lock);
  703. /*
  704. dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
  705. "buffer = 0x%x, period = 0x%x\n",
  706. substream->runtime->channels,
  707. (unsigned int)substream->runtime->dma_addr,
  708. snd_pcm_lib_buffer_bytes(substream),
  709. snd_pcm_lib_period_bytes(substream));
  710. */
  711. return 0;
  712. }
  713. static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
  714. {
  715. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  716. size_t ptr;
  717. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
  718. return 0;
  719. #if 0 /* read PLAYBACK_ADDR */
  720. ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
  721. if (ptr < substream->runtime->dma_addr) {
  722. dev_dbg(ice->card->dev, "invalid negative ptr\n");
  723. return 0;
  724. }
  725. ptr -= substream->runtime->dma_addr;
  726. ptr = bytes_to_frames(substream->runtime, ptr);
  727. if (ptr >= substream->runtime->buffer_size) {
  728. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  729. (int)ptr, (int)substream->runtime->period_size);
  730. return 0;
  731. }
  732. #else /* read PLAYBACK_SIZE */
  733. ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
  734. ptr = (ptr + 1) << 2;
  735. ptr = bytes_to_frames(substream->runtime, ptr);
  736. if (!ptr)
  737. ;
  738. else if (ptr <= substream->runtime->buffer_size)
  739. ptr = substream->runtime->buffer_size - ptr;
  740. else {
  741. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  742. (int)ptr, (int)substream->runtime->buffer_size);
  743. ptr = 0;
  744. }
  745. #endif
  746. return ptr;
  747. }
  748. static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
  749. {
  750. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  751. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  752. spin_lock_irq(&ice->reg_lock);
  753. outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
  754. outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
  755. ice->profi_port + reg->size);
  756. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
  757. ice->profi_port + reg->count);
  758. spin_unlock_irq(&ice->reg_lock);
  759. return 0;
  760. }
  761. static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
  762. {
  763. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  764. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  765. size_t ptr;
  766. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
  767. return 0;
  768. #if 0 /* use ADDR register */
  769. ptr = inl(ice->profi_port + reg->addr);
  770. ptr -= substream->runtime->dma_addr;
  771. return bytes_to_frames(substream->runtime, ptr);
  772. #else /* use SIZE register */
  773. ptr = inw(ice->profi_port + reg->size);
  774. ptr = (ptr + 1) << 2;
  775. ptr = bytes_to_frames(substream->runtime, ptr);
  776. if (!ptr)
  777. ;
  778. else if (ptr <= substream->runtime->buffer_size)
  779. ptr = substream->runtime->buffer_size - ptr;
  780. else {
  781. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  782. (int)ptr, (int)substream->runtime->buffer_size);
  783. ptr = 0;
  784. }
  785. return ptr;
  786. #endif
  787. }
  788. static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
  789. .addr = VT1724_MT_PLAYBACK_ADDR,
  790. .size = VT1724_MT_PLAYBACK_SIZE,
  791. .count = VT1724_MT_PLAYBACK_COUNT,
  792. .start = VT1724_PDMA0_START,
  793. };
  794. static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
  795. .addr = VT1724_MT_PDMA4_ADDR,
  796. .size = VT1724_MT_PDMA4_SIZE,
  797. .count = VT1724_MT_PDMA4_COUNT,
  798. .start = VT1724_PDMA4_START,
  799. };
  800. static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
  801. .addr = VT1724_MT_CAPTURE_ADDR,
  802. .size = VT1724_MT_CAPTURE_SIZE,
  803. .count = VT1724_MT_CAPTURE_COUNT,
  804. .start = VT1724_RDMA0_START,
  805. };
  806. static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
  807. .addr = VT1724_MT_RDMA1_ADDR,
  808. .size = VT1724_MT_RDMA1_SIZE,
  809. .count = VT1724_MT_RDMA1_COUNT,
  810. .start = VT1724_RDMA1_START,
  811. };
  812. #define vt1724_playback_pro_reg vt1724_pdma0_reg
  813. #define vt1724_playback_spdif_reg vt1724_pdma4_reg
  814. #define vt1724_capture_pro_reg vt1724_rdma0_reg
  815. #define vt1724_capture_spdif_reg vt1724_rdma1_reg
  816. static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
  817. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  818. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  819. SNDRV_PCM_INFO_MMAP_VALID |
  820. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  821. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  822. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  823. .rate_min = 8000,
  824. .rate_max = 192000,
  825. .channels_min = 2,
  826. .channels_max = 8,
  827. .buffer_bytes_max = (1UL << 21), /* 19bits dword */
  828. .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
  829. .period_bytes_max = (1UL << 21),
  830. .periods_min = 2,
  831. .periods_max = 1024,
  832. };
  833. static const struct snd_pcm_hardware snd_vt1724_spdif = {
  834. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  835. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  836. SNDRV_PCM_INFO_MMAP_VALID |
  837. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  838. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  839. .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
  840. SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
  841. SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
  842. SNDRV_PCM_RATE_192000),
  843. .rate_min = 32000,
  844. .rate_max = 192000,
  845. .channels_min = 2,
  846. .channels_max = 2,
  847. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  848. .period_bytes_min = 2 * 4 * 2,
  849. .period_bytes_max = (1UL << 18),
  850. .periods_min = 2,
  851. .periods_max = 1024,
  852. };
  853. static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
  854. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  855. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  856. SNDRV_PCM_INFO_MMAP_VALID |
  857. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  858. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  859. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  860. .rate_min = 8000,
  861. .rate_max = 192000,
  862. .channels_min = 2,
  863. .channels_max = 2,
  864. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  865. .period_bytes_min = 2 * 4 * 2,
  866. .period_bytes_max = (1UL << 18),
  867. .periods_min = 2,
  868. .periods_max = 1024,
  869. };
  870. /*
  871. * set rate constraints
  872. */
  873. static void set_std_hw_rates(struct snd_ice1712 *ice)
  874. {
  875. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  876. /* I2S */
  877. /* VT1720 doesn't support more than 96kHz */
  878. if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
  879. ice->hw_rates = &hw_constraints_rates_192;
  880. else
  881. ice->hw_rates = &hw_constraints_rates_96;
  882. } else {
  883. /* ACLINK */
  884. ice->hw_rates = &hw_constraints_rates_48;
  885. }
  886. }
  887. static int set_rate_constraints(struct snd_ice1712 *ice,
  888. struct snd_pcm_substream *substream)
  889. {
  890. struct snd_pcm_runtime *runtime = substream->runtime;
  891. runtime->hw.rate_min = ice->hw_rates->list[0];
  892. runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
  893. runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
  894. return snd_pcm_hw_constraint_list(runtime, 0,
  895. SNDRV_PCM_HW_PARAM_RATE,
  896. ice->hw_rates);
  897. }
  898. /* if the card has the internal rate locked (is_pro_locked), limit runtime
  899. hw rates to the current internal rate only.
  900. */
  901. static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
  902. {
  903. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  904. struct snd_pcm_runtime *runtime = substream->runtime;
  905. unsigned int rate;
  906. if (is_pro_rate_locked(ice)) {
  907. rate = ice->get_rate(ice);
  908. if (rate >= runtime->hw.rate_min
  909. && rate <= runtime->hw.rate_max) {
  910. runtime->hw.rate_min = rate;
  911. runtime->hw.rate_max = rate;
  912. }
  913. }
  914. }
  915. /* multi-channel playback needs alignment 8x32bit regardless of the channels
  916. * actually used
  917. */
  918. #define VT1724_BUFFER_ALIGN 0x20
  919. static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
  920. {
  921. struct snd_pcm_runtime *runtime = substream->runtime;
  922. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  923. int chs, num_indeps;
  924. runtime->private_data = (void *)&vt1724_playback_pro_reg;
  925. ice->playback_pro_substream = substream;
  926. runtime->hw = snd_vt1724_playback_pro;
  927. snd_pcm_set_sync(substream);
  928. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  929. set_rate_constraints(ice, substream);
  930. mutex_lock(&ice->open_mutex);
  931. /* calculate the currently available channels */
  932. num_indeps = ice->num_total_dacs / 2 - 1;
  933. for (chs = 0; chs < num_indeps; chs++) {
  934. if (ice->pcm_reserved[chs])
  935. break;
  936. }
  937. chs = (chs + 1) * 2;
  938. runtime->hw.channels_max = chs;
  939. if (chs > 2) /* channels must be even */
  940. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  941. mutex_unlock(&ice->open_mutex);
  942. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  943. VT1724_BUFFER_ALIGN);
  944. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  945. VT1724_BUFFER_ALIGN);
  946. constrain_rate_if_locked(substream);
  947. if (ice->pro_open)
  948. ice->pro_open(ice, substream);
  949. return 0;
  950. }
  951. static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
  952. {
  953. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  954. struct snd_pcm_runtime *runtime = substream->runtime;
  955. runtime->private_data = (void *)&vt1724_capture_pro_reg;
  956. ice->capture_pro_substream = substream;
  957. runtime->hw = snd_vt1724_2ch_stereo;
  958. snd_pcm_set_sync(substream);
  959. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  960. set_rate_constraints(ice, substream);
  961. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  962. VT1724_BUFFER_ALIGN);
  963. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  964. VT1724_BUFFER_ALIGN);
  965. constrain_rate_if_locked(substream);
  966. if (ice->pro_open)
  967. ice->pro_open(ice, substream);
  968. return 0;
  969. }
  970. static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
  971. {
  972. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  973. if (PRO_RATE_RESET)
  974. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  975. ice->playback_pro_substream = NULL;
  976. return 0;
  977. }
  978. static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
  979. {
  980. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  981. if (PRO_RATE_RESET)
  982. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  983. ice->capture_pro_substream = NULL;
  984. return 0;
  985. }
  986. static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
  987. .open = snd_vt1724_playback_pro_open,
  988. .close = snd_vt1724_playback_pro_close,
  989. .ioctl = snd_pcm_lib_ioctl,
  990. .hw_params = snd_vt1724_pcm_hw_params,
  991. .hw_free = snd_vt1724_pcm_hw_free,
  992. .prepare = snd_vt1724_playback_pro_prepare,
  993. .trigger = snd_vt1724_pcm_trigger,
  994. .pointer = snd_vt1724_playback_pro_pointer,
  995. };
  996. static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
  997. .open = snd_vt1724_capture_pro_open,
  998. .close = snd_vt1724_capture_pro_close,
  999. .ioctl = snd_pcm_lib_ioctl,
  1000. .hw_params = snd_vt1724_pcm_hw_params,
  1001. .hw_free = snd_vt1724_pcm_hw_free,
  1002. .prepare = snd_vt1724_pcm_prepare,
  1003. .trigger = snd_vt1724_pcm_trigger,
  1004. .pointer = snd_vt1724_pcm_pointer,
  1005. };
  1006. static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
  1007. {
  1008. struct snd_pcm *pcm;
  1009. int capt, err;
  1010. if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
  1011. VT1724_CFG_ADC_NONE)
  1012. capt = 0;
  1013. else
  1014. capt = 1;
  1015. err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
  1016. if (err < 0)
  1017. return err;
  1018. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
  1019. if (capt)
  1020. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1021. &snd_vt1724_capture_pro_ops);
  1022. pcm->private_data = ice;
  1023. pcm->info_flags = 0;
  1024. strcpy(pcm->name, "ICE1724");
  1025. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1026. snd_dma_pci_data(ice->pci),
  1027. 256*1024, 256*1024);
  1028. ice->pcm_pro = pcm;
  1029. return 0;
  1030. }
  1031. /*
  1032. * SPDIF PCM
  1033. */
  1034. /* update spdif control bits; call with reg_lock */
  1035. static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
  1036. {
  1037. unsigned char cbit, disabled;
  1038. cbit = inb(ICEREG1724(ice, SPDIF_CFG));
  1039. disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
  1040. if (cbit != disabled)
  1041. outb(disabled, ICEREG1724(ice, SPDIF_CFG));
  1042. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1043. if (cbit != disabled)
  1044. outb(cbit, ICEREG1724(ice, SPDIF_CFG));
  1045. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1046. }
  1047. /* update SPDIF control bits according to the given rate */
  1048. static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
  1049. {
  1050. unsigned int val, nval;
  1051. unsigned long flags;
  1052. spin_lock_irqsave(&ice->reg_lock, flags);
  1053. nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1054. nval &= ~(7 << 12);
  1055. switch (rate) {
  1056. case 44100: break;
  1057. case 48000: nval |= 2 << 12; break;
  1058. case 32000: nval |= 3 << 12; break;
  1059. case 88200: nval |= 4 << 12; break;
  1060. case 96000: nval |= 5 << 12; break;
  1061. case 192000: nval |= 6 << 12; break;
  1062. case 176400: nval |= 7 << 12; break;
  1063. }
  1064. if (val != nval)
  1065. update_spdif_bits(ice, nval);
  1066. spin_unlock_irqrestore(&ice->reg_lock, flags);
  1067. }
  1068. static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
  1069. {
  1070. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1071. if (!ice->force_pdma4)
  1072. update_spdif_rate(ice, substream->runtime->rate);
  1073. return snd_vt1724_pcm_prepare(substream);
  1074. }
  1075. static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
  1076. {
  1077. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1078. struct snd_pcm_runtime *runtime = substream->runtime;
  1079. runtime->private_data = (void *)&vt1724_playback_spdif_reg;
  1080. ice->playback_con_substream = substream;
  1081. if (ice->force_pdma4) {
  1082. runtime->hw = snd_vt1724_2ch_stereo;
  1083. set_rate_constraints(ice, substream);
  1084. } else
  1085. runtime->hw = snd_vt1724_spdif;
  1086. snd_pcm_set_sync(substream);
  1087. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1088. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1089. VT1724_BUFFER_ALIGN);
  1090. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1091. VT1724_BUFFER_ALIGN);
  1092. constrain_rate_if_locked(substream);
  1093. if (ice->spdif.ops.open)
  1094. ice->spdif.ops.open(ice, substream);
  1095. return 0;
  1096. }
  1097. static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
  1098. {
  1099. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1100. if (PRO_RATE_RESET)
  1101. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1102. ice->playback_con_substream = NULL;
  1103. if (ice->spdif.ops.close)
  1104. ice->spdif.ops.close(ice, substream);
  1105. return 0;
  1106. }
  1107. static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
  1108. {
  1109. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1110. struct snd_pcm_runtime *runtime = substream->runtime;
  1111. runtime->private_data = (void *)&vt1724_capture_spdif_reg;
  1112. ice->capture_con_substream = substream;
  1113. if (ice->force_rdma1) {
  1114. runtime->hw = snd_vt1724_2ch_stereo;
  1115. set_rate_constraints(ice, substream);
  1116. } else
  1117. runtime->hw = snd_vt1724_spdif;
  1118. snd_pcm_set_sync(substream);
  1119. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1120. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1121. VT1724_BUFFER_ALIGN);
  1122. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1123. VT1724_BUFFER_ALIGN);
  1124. constrain_rate_if_locked(substream);
  1125. if (ice->spdif.ops.open)
  1126. ice->spdif.ops.open(ice, substream);
  1127. return 0;
  1128. }
  1129. static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
  1130. {
  1131. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1132. if (PRO_RATE_RESET)
  1133. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1134. ice->capture_con_substream = NULL;
  1135. if (ice->spdif.ops.close)
  1136. ice->spdif.ops.close(ice, substream);
  1137. return 0;
  1138. }
  1139. static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
  1140. .open = snd_vt1724_playback_spdif_open,
  1141. .close = snd_vt1724_playback_spdif_close,
  1142. .ioctl = snd_pcm_lib_ioctl,
  1143. .hw_params = snd_vt1724_pcm_hw_params,
  1144. .hw_free = snd_vt1724_pcm_hw_free,
  1145. .prepare = snd_vt1724_playback_spdif_prepare,
  1146. .trigger = snd_vt1724_pcm_trigger,
  1147. .pointer = snd_vt1724_pcm_pointer,
  1148. };
  1149. static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
  1150. .open = snd_vt1724_capture_spdif_open,
  1151. .close = snd_vt1724_capture_spdif_close,
  1152. .ioctl = snd_pcm_lib_ioctl,
  1153. .hw_params = snd_vt1724_pcm_hw_params,
  1154. .hw_free = snd_vt1724_pcm_hw_free,
  1155. .prepare = snd_vt1724_pcm_prepare,
  1156. .trigger = snd_vt1724_pcm_trigger,
  1157. .pointer = snd_vt1724_pcm_pointer,
  1158. };
  1159. static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
  1160. {
  1161. char *name;
  1162. struct snd_pcm *pcm;
  1163. int play, capt;
  1164. int err;
  1165. if (ice->force_pdma4 ||
  1166. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
  1167. play = 1;
  1168. ice->has_spdif = 1;
  1169. } else
  1170. play = 0;
  1171. if (ice->force_rdma1 ||
  1172. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
  1173. capt = 1;
  1174. ice->has_spdif = 1;
  1175. } else
  1176. capt = 0;
  1177. if (!play && !capt)
  1178. return 0; /* no spdif device */
  1179. if (ice->force_pdma4 || ice->force_rdma1)
  1180. name = "ICE1724 Secondary";
  1181. else
  1182. name = "ICE1724 IEC958";
  1183. err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
  1184. if (err < 0)
  1185. return err;
  1186. if (play)
  1187. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1188. &snd_vt1724_playback_spdif_ops);
  1189. if (capt)
  1190. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1191. &snd_vt1724_capture_spdif_ops);
  1192. pcm->private_data = ice;
  1193. pcm->info_flags = 0;
  1194. strcpy(pcm->name, name);
  1195. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1196. snd_dma_pci_data(ice->pci),
  1197. 256*1024, 256*1024);
  1198. ice->pcm = pcm;
  1199. return 0;
  1200. }
  1201. /*
  1202. * independent surround PCMs
  1203. */
  1204. static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
  1205. {
  1206. .addr = VT1724_MT_PDMA1_ADDR,
  1207. .size = VT1724_MT_PDMA1_SIZE,
  1208. .count = VT1724_MT_PDMA1_COUNT,
  1209. .start = VT1724_PDMA1_START,
  1210. },
  1211. {
  1212. .addr = VT1724_MT_PDMA2_ADDR,
  1213. .size = VT1724_MT_PDMA2_SIZE,
  1214. .count = VT1724_MT_PDMA2_COUNT,
  1215. .start = VT1724_PDMA2_START,
  1216. },
  1217. {
  1218. .addr = VT1724_MT_PDMA3_ADDR,
  1219. .size = VT1724_MT_PDMA3_SIZE,
  1220. .count = VT1724_MT_PDMA3_COUNT,
  1221. .start = VT1724_PDMA3_START,
  1222. },
  1223. };
  1224. static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
  1225. {
  1226. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1227. unsigned char val;
  1228. spin_lock_irq(&ice->reg_lock);
  1229. val = 3 - substream->number;
  1230. if (inb(ICEMT1724(ice, BURST)) < val)
  1231. outb(val, ICEMT1724(ice, BURST));
  1232. spin_unlock_irq(&ice->reg_lock);
  1233. return snd_vt1724_pcm_prepare(substream);
  1234. }
  1235. static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
  1236. {
  1237. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1238. struct snd_pcm_runtime *runtime = substream->runtime;
  1239. mutex_lock(&ice->open_mutex);
  1240. /* already used by PDMA0? */
  1241. if (ice->pcm_reserved[substream->number]) {
  1242. mutex_unlock(&ice->open_mutex);
  1243. return -EBUSY; /* FIXME: should handle blocking mode properly */
  1244. }
  1245. mutex_unlock(&ice->open_mutex);
  1246. runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
  1247. ice->playback_con_substream_ds[substream->number] = substream;
  1248. runtime->hw = snd_vt1724_2ch_stereo;
  1249. snd_pcm_set_sync(substream);
  1250. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1251. set_rate_constraints(ice, substream);
  1252. return 0;
  1253. }
  1254. static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
  1255. {
  1256. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1257. if (PRO_RATE_RESET)
  1258. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1259. ice->playback_con_substream_ds[substream->number] = NULL;
  1260. ice->pcm_reserved[substream->number] = NULL;
  1261. return 0;
  1262. }
  1263. static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
  1264. .open = snd_vt1724_playback_indep_open,
  1265. .close = snd_vt1724_playback_indep_close,
  1266. .ioctl = snd_pcm_lib_ioctl,
  1267. .hw_params = snd_vt1724_pcm_hw_params,
  1268. .hw_free = snd_vt1724_pcm_hw_free,
  1269. .prepare = snd_vt1724_playback_indep_prepare,
  1270. .trigger = snd_vt1724_pcm_trigger,
  1271. .pointer = snd_vt1724_pcm_pointer,
  1272. };
  1273. static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
  1274. {
  1275. struct snd_pcm *pcm;
  1276. int play;
  1277. int err;
  1278. play = ice->num_total_dacs / 2 - 1;
  1279. if (play <= 0)
  1280. return 0;
  1281. err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
  1282. if (err < 0)
  1283. return err;
  1284. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1285. &snd_vt1724_playback_indep_ops);
  1286. pcm->private_data = ice;
  1287. pcm->info_flags = 0;
  1288. strcpy(pcm->name, "ICE1724 Surround PCM");
  1289. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1290. snd_dma_pci_data(ice->pci),
  1291. 256*1024, 256*1024);
  1292. ice->pcm_ds = pcm;
  1293. return 0;
  1294. }
  1295. /*
  1296. * Mixer section
  1297. */
  1298. static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
  1299. {
  1300. int err;
  1301. if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
  1302. struct snd_ac97_bus *pbus;
  1303. struct snd_ac97_template ac97;
  1304. static struct snd_ac97_bus_ops ops = {
  1305. .write = snd_vt1724_ac97_write,
  1306. .read = snd_vt1724_ac97_read,
  1307. };
  1308. /* cold reset */
  1309. outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
  1310. mdelay(5); /* FIXME */
  1311. outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
  1312. err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
  1313. if (err < 0)
  1314. return err;
  1315. memset(&ac97, 0, sizeof(ac97));
  1316. ac97.private_data = ice;
  1317. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1318. if (err < 0)
  1319. dev_warn(ice->card->dev,
  1320. "cannot initialize pro ac97, skipped\n");
  1321. else
  1322. return 0;
  1323. }
  1324. /* I2S mixer only */
  1325. strcat(ice->card->mixername, "ICE1724 - multitrack");
  1326. return 0;
  1327. }
  1328. /*
  1329. *
  1330. */
  1331. static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
  1332. {
  1333. return (unsigned int)ice->eeprom.data[idx] | \
  1334. ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
  1335. ((unsigned int)ice->eeprom.data[idx + 2] << 16);
  1336. }
  1337. static void snd_vt1724_proc_read(struct snd_info_entry *entry,
  1338. struct snd_info_buffer *buffer)
  1339. {
  1340. struct snd_ice1712 *ice = entry->private_data;
  1341. unsigned int idx;
  1342. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1343. snd_iprintf(buffer, "EEPROM:\n");
  1344. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1345. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1346. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1347. snd_iprintf(buffer, " System Config : 0x%x\n",
  1348. ice->eeprom.data[ICE_EEP2_SYSCONF]);
  1349. snd_iprintf(buffer, " ACLink : 0x%x\n",
  1350. ice->eeprom.data[ICE_EEP2_ACLINK]);
  1351. snd_iprintf(buffer, " I2S : 0x%x\n",
  1352. ice->eeprom.data[ICE_EEP2_I2S]);
  1353. snd_iprintf(buffer, " S/PDIF : 0x%x\n",
  1354. ice->eeprom.data[ICE_EEP2_SPDIF]);
  1355. snd_iprintf(buffer, " GPIO direction : 0x%x\n",
  1356. ice->eeprom.gpiodir);
  1357. snd_iprintf(buffer, " GPIO mask : 0x%x\n",
  1358. ice->eeprom.gpiomask);
  1359. snd_iprintf(buffer, " GPIO state : 0x%x\n",
  1360. ice->eeprom.gpiostate);
  1361. for (idx = 0x12; idx < ice->eeprom.size; idx++)
  1362. snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
  1363. idx, ice->eeprom.data[idx]);
  1364. snd_iprintf(buffer, "\nRegisters:\n");
  1365. snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
  1366. (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
  1367. for (idx = 0x0; idx < 0x20 ; idx++)
  1368. snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
  1369. idx, inb(ice->port+idx));
  1370. for (idx = 0x0; idx < 0x30 ; idx++)
  1371. snd_iprintf(buffer, " MT%02x : 0x%02x\n",
  1372. idx, inb(ice->profi_port+idx));
  1373. }
  1374. static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
  1375. {
  1376. struct snd_info_entry *entry;
  1377. if (!snd_card_proc_new(ice->card, "ice1724", &entry))
  1378. snd_info_set_text_ops(entry, ice, snd_vt1724_proc_read);
  1379. }
  1380. /*
  1381. *
  1382. */
  1383. static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
  1384. struct snd_ctl_elem_info *uinfo)
  1385. {
  1386. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1387. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1388. return 0;
  1389. }
  1390. static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
  1391. struct snd_ctl_elem_value *ucontrol)
  1392. {
  1393. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1394. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1395. return 0;
  1396. }
  1397. static const struct snd_kcontrol_new snd_vt1724_eeprom = {
  1398. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1399. .name = "ICE1724 EEPROM",
  1400. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1401. .info = snd_vt1724_eeprom_info,
  1402. .get = snd_vt1724_eeprom_get
  1403. };
  1404. /*
  1405. */
  1406. static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
  1407. struct snd_ctl_elem_info *uinfo)
  1408. {
  1409. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1410. uinfo->count = 1;
  1411. return 0;
  1412. }
  1413. static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
  1414. {
  1415. unsigned int val, rbits;
  1416. val = diga->status[0] & 0x03; /* professional, non-audio */
  1417. if (val & 0x01) {
  1418. /* professional */
  1419. if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
  1420. IEC958_AES0_PRO_EMPHASIS_5015)
  1421. val |= 1U << 3;
  1422. rbits = (diga->status[4] >> 3) & 0x0f;
  1423. if (rbits) {
  1424. switch (rbits) {
  1425. case 2: val |= 5 << 12; break; /* 96k */
  1426. case 3: val |= 6 << 12; break; /* 192k */
  1427. case 10: val |= 4 << 12; break; /* 88.2k */
  1428. case 11: val |= 7 << 12; break; /* 176.4k */
  1429. }
  1430. } else {
  1431. switch (diga->status[0] & IEC958_AES0_PRO_FS) {
  1432. case IEC958_AES0_PRO_FS_44100:
  1433. break;
  1434. case IEC958_AES0_PRO_FS_32000:
  1435. val |= 3U << 12;
  1436. break;
  1437. default:
  1438. val |= 2U << 12;
  1439. break;
  1440. }
  1441. }
  1442. } else {
  1443. /* consumer */
  1444. val |= diga->status[1] & 0x04; /* copyright */
  1445. if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
  1446. IEC958_AES0_CON_EMPHASIS_5015)
  1447. val |= 1U << 3;
  1448. val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
  1449. val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
  1450. }
  1451. return val;
  1452. }
  1453. static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
  1454. {
  1455. memset(diga->status, 0, sizeof(diga->status));
  1456. diga->status[0] = val & 0x03; /* professional, non-audio */
  1457. if (val & 0x01) {
  1458. /* professional */
  1459. if (val & (1U << 3))
  1460. diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
  1461. switch ((val >> 12) & 0x7) {
  1462. case 0:
  1463. break;
  1464. case 2:
  1465. diga->status[0] |= IEC958_AES0_PRO_FS_32000;
  1466. break;
  1467. default:
  1468. diga->status[0] |= IEC958_AES0_PRO_FS_48000;
  1469. break;
  1470. }
  1471. } else {
  1472. /* consumer */
  1473. diga->status[0] |= val & (1U << 2); /* copyright */
  1474. if (val & (1U << 3))
  1475. diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
  1476. diga->status[1] |= (val >> 4) & 0x3f; /* category */
  1477. diga->status[3] |= (val >> 12) & 0x07; /* fs */
  1478. }
  1479. }
  1480. static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
  1481. struct snd_ctl_elem_value *ucontrol)
  1482. {
  1483. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1484. unsigned int val;
  1485. val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1486. decode_spdif_bits(&ucontrol->value.iec958, val);
  1487. return 0;
  1488. }
  1489. static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
  1490. struct snd_ctl_elem_value *ucontrol)
  1491. {
  1492. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1493. unsigned int val, old;
  1494. val = encode_spdif_bits(&ucontrol->value.iec958);
  1495. spin_lock_irq(&ice->reg_lock);
  1496. old = inw(ICEMT1724(ice, SPDIF_CTRL));
  1497. if (val != old)
  1498. update_spdif_bits(ice, val);
  1499. spin_unlock_irq(&ice->reg_lock);
  1500. return val != old;
  1501. }
  1502. static const struct snd_kcontrol_new snd_vt1724_spdif_default =
  1503. {
  1504. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1505. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1506. .info = snd_vt1724_spdif_info,
  1507. .get = snd_vt1724_spdif_default_get,
  1508. .put = snd_vt1724_spdif_default_put
  1509. };
  1510. static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1514. IEC958_AES0_PROFESSIONAL |
  1515. IEC958_AES0_CON_NOT_COPYRIGHT |
  1516. IEC958_AES0_CON_EMPHASIS;
  1517. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1518. IEC958_AES1_CON_CATEGORY;
  1519. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1520. return 0;
  1521. }
  1522. static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1523. struct snd_ctl_elem_value *ucontrol)
  1524. {
  1525. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1526. IEC958_AES0_PROFESSIONAL |
  1527. IEC958_AES0_PRO_FS |
  1528. IEC958_AES0_PRO_EMPHASIS;
  1529. return 0;
  1530. }
  1531. static const struct snd_kcontrol_new snd_vt1724_spdif_maskc =
  1532. {
  1533. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1534. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1535. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1536. .info = snd_vt1724_spdif_info,
  1537. .get = snd_vt1724_spdif_maskc_get,
  1538. };
  1539. static const struct snd_kcontrol_new snd_vt1724_spdif_maskp =
  1540. {
  1541. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1542. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1543. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1544. .info = snd_vt1724_spdif_info,
  1545. .get = snd_vt1724_spdif_maskp_get,
  1546. };
  1547. #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
  1548. static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
  1549. struct snd_ctl_elem_value *ucontrol)
  1550. {
  1551. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1552. ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
  1553. VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
  1554. return 0;
  1555. }
  1556. static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
  1557. struct snd_ctl_elem_value *ucontrol)
  1558. {
  1559. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1560. unsigned char old, val;
  1561. spin_lock_irq(&ice->reg_lock);
  1562. old = val = inb(ICEREG1724(ice, SPDIF_CFG));
  1563. val &= ~VT1724_CFG_SPDIF_OUT_EN;
  1564. if (ucontrol->value.integer.value[0])
  1565. val |= VT1724_CFG_SPDIF_OUT_EN;
  1566. if (old != val)
  1567. outb(val, ICEREG1724(ice, SPDIF_CFG));
  1568. spin_unlock_irq(&ice->reg_lock);
  1569. return old != val;
  1570. }
  1571. static const struct snd_kcontrol_new snd_vt1724_spdif_switch =
  1572. {
  1573. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1574. /* FIXME: the following conflict with IEC958 Playback Route */
  1575. /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
  1576. .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
  1577. .info = snd_vt1724_spdif_sw_info,
  1578. .get = snd_vt1724_spdif_sw_get,
  1579. .put = snd_vt1724_spdif_sw_put
  1580. };
  1581. #if 0 /* NOT USED YET */
  1582. /*
  1583. * GPIO access from extern
  1584. */
  1585. #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
  1586. int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
  1587. struct snd_ctl_elem_value *ucontrol)
  1588. {
  1589. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1590. int shift = kcontrol->private_value & 0xff;
  1591. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1592. snd_ice1712_save_gpio_status(ice);
  1593. ucontrol->value.integer.value[0] =
  1594. (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
  1595. snd_ice1712_restore_gpio_status(ice);
  1596. return 0;
  1597. }
  1598. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1599. struct snd_ctl_elem_value *ucontrol)
  1600. {
  1601. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1602. int shift = kcontrol->private_value & 0xff;
  1603. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1604. unsigned int val, nval;
  1605. if (kcontrol->private_value & (1 << 31))
  1606. return -EPERM;
  1607. nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
  1608. snd_ice1712_save_gpio_status(ice);
  1609. val = snd_ice1712_gpio_read(ice);
  1610. nval |= val & ~(1 << shift);
  1611. if (val != nval)
  1612. snd_ice1712_gpio_write(ice, nval);
  1613. snd_ice1712_restore_gpio_status(ice);
  1614. return val != nval;
  1615. }
  1616. #endif /* NOT USED YET */
  1617. /*
  1618. * rate
  1619. */
  1620. static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1621. struct snd_ctl_elem_info *uinfo)
  1622. {
  1623. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1624. int hw_rates_count = ice->hw_rates->count;
  1625. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1626. uinfo->count = 1;
  1627. /* internal clocks */
  1628. uinfo->value.enumerated.items = hw_rates_count;
  1629. /* external clocks */
  1630. if (ice->force_rdma1 ||
  1631. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
  1632. uinfo->value.enumerated.items += ice->ext_clock_count;
  1633. /* upper limit - keep at top */
  1634. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1635. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1636. if (uinfo->value.enumerated.item >= hw_rates_count)
  1637. /* ext_clock items */
  1638. strcpy(uinfo->value.enumerated.name,
  1639. ice->ext_clock_names[
  1640. uinfo->value.enumerated.item - hw_rates_count]);
  1641. else
  1642. /* int clock items */
  1643. sprintf(uinfo->value.enumerated.name, "%d",
  1644. ice->hw_rates->list[uinfo->value.enumerated.item]);
  1645. return 0;
  1646. }
  1647. static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1648. struct snd_ctl_elem_value *ucontrol)
  1649. {
  1650. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1651. unsigned int i, rate;
  1652. spin_lock_irq(&ice->reg_lock);
  1653. if (ice->is_spdif_master(ice)) {
  1654. ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
  1655. ice->get_spdif_master_type(ice);
  1656. } else {
  1657. rate = ice->get_rate(ice);
  1658. ucontrol->value.enumerated.item[0] = 0;
  1659. for (i = 0; i < ice->hw_rates->count; i++) {
  1660. if (ice->hw_rates->list[i] == rate) {
  1661. ucontrol->value.enumerated.item[0] = i;
  1662. break;
  1663. }
  1664. }
  1665. }
  1666. spin_unlock_irq(&ice->reg_lock);
  1667. return 0;
  1668. }
  1669. static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
  1670. {
  1671. /* standard external clock - only single type - SPDIF IN */
  1672. return 0;
  1673. }
  1674. /* setting clock to external - SPDIF */
  1675. static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
  1676. {
  1677. unsigned char oval;
  1678. unsigned char i2s_oval;
  1679. oval = inb(ICEMT1724(ice, RATE));
  1680. outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
  1681. /* setting 256fs */
  1682. i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
  1683. outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
  1684. return 0;
  1685. }
  1686. static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1687. struct snd_ctl_elem_value *ucontrol)
  1688. {
  1689. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1690. unsigned int old_rate, new_rate;
  1691. unsigned int item = ucontrol->value.enumerated.item[0];
  1692. unsigned int first_ext_clock = ice->hw_rates->count;
  1693. if (item > first_ext_clock + ice->ext_clock_count - 1)
  1694. return -EINVAL;
  1695. /* if rate = 0 => external clock */
  1696. spin_lock_irq(&ice->reg_lock);
  1697. if (ice->is_spdif_master(ice))
  1698. old_rate = 0;
  1699. else
  1700. old_rate = ice->get_rate(ice);
  1701. if (item >= first_ext_clock) {
  1702. /* switching to external clock */
  1703. ice->set_spdif_clock(ice, item - first_ext_clock);
  1704. new_rate = 0;
  1705. } else {
  1706. /* internal on-card clock */
  1707. new_rate = ice->hw_rates->list[item];
  1708. ice->pro_rate_default = new_rate;
  1709. spin_unlock_irq(&ice->reg_lock);
  1710. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
  1711. spin_lock_irq(&ice->reg_lock);
  1712. }
  1713. spin_unlock_irq(&ice->reg_lock);
  1714. /* the first switch to the ext. clock mode? */
  1715. if (old_rate != new_rate && !new_rate) {
  1716. /* notify akm chips as well */
  1717. unsigned int i;
  1718. if (ice->gpio.set_pro_rate)
  1719. ice->gpio.set_pro_rate(ice, 0);
  1720. for (i = 0; i < ice->akm_codecs; i++) {
  1721. if (ice->akm[i].ops.set_rate_val)
  1722. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  1723. }
  1724. }
  1725. return old_rate != new_rate;
  1726. }
  1727. static const struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
  1728. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1729. .name = "Multi Track Internal Clock",
  1730. .info = snd_vt1724_pro_internal_clock_info,
  1731. .get = snd_vt1724_pro_internal_clock_get,
  1732. .put = snd_vt1724_pro_internal_clock_put
  1733. };
  1734. #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
  1735. static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1736. struct snd_ctl_elem_value *ucontrol)
  1737. {
  1738. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1739. return 0;
  1740. }
  1741. static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1742. struct snd_ctl_elem_value *ucontrol)
  1743. {
  1744. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1745. int change = 0, nval;
  1746. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1747. spin_lock_irq(&ice->reg_lock);
  1748. change = PRO_RATE_LOCKED != nval;
  1749. PRO_RATE_LOCKED = nval;
  1750. spin_unlock_irq(&ice->reg_lock);
  1751. return change;
  1752. }
  1753. static const struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
  1754. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1755. .name = "Multi Track Rate Locking",
  1756. .info = snd_vt1724_pro_rate_locking_info,
  1757. .get = snd_vt1724_pro_rate_locking_get,
  1758. .put = snd_vt1724_pro_rate_locking_put
  1759. };
  1760. #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
  1761. static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1762. struct snd_ctl_elem_value *ucontrol)
  1763. {
  1764. ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
  1765. return 0;
  1766. }
  1767. static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1768. struct snd_ctl_elem_value *ucontrol)
  1769. {
  1770. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1771. int change = 0, nval;
  1772. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1773. spin_lock_irq(&ice->reg_lock);
  1774. change = PRO_RATE_RESET != nval;
  1775. PRO_RATE_RESET = nval;
  1776. spin_unlock_irq(&ice->reg_lock);
  1777. return change;
  1778. }
  1779. static const struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
  1780. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1781. .name = "Multi Track Rate Reset",
  1782. .info = snd_vt1724_pro_rate_reset_info,
  1783. .get = snd_vt1724_pro_rate_reset_get,
  1784. .put = snd_vt1724_pro_rate_reset_put
  1785. };
  1786. /*
  1787. * routing
  1788. */
  1789. static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
  1790. struct snd_ctl_elem_info *uinfo)
  1791. {
  1792. static const char * const texts[] = {
  1793. "PCM Out", /* 0 */
  1794. "H/W In 0", "H/W In 1", /* 1-2 */
  1795. "IEC958 In L", "IEC958 In R", /* 3-4 */
  1796. };
  1797. return snd_ctl_enum_info(uinfo, 1, 5, texts);
  1798. }
  1799. static inline int analog_route_shift(int idx)
  1800. {
  1801. return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
  1802. }
  1803. static inline int digital_route_shift(int idx)
  1804. {
  1805. return idx * 3;
  1806. }
  1807. int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
  1808. {
  1809. unsigned long val;
  1810. unsigned char eitem;
  1811. static const unsigned char xlate[8] = {
  1812. 0, 255, 1, 2, 255, 255, 3, 4,
  1813. };
  1814. val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1815. val >>= shift;
  1816. val &= 7; /* we now have 3 bits per output */
  1817. eitem = xlate[val];
  1818. if (eitem == 255) {
  1819. snd_BUG();
  1820. return 0;
  1821. }
  1822. return eitem;
  1823. }
  1824. int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
  1825. int shift)
  1826. {
  1827. unsigned int old_val, nval;
  1828. int change;
  1829. static const unsigned char xroute[8] = {
  1830. 0, /* PCM */
  1831. 2, /* PSDIN0 Left */
  1832. 3, /* PSDIN0 Right */
  1833. 6, /* SPDIN Left */
  1834. 7, /* SPDIN Right */
  1835. };
  1836. nval = xroute[val % 5];
  1837. val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1838. val &= ~(0x07 << shift);
  1839. val |= nval << shift;
  1840. change = val != old_val;
  1841. if (change)
  1842. outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
  1843. return change;
  1844. }
  1845. static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1846. struct snd_ctl_elem_value *ucontrol)
  1847. {
  1848. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1849. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1850. ucontrol->value.enumerated.item[0] =
  1851. snd_ice1724_get_route_val(ice, analog_route_shift(idx));
  1852. return 0;
  1853. }
  1854. static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1855. struct snd_ctl_elem_value *ucontrol)
  1856. {
  1857. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1858. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1859. return snd_ice1724_put_route_val(ice,
  1860. ucontrol->value.enumerated.item[0],
  1861. analog_route_shift(idx));
  1862. }
  1863. static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1864. struct snd_ctl_elem_value *ucontrol)
  1865. {
  1866. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1867. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1868. ucontrol->value.enumerated.item[0] =
  1869. snd_ice1724_get_route_val(ice, digital_route_shift(idx));
  1870. return 0;
  1871. }
  1872. static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1873. struct snd_ctl_elem_value *ucontrol)
  1874. {
  1875. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1876. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1877. return snd_ice1724_put_route_val(ice,
  1878. ucontrol->value.enumerated.item[0],
  1879. digital_route_shift(idx));
  1880. }
  1881. static const struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
  1882. {
  1883. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1884. .name = "H/W Playback Route",
  1885. .info = snd_vt1724_pro_route_info,
  1886. .get = snd_vt1724_pro_route_analog_get,
  1887. .put = snd_vt1724_pro_route_analog_put,
  1888. };
  1889. static const struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
  1890. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1891. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1892. .info = snd_vt1724_pro_route_info,
  1893. .get = snd_vt1724_pro_route_spdif_get,
  1894. .put = snd_vt1724_pro_route_spdif_put,
  1895. .count = 2,
  1896. };
  1897. static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
  1898. struct snd_ctl_elem_info *uinfo)
  1899. {
  1900. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1901. uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
  1902. uinfo->value.integer.min = 0;
  1903. uinfo->value.integer.max = 255;
  1904. return 0;
  1905. }
  1906. static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
  1907. struct snd_ctl_elem_value *ucontrol)
  1908. {
  1909. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1910. int idx;
  1911. spin_lock_irq(&ice->reg_lock);
  1912. for (idx = 0; idx < 22; idx++) {
  1913. outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
  1914. ucontrol->value.integer.value[idx] =
  1915. inb(ICEMT1724(ice, MONITOR_PEAKDATA));
  1916. }
  1917. spin_unlock_irq(&ice->reg_lock);
  1918. return 0;
  1919. }
  1920. static const struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
  1921. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1922. .name = "Multi Track Peak",
  1923. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1924. .info = snd_vt1724_pro_peak_info,
  1925. .get = snd_vt1724_pro_peak_get
  1926. };
  1927. /*
  1928. *
  1929. */
  1930. static struct snd_ice1712_card_info no_matched;
  1931. /*
  1932. ooAoo cards with no controls
  1933. */
  1934. static unsigned char ooaoo_sq210_eeprom[] = {
  1935. [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
  1936. 1xDACs */
  1937. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  1938. [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
  1939. [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
  1940. [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
  1941. [ICE_EEP2_GPIO_DIR1] = 0x00,
  1942. [ICE_EEP2_GPIO_DIR2] = 0x00,
  1943. [ICE_EEP2_GPIO_MASK] = 0xff,
  1944. [ICE_EEP2_GPIO_MASK1] = 0xff,
  1945. [ICE_EEP2_GPIO_MASK2] = 0xff,
  1946. [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
  1947. [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
  1948. and GPIO15 always zero */
  1949. [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
  1950. };
  1951. static struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
  1952. {
  1953. .name = "ooAoo SQ210a",
  1954. .model = "sq210a",
  1955. .eeprom_size = sizeof(ooaoo_sq210_eeprom),
  1956. .eeprom_data = ooaoo_sq210_eeprom,
  1957. },
  1958. { } /* terminator */
  1959. };
  1960. static struct snd_ice1712_card_info *card_tables[] = {
  1961. snd_vt1724_revo_cards,
  1962. snd_vt1724_amp_cards,
  1963. snd_vt1724_aureon_cards,
  1964. snd_vt1720_mobo_cards,
  1965. snd_vt1720_pontis_cards,
  1966. snd_vt1724_prodigy_hifi_cards,
  1967. snd_vt1724_prodigy192_cards,
  1968. snd_vt1724_juli_cards,
  1969. snd_vt1724_maya44_cards,
  1970. snd_vt1724_phase_cards,
  1971. snd_vt1724_wtm_cards,
  1972. snd_vt1724_se_cards,
  1973. snd_vt1724_qtet_cards,
  1974. snd_vt1724_ooaoo_cards,
  1975. snd_vt1724_psc724_cards,
  1976. NULL,
  1977. };
  1978. /*
  1979. */
  1980. static void wait_i2c_busy(struct snd_ice1712 *ice)
  1981. {
  1982. int t = 0x10000;
  1983. while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
  1984. ;
  1985. if (t == -1)
  1986. dev_err(ice->card->dev, "i2c busy timeout\n");
  1987. }
  1988. unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
  1989. unsigned char dev, unsigned char addr)
  1990. {
  1991. unsigned char val;
  1992. mutex_lock(&ice->i2c_mutex);
  1993. wait_i2c_busy(ice);
  1994. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  1995. outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  1996. wait_i2c_busy(ice);
  1997. val = inb(ICEREG1724(ice, I2C_DATA));
  1998. mutex_unlock(&ice->i2c_mutex);
  1999. /*
  2000. dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
  2001. */
  2002. return val;
  2003. }
  2004. void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
  2005. unsigned char dev, unsigned char addr, unsigned char data)
  2006. {
  2007. mutex_lock(&ice->i2c_mutex);
  2008. wait_i2c_busy(ice);
  2009. /*
  2010. dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
  2011. */
  2012. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  2013. outb(data, ICEREG1724(ice, I2C_DATA));
  2014. outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  2015. wait_i2c_busy(ice);
  2016. mutex_unlock(&ice->i2c_mutex);
  2017. }
  2018. static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
  2019. const char *modelname)
  2020. {
  2021. const int dev = 0xa0; /* EEPROM device address */
  2022. unsigned int i, size;
  2023. struct snd_ice1712_card_info * const *tbl, *c;
  2024. if (!modelname || !*modelname) {
  2025. ice->eeprom.subvendor = 0;
  2026. if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
  2027. ice->eeprom.subvendor =
  2028. (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
  2029. (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
  2030. (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
  2031. (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
  2032. if (ice->eeprom.subvendor == 0 ||
  2033. ice->eeprom.subvendor == (unsigned int)-1) {
  2034. /* invalid subvendor from EEPROM, try the PCI
  2035. * subststem ID instead
  2036. */
  2037. u16 vendor, device;
  2038. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
  2039. &vendor);
  2040. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2041. ice->eeprom.subvendor =
  2042. ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2043. if (ice->eeprom.subvendor == 0 ||
  2044. ice->eeprom.subvendor == (unsigned int)-1) {
  2045. dev_err(ice->card->dev,
  2046. "No valid ID is found\n");
  2047. return -ENXIO;
  2048. }
  2049. }
  2050. }
  2051. for (tbl = card_tables; *tbl; tbl++) {
  2052. for (c = *tbl; c->name; c++) {
  2053. if (modelname && c->model &&
  2054. !strcmp(modelname, c->model)) {
  2055. dev_info(ice->card->dev,
  2056. "Using board model %s\n",
  2057. c->name);
  2058. ice->eeprom.subvendor = c->subvendor;
  2059. } else if (c->subvendor != ice->eeprom.subvendor)
  2060. continue;
  2061. ice->card_info = c;
  2062. if (!c->eeprom_size || !c->eeprom_data)
  2063. goto found;
  2064. /* if the EEPROM is given by the driver, use it */
  2065. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2066. ice->eeprom.version = 2;
  2067. ice->eeprom.size = c->eeprom_size + 6;
  2068. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2069. goto read_skipped;
  2070. }
  2071. }
  2072. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2073. ice->eeprom.subvendor);
  2074. #ifdef CONFIG_PM_SLEEP
  2075. /* assume AC97-only card which can suspend without additional code */
  2076. ice->pm_suspend_enabled = 1;
  2077. #endif
  2078. found:
  2079. ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
  2080. if (ice->eeprom.size < 6)
  2081. ice->eeprom.size = 32;
  2082. else if (ice->eeprom.size > 32) {
  2083. dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
  2084. ice->eeprom.size);
  2085. return -EIO;
  2086. }
  2087. ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
  2088. if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
  2089. dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
  2090. ice->eeprom.version);
  2091. size = ice->eeprom.size - 6;
  2092. for (i = 0; i < size; i++)
  2093. ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
  2094. read_skipped:
  2095. ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
  2096. ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
  2097. ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
  2098. return 0;
  2099. }
  2100. static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
  2101. {
  2102. outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
  2103. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2104. msleep(10);
  2105. outb(0, ICEREG1724(ice, CONTROL));
  2106. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2107. msleep(10);
  2108. }
  2109. static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
  2110. {
  2111. outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
  2112. outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
  2113. outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
  2114. outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
  2115. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2116. ice->gpio.direction = ice->eeprom.gpiodir;
  2117. snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
  2118. snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
  2119. snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
  2120. outb(0, ICEREG1724(ice, POWERDOWN));
  2121. /* MPU_RX and TX irq masks are cleared later dynamically */
  2122. outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
  2123. /* don't handle FIFO overrun/underruns (just yet),
  2124. * since they cause machine lockups
  2125. */
  2126. outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
  2127. return 0;
  2128. }
  2129. static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
  2130. {
  2131. int err;
  2132. struct snd_kcontrol *kctl;
  2133. if (snd_BUG_ON(!ice->pcm))
  2134. return -EIO;
  2135. if (!ice->own_routing) {
  2136. err = snd_ctl_add(ice->card,
  2137. snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
  2138. if (err < 0)
  2139. return err;
  2140. }
  2141. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
  2142. if (err < 0)
  2143. return err;
  2144. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
  2145. if (err < 0)
  2146. return err;
  2147. kctl->id.device = ice->pcm->device;
  2148. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
  2149. if (err < 0)
  2150. return err;
  2151. kctl->id.device = ice->pcm->device;
  2152. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
  2153. if (err < 0)
  2154. return err;
  2155. kctl->id.device = ice->pcm->device;
  2156. #if 0 /* use default only */
  2157. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
  2158. if (err < 0)
  2159. return err;
  2160. kctl->id.device = ice->pcm->device;
  2161. ice->spdif.stream_ctl = kctl;
  2162. #endif
  2163. return 0;
  2164. }
  2165. static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
  2166. {
  2167. int err;
  2168. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
  2169. if (err < 0)
  2170. return err;
  2171. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
  2172. if (err < 0)
  2173. return err;
  2174. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
  2175. if (err < 0)
  2176. return err;
  2177. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
  2178. if (err < 0)
  2179. return err;
  2180. if (!ice->own_routing && ice->num_total_dacs > 0) {
  2181. struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
  2182. tmp.count = ice->num_total_dacs;
  2183. if (ice->vt1720 && tmp.count > 2)
  2184. tmp.count = 2;
  2185. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2186. if (err < 0)
  2187. return err;
  2188. }
  2189. return snd_ctl_add(ice->card,
  2190. snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
  2191. }
  2192. static int snd_vt1724_free(struct snd_ice1712 *ice)
  2193. {
  2194. if (!ice->port)
  2195. goto __hw_end;
  2196. /* mask all interrupts */
  2197. outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
  2198. outb(0xff, ICEREG1724(ice, IRQMASK));
  2199. /* --- */
  2200. __hw_end:
  2201. if (ice->irq >= 0)
  2202. free_irq(ice->irq, ice);
  2203. pci_release_regions(ice->pci);
  2204. snd_ice1712_akm4xxx_free(ice);
  2205. pci_disable_device(ice->pci);
  2206. kfree(ice->spec);
  2207. kfree(ice);
  2208. return 0;
  2209. }
  2210. static int snd_vt1724_dev_free(struct snd_device *device)
  2211. {
  2212. struct snd_ice1712 *ice = device->device_data;
  2213. return snd_vt1724_free(ice);
  2214. }
  2215. static int snd_vt1724_create(struct snd_card *card,
  2216. struct pci_dev *pci,
  2217. const char *modelname,
  2218. struct snd_ice1712 **r_ice1712)
  2219. {
  2220. struct snd_ice1712 *ice;
  2221. int err;
  2222. static struct snd_device_ops ops = {
  2223. .dev_free = snd_vt1724_dev_free,
  2224. };
  2225. *r_ice1712 = NULL;
  2226. /* enable PCI device */
  2227. err = pci_enable_device(pci);
  2228. if (err < 0)
  2229. return err;
  2230. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2231. if (ice == NULL) {
  2232. pci_disable_device(pci);
  2233. return -ENOMEM;
  2234. }
  2235. ice->vt1724 = 1;
  2236. spin_lock_init(&ice->reg_lock);
  2237. mutex_init(&ice->gpio_mutex);
  2238. mutex_init(&ice->open_mutex);
  2239. mutex_init(&ice->i2c_mutex);
  2240. ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
  2241. ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
  2242. ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
  2243. ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
  2244. ice->gpio.set_data = snd_vt1724_set_gpio_data;
  2245. ice->gpio.get_data = snd_vt1724_get_gpio_data;
  2246. ice->card = card;
  2247. ice->pci = pci;
  2248. ice->irq = -1;
  2249. pci_set_master(pci);
  2250. snd_vt1724_proc_init(ice);
  2251. synchronize_irq(pci->irq);
  2252. card->private_data = ice;
  2253. err = pci_request_regions(pci, "ICE1724");
  2254. if (err < 0) {
  2255. kfree(ice);
  2256. pci_disable_device(pci);
  2257. return err;
  2258. }
  2259. ice->port = pci_resource_start(pci, 0);
  2260. ice->profi_port = pci_resource_start(pci, 1);
  2261. if (request_irq(pci->irq, snd_vt1724_interrupt,
  2262. IRQF_SHARED, KBUILD_MODNAME, ice)) {
  2263. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2264. snd_vt1724_free(ice);
  2265. return -EIO;
  2266. }
  2267. ice->irq = pci->irq;
  2268. snd_vt1724_chip_reset(ice);
  2269. if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
  2270. snd_vt1724_free(ice);
  2271. return -EIO;
  2272. }
  2273. if (snd_vt1724_chip_init(ice) < 0) {
  2274. snd_vt1724_free(ice);
  2275. return -EIO;
  2276. }
  2277. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2278. if (err < 0) {
  2279. snd_vt1724_free(ice);
  2280. return err;
  2281. }
  2282. *r_ice1712 = ice;
  2283. return 0;
  2284. }
  2285. /*
  2286. *
  2287. * Registration
  2288. *
  2289. */
  2290. static int snd_vt1724_probe(struct pci_dev *pci,
  2291. const struct pci_device_id *pci_id)
  2292. {
  2293. static int dev;
  2294. struct snd_card *card;
  2295. struct snd_ice1712 *ice;
  2296. int pcm_dev = 0, err;
  2297. struct snd_ice1712_card_info * const *tbl, *c;
  2298. if (dev >= SNDRV_CARDS)
  2299. return -ENODEV;
  2300. if (!enable[dev]) {
  2301. dev++;
  2302. return -ENOENT;
  2303. }
  2304. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2305. 0, &card);
  2306. if (err < 0)
  2307. return err;
  2308. strcpy(card->driver, "ICE1724");
  2309. strcpy(card->shortname, "ICEnsemble ICE1724");
  2310. err = snd_vt1724_create(card, pci, model[dev], &ice);
  2311. if (err < 0) {
  2312. snd_card_free(card);
  2313. return err;
  2314. }
  2315. /* field init before calling chip_init */
  2316. ice->ext_clock_count = 0;
  2317. for (tbl = card_tables; *tbl; tbl++) {
  2318. for (c = *tbl; c->name; c++) {
  2319. if ((model[dev] && c->model &&
  2320. !strcmp(model[dev], c->model)) ||
  2321. (c->subvendor == ice->eeprom.subvendor)) {
  2322. strcpy(card->shortname, c->name);
  2323. if (c->driver) /* specific driver? */
  2324. strcpy(card->driver, c->driver);
  2325. if (c->chip_init) {
  2326. err = c->chip_init(ice);
  2327. if (err < 0) {
  2328. snd_card_free(card);
  2329. return err;
  2330. }
  2331. }
  2332. goto __found;
  2333. }
  2334. }
  2335. }
  2336. c = &no_matched;
  2337. __found:
  2338. /*
  2339. * VT1724 has separate DMAs for the analog and the SPDIF streams while
  2340. * ICE1712 has only one for both (mixed up).
  2341. *
  2342. * Confusingly the analog PCM is named "professional" here because it
  2343. * was called so in ice1712 driver, and vt1724 driver is derived from
  2344. * ice1712 driver.
  2345. */
  2346. ice->pro_rate_default = PRO_RATE_DEFAULT;
  2347. if (!ice->is_spdif_master)
  2348. ice->is_spdif_master = stdclock_is_spdif_master;
  2349. if (!ice->get_rate)
  2350. ice->get_rate = stdclock_get_rate;
  2351. if (!ice->set_rate)
  2352. ice->set_rate = stdclock_set_rate;
  2353. if (!ice->set_mclk)
  2354. ice->set_mclk = stdclock_set_mclk;
  2355. if (!ice->set_spdif_clock)
  2356. ice->set_spdif_clock = stdclock_set_spdif_clock;
  2357. if (!ice->get_spdif_master_type)
  2358. ice->get_spdif_master_type = stdclock_get_spdif_master_type;
  2359. if (!ice->ext_clock_names)
  2360. ice->ext_clock_names = ext_clock_names;
  2361. if (!ice->ext_clock_count)
  2362. ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
  2363. if (!ice->hw_rates)
  2364. set_std_hw_rates(ice);
  2365. err = snd_vt1724_pcm_profi(ice, pcm_dev++);
  2366. if (err < 0) {
  2367. snd_card_free(card);
  2368. return err;
  2369. }
  2370. err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
  2371. if (err < 0) {
  2372. snd_card_free(card);
  2373. return err;
  2374. }
  2375. err = snd_vt1724_pcm_indep(ice, pcm_dev++);
  2376. if (err < 0) {
  2377. snd_card_free(card);
  2378. return err;
  2379. }
  2380. err = snd_vt1724_ac97_mixer(ice);
  2381. if (err < 0) {
  2382. snd_card_free(card);
  2383. return err;
  2384. }
  2385. err = snd_vt1724_build_controls(ice);
  2386. if (err < 0) {
  2387. snd_card_free(card);
  2388. return err;
  2389. }
  2390. if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
  2391. err = snd_vt1724_spdif_build_controls(ice);
  2392. if (err < 0) {
  2393. snd_card_free(card);
  2394. return err;
  2395. }
  2396. }
  2397. if (c->build_controls) {
  2398. err = c->build_controls(ice);
  2399. if (err < 0) {
  2400. snd_card_free(card);
  2401. return err;
  2402. }
  2403. }
  2404. if (!c->no_mpu401) {
  2405. if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
  2406. struct snd_rawmidi *rmidi;
  2407. err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
  2408. if (err < 0) {
  2409. snd_card_free(card);
  2410. return err;
  2411. }
  2412. ice->rmidi[0] = rmidi;
  2413. rmidi->private_data = ice;
  2414. strcpy(rmidi->name, "ICE1724 MIDI");
  2415. rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
  2416. SNDRV_RAWMIDI_INFO_INPUT |
  2417. SNDRV_RAWMIDI_INFO_DUPLEX;
  2418. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
  2419. &vt1724_midi_output_ops);
  2420. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
  2421. &vt1724_midi_input_ops);
  2422. /* set watermarks */
  2423. outb(VT1724_MPU_RX_FIFO | 0x1,
  2424. ICEREG1724(ice, MPU_FIFO_WM));
  2425. outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
  2426. /* set UART mode */
  2427. outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
  2428. }
  2429. }
  2430. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2431. card->shortname, ice->port, ice->irq);
  2432. err = snd_card_register(card);
  2433. if (err < 0) {
  2434. snd_card_free(card);
  2435. return err;
  2436. }
  2437. pci_set_drvdata(pci, card);
  2438. dev++;
  2439. return 0;
  2440. }
  2441. static void snd_vt1724_remove(struct pci_dev *pci)
  2442. {
  2443. struct snd_card *card = pci_get_drvdata(pci);
  2444. struct snd_ice1712 *ice = card->private_data;
  2445. if (ice->card_info && ice->card_info->chip_exit)
  2446. ice->card_info->chip_exit(ice);
  2447. snd_card_free(card);
  2448. }
  2449. #ifdef CONFIG_PM_SLEEP
  2450. static int snd_vt1724_suspend(struct device *dev)
  2451. {
  2452. struct snd_card *card = dev_get_drvdata(dev);
  2453. struct snd_ice1712 *ice = card->private_data;
  2454. if (!ice->pm_suspend_enabled)
  2455. return 0;
  2456. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2457. snd_pcm_suspend_all(ice->pcm);
  2458. snd_pcm_suspend_all(ice->pcm_pro);
  2459. snd_pcm_suspend_all(ice->pcm_ds);
  2460. snd_ac97_suspend(ice->ac97);
  2461. spin_lock_irq(&ice->reg_lock);
  2462. ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
  2463. ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
  2464. ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
  2465. ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  2466. spin_unlock_irq(&ice->reg_lock);
  2467. if (ice->pm_suspend)
  2468. ice->pm_suspend(ice);
  2469. return 0;
  2470. }
  2471. static int snd_vt1724_resume(struct device *dev)
  2472. {
  2473. struct snd_card *card = dev_get_drvdata(dev);
  2474. struct snd_ice1712 *ice = card->private_data;
  2475. if (!ice->pm_suspend_enabled)
  2476. return 0;
  2477. snd_vt1724_chip_reset(ice);
  2478. if (snd_vt1724_chip_init(ice) < 0) {
  2479. snd_card_disconnect(card);
  2480. return -EIO;
  2481. }
  2482. if (ice->pm_resume)
  2483. ice->pm_resume(ice);
  2484. if (ice->pm_saved_is_spdif_master) {
  2485. /* switching to external clock via SPDIF */
  2486. ice->set_spdif_clock(ice, 0);
  2487. } else {
  2488. /* internal on-card clock */
  2489. int rate;
  2490. if (ice->cur_rate)
  2491. rate = ice->cur_rate;
  2492. else
  2493. rate = ice->pro_rate_default;
  2494. snd_vt1724_set_pro_rate(ice, rate, 1);
  2495. }
  2496. update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
  2497. outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
  2498. outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
  2499. snd_ac97_resume(ice->ac97);
  2500. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2501. return 0;
  2502. }
  2503. static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
  2504. #define SND_VT1724_PM_OPS &snd_vt1724_pm
  2505. #else
  2506. #define SND_VT1724_PM_OPS NULL
  2507. #endif /* CONFIG_PM_SLEEP */
  2508. static struct pci_driver vt1724_driver = {
  2509. .name = KBUILD_MODNAME,
  2510. .id_table = snd_vt1724_ids,
  2511. .probe = snd_vt1724_probe,
  2512. .remove = snd_vt1724_remove,
  2513. .driver = {
  2514. .pm = SND_VT1724_PM_OPS,
  2515. },
  2516. };
  2517. module_pci_driver(vt1724_driver);