als4000.c 31 KB

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  1. /*
  2. * card-als4000.c - driver for Avance Logic ALS4000 based soundcards.
  3. * Copyright (C) 2000 by Bart Hartgers <bart@etpmod.phys.tue.nl>,
  4. * Jaroslav Kysela <perex@perex.cz>
  5. * Copyright (C) 2002, 2008 by Andreas Mohr <hw7oshyuv3001@sneakemail.com>
  6. *
  7. * Framework borrowed from Massimo Piccioni's card-als100.c.
  8. *
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. * NOTES
  24. *
  25. * Since Avance does not provide any meaningful documentation, and I
  26. * bought an ALS4000 based soundcard, I was forced to base this driver
  27. * on reverse engineering.
  28. *
  29. * Note: this is no longer true (thank you!):
  30. * pretty verbose chip docu (ALS4000a.PDF) can be found on the ALSA web site.
  31. * Page numbers stated anywhere below with the "SPECS_PAGE:" tag
  32. * refer to: ALS4000a.PDF specs Ver 1.0, May 28th, 1998.
  33. *
  34. * The ALS4000 seems to be the PCI-cousin of the ALS100. It contains an
  35. * ALS100-like SB DSP/mixer, an OPL3 synth, a MPU401 and a gameport
  36. * interface. These subsystems can be mapped into ISA io-port space,
  37. * using the PCI-interface. In addition, the PCI-bit provides DMA and IRQ
  38. * services to the subsystems.
  39. *
  40. * While ALS4000 is very similar to a SoundBlaster, the differences in
  41. * DMA and capturing require more changes to the SoundBlaster than
  42. * desirable, so I made this separate driver.
  43. *
  44. * The ALS4000 can do real full duplex playback/capture.
  45. *
  46. * FMDAC:
  47. * - 0x4f -> port 0x14
  48. * - port 0x15 |= 1
  49. *
  50. * Enable/disable 3D sound:
  51. * - 0x50 -> port 0x14
  52. * - change bit 6 (0x40) of port 0x15
  53. *
  54. * Set QSound:
  55. * - 0xdb -> port 0x14
  56. * - set port 0x15:
  57. * 0x3e (mode 3), 0x3c (mode 2), 0x3a (mode 1), 0x38 (mode 0)
  58. *
  59. * Set KSound:
  60. * - value -> some port 0x0c0d
  61. *
  62. * ToDo:
  63. * - by default, don't enable legacy game and use PCI game I/O
  64. * - power management? (card can do voice wakeup according to datasheet!!)
  65. */
  66. #include <linux/io.h>
  67. #include <linux/init.h>
  68. #include <linux/pci.h>
  69. #include <linux/gameport.h>
  70. #include <linux/module.h>
  71. #include <linux/dma-mapping.h>
  72. #include <sound/core.h>
  73. #include <sound/pcm.h>
  74. #include <sound/rawmidi.h>
  75. #include <sound/mpu401.h>
  76. #include <sound/opl3.h>
  77. #include <sound/sb.h>
  78. #include <sound/initval.h>
  79. MODULE_AUTHOR("Bart Hartgers <bart@etpmod.phys.tue.nl>, Andreas Mohr");
  80. MODULE_DESCRIPTION("Avance Logic ALS4000");
  81. MODULE_LICENSE("GPL");
  82. MODULE_SUPPORTED_DEVICE("{{Avance Logic,ALS4000}}");
  83. #if IS_REACHABLE(CONFIG_GAMEPORT)
  84. #define SUPPORT_JOYSTICK 1
  85. #endif
  86. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  87. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  88. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  89. #ifdef SUPPORT_JOYSTICK
  90. static int joystick_port[SNDRV_CARDS];
  91. #endif
  92. module_param_array(index, int, NULL, 0444);
  93. MODULE_PARM_DESC(index, "Index value for ALS4000 soundcard.");
  94. module_param_array(id, charp, NULL, 0444);
  95. MODULE_PARM_DESC(id, "ID string for ALS4000 soundcard.");
  96. module_param_array(enable, bool, NULL, 0444);
  97. MODULE_PARM_DESC(enable, "Enable ALS4000 soundcard.");
  98. #ifdef SUPPORT_JOYSTICK
  99. module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  100. MODULE_PARM_DESC(joystick_port, "Joystick port address for ALS4000 soundcard. (0 = disabled)");
  101. #endif
  102. struct snd_card_als4000 {
  103. /* most frequent access first */
  104. unsigned long iobase;
  105. struct pci_dev *pci;
  106. struct snd_sb *chip;
  107. #ifdef SUPPORT_JOYSTICK
  108. struct gameport *gameport;
  109. #endif
  110. };
  111. static const struct pci_device_id snd_als4000_ids[] = {
  112. { 0x4005, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ALS4000 */
  113. { 0, }
  114. };
  115. MODULE_DEVICE_TABLE(pci, snd_als4000_ids);
  116. enum als4k_iobase_t {
  117. /* IOx: B == Byte, W = Word, D = DWord; SPECS_PAGE: 37 */
  118. ALS4K_IOD_00_AC97_ACCESS = 0x00,
  119. ALS4K_IOW_04_AC97_READ = 0x04,
  120. ALS4K_IOB_06_AC97_STATUS = 0x06,
  121. ALS4K_IOB_07_IRQSTATUS = 0x07,
  122. ALS4K_IOD_08_GCR_DATA = 0x08,
  123. ALS4K_IOB_0C_GCR_INDEX = 0x0c,
  124. ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU = 0x0e,
  125. ALS4K_IOB_10_ADLIB_ADDR0 = 0x10,
  126. ALS4K_IOB_11_ADLIB_ADDR1 = 0x11,
  127. ALS4K_IOB_12_ADLIB_ADDR2 = 0x12,
  128. ALS4K_IOB_13_ADLIB_ADDR3 = 0x13,
  129. ALS4K_IOB_14_MIXER_INDEX = 0x14,
  130. ALS4K_IOB_15_MIXER_DATA = 0x15,
  131. ALS4K_IOB_16_ESP_RESET = 0x16,
  132. ALS4K_IOB_16_ACK_FOR_CR1E = 0x16, /* 2nd function */
  133. ALS4K_IOB_18_OPL_ADDR0 = 0x18,
  134. ALS4K_IOB_19_OPL_ADDR1 = 0x19,
  135. ALS4K_IOB_1A_ESP_RD_DATA = 0x1a,
  136. ALS4K_IOB_1C_ESP_CMD_DATA = 0x1c,
  137. ALS4K_IOB_1C_ESP_WR_STATUS = 0x1c, /* 2nd function */
  138. ALS4K_IOB_1E_ESP_RD_STATUS8 = 0x1e,
  139. ALS4K_IOB_1F_ESP_RD_STATUS16 = 0x1f,
  140. ALS4K_IOB_20_ESP_GAMEPORT_200 = 0x20,
  141. ALS4K_IOB_21_ESP_GAMEPORT_201 = 0x21,
  142. ALS4K_IOB_30_MIDI_DATA = 0x30,
  143. ALS4K_IOB_31_MIDI_STATUS = 0x31,
  144. ALS4K_IOB_31_MIDI_COMMAND = 0x31, /* 2nd function */
  145. };
  146. enum als4k_iobase_0e_t {
  147. ALS4K_IOB_0E_MPU_IRQ = 0x10,
  148. ALS4K_IOB_0E_CR1E_IRQ = 0x40,
  149. ALS4K_IOB_0E_SB_DMA_IRQ = 0x80,
  150. };
  151. enum als4k_gcr_t { /* all registers 32bit wide; SPECS_PAGE: 38 to 42 */
  152. ALS4K_GCR8C_MISC_CTRL = 0x8c,
  153. ALS4K_GCR90_TEST_MODE_REG = 0x90,
  154. ALS4K_GCR91_DMA0_ADDR = 0x91,
  155. ALS4K_GCR92_DMA0_MODE_COUNT = 0x92,
  156. ALS4K_GCR93_DMA1_ADDR = 0x93,
  157. ALS4K_GCR94_DMA1_MODE_COUNT = 0x94,
  158. ALS4K_GCR95_DMA3_ADDR = 0x95,
  159. ALS4K_GCR96_DMA3_MODE_COUNT = 0x96,
  160. ALS4K_GCR99_DMA_EMULATION_CTRL = 0x99,
  161. ALS4K_GCRA0_FIFO1_CURRENT_ADDR = 0xa0,
  162. ALS4K_GCRA1_FIFO1_STATUS_BYTECOUNT = 0xa1,
  163. ALS4K_GCRA2_FIFO2_PCIADDR = 0xa2,
  164. ALS4K_GCRA3_FIFO2_COUNT = 0xa3,
  165. ALS4K_GCRA4_FIFO2_CURRENT_ADDR = 0xa4,
  166. ALS4K_GCRA5_FIFO1_STATUS_BYTECOUNT = 0xa5,
  167. ALS4K_GCRA6_PM_CTRL = 0xa6,
  168. ALS4K_GCRA7_PCI_ACCESS_STORAGE = 0xa7,
  169. ALS4K_GCRA8_LEGACY_CFG1 = 0xa8,
  170. ALS4K_GCRA9_LEGACY_CFG2 = 0xa9,
  171. ALS4K_GCRFF_DUMMY_SCRATCH = 0xff,
  172. };
  173. enum als4k_gcr8c_t {
  174. ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE = 0x8000,
  175. ALS4K_GCR8C_CHIP_REV_MASK = 0xf0000
  176. };
  177. static inline void snd_als4k_iobase_writeb(unsigned long iobase,
  178. enum als4k_iobase_t reg,
  179. u8 val)
  180. {
  181. outb(val, iobase + reg);
  182. }
  183. static inline void snd_als4k_iobase_writel(unsigned long iobase,
  184. enum als4k_iobase_t reg,
  185. u32 val)
  186. {
  187. outl(val, iobase + reg);
  188. }
  189. static inline u8 snd_als4k_iobase_readb(unsigned long iobase,
  190. enum als4k_iobase_t reg)
  191. {
  192. return inb(iobase + reg);
  193. }
  194. static inline u32 snd_als4k_iobase_readl(unsigned long iobase,
  195. enum als4k_iobase_t reg)
  196. {
  197. return inl(iobase + reg);
  198. }
  199. static inline void snd_als4k_gcr_write_addr(unsigned long iobase,
  200. enum als4k_gcr_t reg,
  201. u32 val)
  202. {
  203. snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg);
  204. snd_als4k_iobase_writel(iobase, ALS4K_IOD_08_GCR_DATA, val);
  205. }
  206. static inline void snd_als4k_gcr_write(struct snd_sb *sb,
  207. enum als4k_gcr_t reg,
  208. u32 val)
  209. {
  210. snd_als4k_gcr_write_addr(sb->alt_port, reg, val);
  211. }
  212. static inline u32 snd_als4k_gcr_read_addr(unsigned long iobase,
  213. enum als4k_gcr_t reg)
  214. {
  215. /* SPECS_PAGE: 37/38 */
  216. snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg);
  217. return snd_als4k_iobase_readl(iobase, ALS4K_IOD_08_GCR_DATA);
  218. }
  219. static inline u32 snd_als4k_gcr_read(struct snd_sb *sb, enum als4k_gcr_t reg)
  220. {
  221. return snd_als4k_gcr_read_addr(sb->alt_port, reg);
  222. }
  223. enum als4k_cr_t { /* all registers 8bit wide; SPECS_PAGE: 20 to 23 */
  224. ALS4K_CR0_SB_CONFIG = 0x00,
  225. ALS4K_CR2_MISC_CONTROL = 0x02,
  226. ALS4K_CR3_CONFIGURATION = 0x03,
  227. ALS4K_CR17_FIFO_STATUS = 0x17,
  228. ALS4K_CR18_ESP_MAJOR_VERSION = 0x18,
  229. ALS4K_CR19_ESP_MINOR_VERSION = 0x19,
  230. ALS4K_CR1A_MPU401_UART_MODE_CONTROL = 0x1a,
  231. ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO = 0x1c,
  232. ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI = 0x1d,
  233. ALS4K_CR1E_FIFO2_CONTROL = 0x1e, /* secondary PCM FIFO (recording) */
  234. ALS4K_CR3A_MISC_CONTROL = 0x3a,
  235. ALS4K_CR3B_CRC32_BYTE0 = 0x3b, /* for testing, activate via CR3A */
  236. ALS4K_CR3C_CRC32_BYTE1 = 0x3c,
  237. ALS4K_CR3D_CRC32_BYTE2 = 0x3d,
  238. ALS4K_CR3E_CRC32_BYTE3 = 0x3e,
  239. };
  240. enum als4k_cr0_t {
  241. ALS4K_CR0_DMA_CONTIN_MODE_CTRL = 0x02, /* IRQ/FIFO controlled for 0/1 */
  242. ALS4K_CR0_DMA_90H_MODE_CTRL = 0x04, /* IRQ/FIFO controlled for 0/1 */
  243. ALS4K_CR0_MX80_81_REG_WRITE_ENABLE = 0x80,
  244. };
  245. static inline void snd_als4_cr_write(struct snd_sb *chip,
  246. enum als4k_cr_t reg,
  247. u8 data)
  248. {
  249. /* Control Register is reg | 0xc0 (bit 7, 6 set) on sbmixer_index
  250. * NOTE: assumes chip->mixer_lock to be locked externally already!
  251. * SPECS_PAGE: 6 */
  252. snd_sbmixer_write(chip, reg | 0xc0, data);
  253. }
  254. static inline u8 snd_als4_cr_read(struct snd_sb *chip,
  255. enum als4k_cr_t reg)
  256. {
  257. /* NOTE: assumes chip->mixer_lock to be locked externally already! */
  258. return snd_sbmixer_read(chip, reg | 0xc0);
  259. }
  260. static void snd_als4000_set_rate(struct snd_sb *chip, unsigned int rate)
  261. {
  262. if (!(chip->mode & SB_RATE_LOCK)) {
  263. snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE_OUT);
  264. snd_sbdsp_command(chip, rate>>8);
  265. snd_sbdsp_command(chip, rate);
  266. }
  267. }
  268. static inline void snd_als4000_set_capture_dma(struct snd_sb *chip,
  269. dma_addr_t addr, unsigned size)
  270. {
  271. /* SPECS_PAGE: 40 */
  272. snd_als4k_gcr_write(chip, ALS4K_GCRA2_FIFO2_PCIADDR, addr);
  273. snd_als4k_gcr_write(chip, ALS4K_GCRA3_FIFO2_COUNT, (size-1));
  274. }
  275. static inline void snd_als4000_set_playback_dma(struct snd_sb *chip,
  276. dma_addr_t addr,
  277. unsigned size)
  278. {
  279. /* SPECS_PAGE: 38 */
  280. snd_als4k_gcr_write(chip, ALS4K_GCR91_DMA0_ADDR, addr);
  281. snd_als4k_gcr_write(chip, ALS4K_GCR92_DMA0_MODE_COUNT,
  282. (size-1)|0x180000);
  283. }
  284. #define ALS4000_FORMAT_SIGNED (1<<0)
  285. #define ALS4000_FORMAT_16BIT (1<<1)
  286. #define ALS4000_FORMAT_STEREO (1<<2)
  287. static int snd_als4000_get_format(struct snd_pcm_runtime *runtime)
  288. {
  289. int result;
  290. result = 0;
  291. if (snd_pcm_format_signed(runtime->format))
  292. result |= ALS4000_FORMAT_SIGNED;
  293. if (snd_pcm_format_physical_width(runtime->format) == 16)
  294. result |= ALS4000_FORMAT_16BIT;
  295. if (runtime->channels > 1)
  296. result |= ALS4000_FORMAT_STEREO;
  297. return result;
  298. }
  299. /* structure for setting up playback */
  300. static const struct {
  301. unsigned char dsp_cmd, dma_on, dma_off, format;
  302. } playback_cmd_vals[]={
  303. /* ALS4000_FORMAT_U8_MONO */
  304. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_MONO },
  305. /* ALS4000_FORMAT_S8_MONO */
  306. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_MONO },
  307. /* ALS4000_FORMAT_U16L_MONO */
  308. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_MONO },
  309. /* ALS4000_FORMAT_S16L_MONO */
  310. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_MONO },
  311. /* ALS4000_FORMAT_U8_STEREO */
  312. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_STEREO },
  313. /* ALS4000_FORMAT_S8_STEREO */
  314. { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_STEREO },
  315. /* ALS4000_FORMAT_U16L_STEREO */
  316. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_STEREO },
  317. /* ALS4000_FORMAT_S16L_STEREO */
  318. { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_STEREO },
  319. };
  320. #define playback_cmd(chip) (playback_cmd_vals[(chip)->playback_format])
  321. /* structure for setting up capture */
  322. enum { CMD_WIDTH8=0x04, CMD_SIGNED=0x10, CMD_MONO=0x80, CMD_STEREO=0xA0 };
  323. static const unsigned char capture_cmd_vals[]=
  324. {
  325. CMD_WIDTH8|CMD_MONO, /* ALS4000_FORMAT_U8_MONO */
  326. CMD_WIDTH8|CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S8_MONO */
  327. CMD_MONO, /* ALS4000_FORMAT_U16L_MONO */
  328. CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S16L_MONO */
  329. CMD_WIDTH8|CMD_STEREO, /* ALS4000_FORMAT_U8_STEREO */
  330. CMD_WIDTH8|CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S8_STEREO */
  331. CMD_STEREO, /* ALS4000_FORMAT_U16L_STEREO */
  332. CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S16L_STEREO */
  333. };
  334. #define capture_cmd(chip) (capture_cmd_vals[(chip)->capture_format])
  335. static int snd_als4000_hw_params(struct snd_pcm_substream *substream,
  336. struct snd_pcm_hw_params *hw_params)
  337. {
  338. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  339. }
  340. static int snd_als4000_hw_free(struct snd_pcm_substream *substream)
  341. {
  342. snd_pcm_lib_free_pages(substream);
  343. return 0;
  344. }
  345. static int snd_als4000_capture_prepare(struct snd_pcm_substream *substream)
  346. {
  347. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  348. struct snd_pcm_runtime *runtime = substream->runtime;
  349. unsigned long size;
  350. unsigned count;
  351. chip->capture_format = snd_als4000_get_format(runtime);
  352. size = snd_pcm_lib_buffer_bytes(substream);
  353. count = snd_pcm_lib_period_bytes(substream);
  354. if (chip->capture_format & ALS4000_FORMAT_16BIT)
  355. count >>= 1;
  356. count--;
  357. spin_lock_irq(&chip->reg_lock);
  358. snd_als4000_set_rate(chip, runtime->rate);
  359. snd_als4000_set_capture_dma(chip, runtime->dma_addr, size);
  360. spin_unlock_irq(&chip->reg_lock);
  361. spin_lock_irq(&chip->mixer_lock);
  362. snd_als4_cr_write(chip, ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO, count & 0xff);
  363. snd_als4_cr_write(chip, ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI, count >> 8);
  364. spin_unlock_irq(&chip->mixer_lock);
  365. return 0;
  366. }
  367. static int snd_als4000_playback_prepare(struct snd_pcm_substream *substream)
  368. {
  369. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  370. struct snd_pcm_runtime *runtime = substream->runtime;
  371. unsigned long size;
  372. unsigned count;
  373. chip->playback_format = snd_als4000_get_format(runtime);
  374. size = snd_pcm_lib_buffer_bytes(substream);
  375. count = snd_pcm_lib_period_bytes(substream);
  376. if (chip->playback_format & ALS4000_FORMAT_16BIT)
  377. count >>= 1;
  378. count--;
  379. /* FIXME: from second playback on, there's a lot more clicks and pops
  380. * involved here than on first playback. Fiddling with
  381. * tons of different settings didn't help (DMA, speaker on/off,
  382. * reordering, ...). Something seems to get enabled on playback
  383. * that I haven't found out how to disable again, which then causes
  384. * the switching pops to reach the speakers the next time here. */
  385. spin_lock_irq(&chip->reg_lock);
  386. snd_als4000_set_rate(chip, runtime->rate);
  387. snd_als4000_set_playback_dma(chip, runtime->dma_addr, size);
  388. /* SPEAKER_ON not needed, since dma_on seems to also enable speaker */
  389. /* snd_sbdsp_command(chip, SB_DSP_SPEAKER_ON); */
  390. snd_sbdsp_command(chip, playback_cmd(chip).dsp_cmd);
  391. snd_sbdsp_command(chip, playback_cmd(chip).format);
  392. snd_sbdsp_command(chip, count & 0xff);
  393. snd_sbdsp_command(chip, count >> 8);
  394. snd_sbdsp_command(chip, playback_cmd(chip).dma_off);
  395. spin_unlock_irq(&chip->reg_lock);
  396. return 0;
  397. }
  398. static int snd_als4000_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  399. {
  400. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  401. int result = 0;
  402. /* FIXME race condition in here!!!
  403. chip->mode non-atomic update gets consistently protected
  404. by reg_lock always, _except_ for this place!!
  405. Probably need to take reg_lock as outer (or inner??) lock, too.
  406. (or serialize both lock operations? probably not, though... - racy?)
  407. */
  408. spin_lock(&chip->mixer_lock);
  409. switch (cmd) {
  410. case SNDRV_PCM_TRIGGER_START:
  411. case SNDRV_PCM_TRIGGER_RESUME:
  412. chip->mode |= SB_RATE_LOCK_CAPTURE;
  413. snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL,
  414. capture_cmd(chip));
  415. break;
  416. case SNDRV_PCM_TRIGGER_STOP:
  417. case SNDRV_PCM_TRIGGER_SUSPEND:
  418. chip->mode &= ~SB_RATE_LOCK_CAPTURE;
  419. snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL,
  420. capture_cmd(chip));
  421. break;
  422. default:
  423. result = -EINVAL;
  424. break;
  425. }
  426. spin_unlock(&chip->mixer_lock);
  427. return result;
  428. }
  429. static int snd_als4000_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  430. {
  431. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  432. int result = 0;
  433. spin_lock(&chip->reg_lock);
  434. switch (cmd) {
  435. case SNDRV_PCM_TRIGGER_START:
  436. case SNDRV_PCM_TRIGGER_RESUME:
  437. chip->mode |= SB_RATE_LOCK_PLAYBACK;
  438. snd_sbdsp_command(chip, playback_cmd(chip).dma_on);
  439. break;
  440. case SNDRV_PCM_TRIGGER_STOP:
  441. case SNDRV_PCM_TRIGGER_SUSPEND:
  442. snd_sbdsp_command(chip, playback_cmd(chip).dma_off);
  443. chip->mode &= ~SB_RATE_LOCK_PLAYBACK;
  444. break;
  445. default:
  446. result = -EINVAL;
  447. break;
  448. }
  449. spin_unlock(&chip->reg_lock);
  450. return result;
  451. }
  452. static snd_pcm_uframes_t snd_als4000_capture_pointer(struct snd_pcm_substream *substream)
  453. {
  454. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  455. unsigned int result;
  456. spin_lock(&chip->reg_lock);
  457. result = snd_als4k_gcr_read(chip, ALS4K_GCRA4_FIFO2_CURRENT_ADDR);
  458. spin_unlock(&chip->reg_lock);
  459. result &= 0xffff;
  460. return bytes_to_frames( substream->runtime, result );
  461. }
  462. static snd_pcm_uframes_t snd_als4000_playback_pointer(struct snd_pcm_substream *substream)
  463. {
  464. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  465. unsigned result;
  466. spin_lock(&chip->reg_lock);
  467. result = snd_als4k_gcr_read(chip, ALS4K_GCRA0_FIFO1_CURRENT_ADDR);
  468. spin_unlock(&chip->reg_lock);
  469. result &= 0xffff;
  470. return bytes_to_frames( substream->runtime, result );
  471. }
  472. /* FIXME: this IRQ routine doesn't really support IRQ sharing (we always
  473. * return IRQ_HANDLED no matter whether we actually had an IRQ flag or not).
  474. * ALS4000a.PDF writes that while ACKing IRQ in PCI block will *not* ACK
  475. * the IRQ in the SB core, ACKing IRQ in SB block *will* ACK the PCI IRQ
  476. * register (alt_port + ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU). Probably something
  477. * could be optimized here to query/write one register only...
  478. * And even if both registers need to be queried, then there's still the
  479. * question of whether it's actually correct to ACK PCI IRQ before reading
  480. * SB IRQ like we do now, since ALS4000a.PDF mentions that PCI IRQ will *clear*
  481. * SB IRQ status.
  482. * (hmm, SPECS_PAGE: 38 mentions it the other way around!)
  483. * And do we *really* need the lock here for *reading* SB_DSP4_IRQSTATUS??
  484. * */
  485. static irqreturn_t snd_als4000_interrupt(int irq, void *dev_id)
  486. {
  487. struct snd_sb *chip = dev_id;
  488. unsigned pci_irqstatus;
  489. unsigned sb_irqstatus;
  490. /* find out which bit of the ALS4000 PCI block produced the interrupt,
  491. SPECS_PAGE: 38, 5 */
  492. pci_irqstatus = snd_als4k_iobase_readb(chip->alt_port,
  493. ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU);
  494. if ((pci_irqstatus & ALS4K_IOB_0E_SB_DMA_IRQ)
  495. && (chip->playback_substream)) /* playback */
  496. snd_pcm_period_elapsed(chip->playback_substream);
  497. if ((pci_irqstatus & ALS4K_IOB_0E_CR1E_IRQ)
  498. && (chip->capture_substream)) /* capturing */
  499. snd_pcm_period_elapsed(chip->capture_substream);
  500. if ((pci_irqstatus & ALS4K_IOB_0E_MPU_IRQ)
  501. && (chip->rmidi)) /* MPU401 interrupt */
  502. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  503. /* ACK the PCI block IRQ */
  504. snd_als4k_iobase_writeb(chip->alt_port,
  505. ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU, pci_irqstatus);
  506. spin_lock(&chip->mixer_lock);
  507. /* SPECS_PAGE: 20 */
  508. sb_irqstatus = snd_sbmixer_read(chip, SB_DSP4_IRQSTATUS);
  509. spin_unlock(&chip->mixer_lock);
  510. if (sb_irqstatus & SB_IRQTYPE_8BIT)
  511. snd_sb_ack_8bit(chip);
  512. if (sb_irqstatus & SB_IRQTYPE_16BIT)
  513. snd_sb_ack_16bit(chip);
  514. if (sb_irqstatus & SB_IRQTYPE_MPUIN)
  515. inb(chip->mpu_port);
  516. if (sb_irqstatus & ALS4K_IRQTYPE_CR1E_DMA)
  517. snd_als4k_iobase_readb(chip->alt_port,
  518. ALS4K_IOB_16_ACK_FOR_CR1E);
  519. /* dev_dbg(chip->card->dev, "als4000: irq 0x%04x 0x%04x\n",
  520. pci_irqstatus, sb_irqstatus); */
  521. /* only ack the things we actually handled above */
  522. return IRQ_RETVAL(
  523. (pci_irqstatus & (ALS4K_IOB_0E_SB_DMA_IRQ|ALS4K_IOB_0E_CR1E_IRQ|
  524. ALS4K_IOB_0E_MPU_IRQ))
  525. || (sb_irqstatus & (SB_IRQTYPE_8BIT|SB_IRQTYPE_16BIT|
  526. SB_IRQTYPE_MPUIN|ALS4K_IRQTYPE_CR1E_DMA))
  527. );
  528. }
  529. /*****************************************************************/
  530. static const struct snd_pcm_hardware snd_als4000_playback =
  531. {
  532. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  533. SNDRV_PCM_INFO_MMAP_VALID),
  534. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
  535. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */
  536. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  537. .rate_min = 4000,
  538. .rate_max = 48000,
  539. .channels_min = 1,
  540. .channels_max = 2,
  541. .buffer_bytes_max = 65536,
  542. .period_bytes_min = 64,
  543. .period_bytes_max = 65536,
  544. .periods_min = 1,
  545. .periods_max = 1024,
  546. .fifo_size = 0
  547. };
  548. static const struct snd_pcm_hardware snd_als4000_capture =
  549. {
  550. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  551. SNDRV_PCM_INFO_MMAP_VALID),
  552. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
  553. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */
  554. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  555. .rate_min = 4000,
  556. .rate_max = 48000,
  557. .channels_min = 1,
  558. .channels_max = 2,
  559. .buffer_bytes_max = 65536,
  560. .period_bytes_min = 64,
  561. .period_bytes_max = 65536,
  562. .periods_min = 1,
  563. .periods_max = 1024,
  564. .fifo_size = 0
  565. };
  566. /*****************************************************************/
  567. static int snd_als4000_playback_open(struct snd_pcm_substream *substream)
  568. {
  569. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  570. struct snd_pcm_runtime *runtime = substream->runtime;
  571. chip->playback_substream = substream;
  572. runtime->hw = snd_als4000_playback;
  573. return 0;
  574. }
  575. static int snd_als4000_playback_close(struct snd_pcm_substream *substream)
  576. {
  577. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  578. chip->playback_substream = NULL;
  579. snd_pcm_lib_free_pages(substream);
  580. return 0;
  581. }
  582. static int snd_als4000_capture_open(struct snd_pcm_substream *substream)
  583. {
  584. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  585. struct snd_pcm_runtime *runtime = substream->runtime;
  586. chip->capture_substream = substream;
  587. runtime->hw = snd_als4000_capture;
  588. return 0;
  589. }
  590. static int snd_als4000_capture_close(struct snd_pcm_substream *substream)
  591. {
  592. struct snd_sb *chip = snd_pcm_substream_chip(substream);
  593. chip->capture_substream = NULL;
  594. snd_pcm_lib_free_pages(substream);
  595. return 0;
  596. }
  597. /******************************************************************/
  598. static const struct snd_pcm_ops snd_als4000_playback_ops = {
  599. .open = snd_als4000_playback_open,
  600. .close = snd_als4000_playback_close,
  601. .ioctl = snd_pcm_lib_ioctl,
  602. .hw_params = snd_als4000_hw_params,
  603. .hw_free = snd_als4000_hw_free,
  604. .prepare = snd_als4000_playback_prepare,
  605. .trigger = snd_als4000_playback_trigger,
  606. .pointer = snd_als4000_playback_pointer
  607. };
  608. static const struct snd_pcm_ops snd_als4000_capture_ops = {
  609. .open = snd_als4000_capture_open,
  610. .close = snd_als4000_capture_close,
  611. .ioctl = snd_pcm_lib_ioctl,
  612. .hw_params = snd_als4000_hw_params,
  613. .hw_free = snd_als4000_hw_free,
  614. .prepare = snd_als4000_capture_prepare,
  615. .trigger = snd_als4000_capture_trigger,
  616. .pointer = snd_als4000_capture_pointer
  617. };
  618. static int snd_als4000_pcm(struct snd_sb *chip, int device)
  619. {
  620. struct snd_pcm *pcm;
  621. int err;
  622. err = snd_pcm_new(chip->card, "ALS4000 DSP", device, 1, 1, &pcm);
  623. if (err < 0)
  624. return err;
  625. pcm->private_data = chip;
  626. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  627. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_als4000_playback_ops);
  628. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_als4000_capture_ops);
  629. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  630. 64*1024, 64*1024);
  631. chip->pcm = pcm;
  632. return 0;
  633. }
  634. /******************************************************************/
  635. static void snd_als4000_set_addr(unsigned long iobase,
  636. unsigned int sb_io,
  637. unsigned int mpu_io,
  638. unsigned int opl_io,
  639. unsigned int game_io)
  640. {
  641. u32 cfg1 = 0;
  642. u32 cfg2 = 0;
  643. if (mpu_io > 0)
  644. cfg2 |= (mpu_io | 1) << 16;
  645. if (sb_io > 0)
  646. cfg2 |= (sb_io | 1);
  647. if (game_io > 0)
  648. cfg1 |= (game_io | 1) << 16;
  649. if (opl_io > 0)
  650. cfg1 |= (opl_io | 1);
  651. snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1);
  652. snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA9_LEGACY_CFG2, cfg2);
  653. }
  654. static void snd_als4000_configure(struct snd_sb *chip)
  655. {
  656. u8 tmp;
  657. int i;
  658. /* do some more configuration */
  659. spin_lock_irq(&chip->mixer_lock);
  660. tmp = snd_als4_cr_read(chip, ALS4K_CR0_SB_CONFIG);
  661. snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG,
  662. tmp|ALS4K_CR0_MX80_81_REG_WRITE_ENABLE);
  663. /* always select DMA channel 0, since we do not actually use DMA
  664. * SPECS_PAGE: 19/20 */
  665. snd_sbmixer_write(chip, SB_DSP4_DMASETUP, SB_DMASETUP_DMA0);
  666. snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG,
  667. tmp & ~ALS4K_CR0_MX80_81_REG_WRITE_ENABLE);
  668. spin_unlock_irq(&chip->mixer_lock);
  669. spin_lock_irq(&chip->reg_lock);
  670. /* enable interrupts */
  671. snd_als4k_gcr_write(chip, ALS4K_GCR8C_MISC_CTRL,
  672. ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE);
  673. /* SPECS_PAGE: 39 */
  674. for (i = ALS4K_GCR91_DMA0_ADDR; i <= ALS4K_GCR96_DMA3_MODE_COUNT; ++i)
  675. snd_als4k_gcr_write(chip, i, 0);
  676. /* enable burst mode to prevent dropouts during high PCI bus usage */
  677. snd_als4k_gcr_write(chip, ALS4K_GCR99_DMA_EMULATION_CTRL,
  678. (snd_als4k_gcr_read(chip, ALS4K_GCR99_DMA_EMULATION_CTRL) & ~0x07) | 0x04);
  679. spin_unlock_irq(&chip->reg_lock);
  680. }
  681. #ifdef SUPPORT_JOYSTICK
  682. static int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev)
  683. {
  684. struct gameport *gp;
  685. struct resource *r;
  686. int io_port;
  687. if (joystick_port[dev] == 0)
  688. return -ENODEV;
  689. if (joystick_port[dev] == 1) { /* auto-detect */
  690. for (io_port = 0x200; io_port <= 0x218; io_port += 8) {
  691. r = request_region(io_port, 8, "ALS4000 gameport");
  692. if (r)
  693. break;
  694. }
  695. } else {
  696. io_port = joystick_port[dev];
  697. r = request_region(io_port, 8, "ALS4000 gameport");
  698. }
  699. if (!r) {
  700. dev_warn(&acard->pci->dev, "cannot reserve joystick ports\n");
  701. return -EBUSY;
  702. }
  703. acard->gameport = gp = gameport_allocate_port();
  704. if (!gp) {
  705. dev_err(&acard->pci->dev, "cannot allocate memory for gameport\n");
  706. release_and_free_resource(r);
  707. return -ENOMEM;
  708. }
  709. gameport_set_name(gp, "ALS4000 Gameport");
  710. gameport_set_phys(gp, "pci%s/gameport0", pci_name(acard->pci));
  711. gameport_set_dev_parent(gp, &acard->pci->dev);
  712. gp->io = io_port;
  713. gameport_set_port_data(gp, r);
  714. /* Enable legacy joystick port */
  715. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1);
  716. gameport_register_port(acard->gameport);
  717. return 0;
  718. }
  719. static void snd_als4000_free_gameport(struct snd_card_als4000 *acard)
  720. {
  721. if (acard->gameport) {
  722. struct resource *r = gameport_get_port_data(acard->gameport);
  723. gameport_unregister_port(acard->gameport);
  724. acard->gameport = NULL;
  725. /* disable joystick */
  726. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0);
  727. release_and_free_resource(r);
  728. }
  729. }
  730. #else
  731. static inline int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev) { return -ENOSYS; }
  732. static inline void snd_als4000_free_gameport(struct snd_card_als4000 *acard) { }
  733. #endif
  734. static void snd_card_als4000_free( struct snd_card *card )
  735. {
  736. struct snd_card_als4000 *acard = card->private_data;
  737. /* make sure that interrupts are disabled */
  738. snd_als4k_gcr_write_addr(acard->iobase, ALS4K_GCR8C_MISC_CTRL, 0);
  739. /* free resources */
  740. snd_als4000_free_gameport(acard);
  741. pci_release_regions(acard->pci);
  742. pci_disable_device(acard->pci);
  743. }
  744. static int snd_card_als4000_probe(struct pci_dev *pci,
  745. const struct pci_device_id *pci_id)
  746. {
  747. static int dev;
  748. struct snd_card *card;
  749. struct snd_card_als4000 *acard;
  750. unsigned long iobase;
  751. struct snd_sb *chip;
  752. struct snd_opl3 *opl3;
  753. unsigned short word;
  754. int err;
  755. if (dev >= SNDRV_CARDS)
  756. return -ENODEV;
  757. if (!enable[dev]) {
  758. dev++;
  759. return -ENOENT;
  760. }
  761. /* enable PCI device */
  762. if ((err = pci_enable_device(pci)) < 0) {
  763. return err;
  764. }
  765. /* check, if we can restrict PCI DMA transfers to 24 bits */
  766. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
  767. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
  768. dev_err(&pci->dev, "architecture does not support 24bit PCI busmaster DMA\n");
  769. pci_disable_device(pci);
  770. return -ENXIO;
  771. }
  772. if ((err = pci_request_regions(pci, "ALS4000")) < 0) {
  773. pci_disable_device(pci);
  774. return err;
  775. }
  776. iobase = pci_resource_start(pci, 0);
  777. pci_read_config_word(pci, PCI_COMMAND, &word);
  778. pci_write_config_word(pci, PCI_COMMAND, word | PCI_COMMAND_IO);
  779. pci_set_master(pci);
  780. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  781. sizeof(*acard) /* private_data: acard */,
  782. &card);
  783. if (err < 0) {
  784. pci_release_regions(pci);
  785. pci_disable_device(pci);
  786. return err;
  787. }
  788. acard = card->private_data;
  789. acard->pci = pci;
  790. acard->iobase = iobase;
  791. card->private_free = snd_card_als4000_free;
  792. /* disable all legacy ISA stuff */
  793. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0);
  794. if ((err = snd_sbdsp_create(card,
  795. iobase + ALS4K_IOB_10_ADLIB_ADDR0,
  796. pci->irq,
  797. /* internally registered as IRQF_SHARED in case of ALS4000 SB */
  798. snd_als4000_interrupt,
  799. -1,
  800. -1,
  801. SB_HW_ALS4000,
  802. &chip)) < 0) {
  803. goto out_err;
  804. }
  805. acard->chip = chip;
  806. chip->pci = pci;
  807. chip->alt_port = iobase;
  808. snd_als4000_configure(chip);
  809. strcpy(card->driver, "ALS4000");
  810. strcpy(card->shortname, "Avance Logic ALS4000");
  811. sprintf(card->longname, "%s at 0x%lx, irq %i",
  812. card->shortname, chip->alt_port, chip->irq);
  813. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_ALS4000,
  814. iobase + ALS4K_IOB_30_MIDI_DATA,
  815. MPU401_INFO_INTEGRATED |
  816. MPU401_INFO_IRQ_HOOK,
  817. -1, &chip->rmidi)) < 0) {
  818. dev_err(&pci->dev, "no MPU-401 device at 0x%lx?\n",
  819. iobase + ALS4K_IOB_30_MIDI_DATA);
  820. goto out_err;
  821. }
  822. /* FIXME: ALS4000 has interesting MPU401 configuration features
  823. * at ALS4K_CR1A_MPU401_UART_MODE_CONTROL
  824. * (pass-thru / UART switching, fast MIDI clock, etc.),
  825. * however there doesn't seem to be an ALSA API for this...
  826. * SPECS_PAGE: 21 */
  827. if ((err = snd_als4000_pcm(chip, 0)) < 0) {
  828. goto out_err;
  829. }
  830. if ((err = snd_sbmixer_new(chip)) < 0) {
  831. goto out_err;
  832. }
  833. if (snd_opl3_create(card,
  834. iobase + ALS4K_IOB_10_ADLIB_ADDR0,
  835. iobase + ALS4K_IOB_12_ADLIB_ADDR2,
  836. OPL3_HW_AUTO, 1, &opl3) < 0) {
  837. dev_err(&pci->dev, "no OPL device at 0x%lx-0x%lx?\n",
  838. iobase + ALS4K_IOB_10_ADLIB_ADDR0,
  839. iobase + ALS4K_IOB_12_ADLIB_ADDR2);
  840. } else {
  841. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  842. goto out_err;
  843. }
  844. }
  845. snd_als4000_create_gameport(acard, dev);
  846. if ((err = snd_card_register(card)) < 0) {
  847. goto out_err;
  848. }
  849. pci_set_drvdata(pci, card);
  850. dev++;
  851. err = 0;
  852. goto out;
  853. out_err:
  854. snd_card_free(card);
  855. out:
  856. return err;
  857. }
  858. static void snd_card_als4000_remove(struct pci_dev *pci)
  859. {
  860. snd_card_free(pci_get_drvdata(pci));
  861. }
  862. #ifdef CONFIG_PM_SLEEP
  863. static int snd_als4000_suspend(struct device *dev)
  864. {
  865. struct snd_card *card = dev_get_drvdata(dev);
  866. struct snd_card_als4000 *acard = card->private_data;
  867. struct snd_sb *chip = acard->chip;
  868. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  869. snd_pcm_suspend_all(chip->pcm);
  870. snd_sbmixer_suspend(chip);
  871. return 0;
  872. }
  873. static int snd_als4000_resume(struct device *dev)
  874. {
  875. struct snd_card *card = dev_get_drvdata(dev);
  876. struct snd_card_als4000 *acard = card->private_data;
  877. struct snd_sb *chip = acard->chip;
  878. snd_als4000_configure(chip);
  879. snd_sbdsp_reset(chip);
  880. snd_sbmixer_resume(chip);
  881. #ifdef SUPPORT_JOYSTICK
  882. if (acard->gameport)
  883. snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1);
  884. #endif
  885. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  886. return 0;
  887. }
  888. static SIMPLE_DEV_PM_OPS(snd_als4000_pm, snd_als4000_suspend, snd_als4000_resume);
  889. #define SND_ALS4000_PM_OPS &snd_als4000_pm
  890. #else
  891. #define SND_ALS4000_PM_OPS NULL
  892. #endif /* CONFIG_PM_SLEEP */
  893. static struct pci_driver als4000_driver = {
  894. .name = KBUILD_MODNAME,
  895. .id_table = snd_als4000_ids,
  896. .probe = snd_card_als4000_probe,
  897. .remove = snd_card_als4000_remove,
  898. .driver = {
  899. .pm = SND_ALS4000_PM_OPS,
  900. },
  901. };
  902. module_pci_driver(als4000_driver);