debugfs.c 6.8 KB

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  1. /*
  2. * Copyright 2017 Thomas Gleixner <tglx@linutronix.de>
  3. *
  4. * This file is licensed under the GPL V2.
  5. */
  6. #include <linux/irqdomain.h>
  7. #include <linux/irq.h>
  8. #include <linux/uaccess.h>
  9. #include "internals.h"
  10. static struct dentry *irq_dir;
  11. struct irq_bit_descr {
  12. unsigned int mask;
  13. char *name;
  14. };
  15. #define BIT_MASK_DESCR(m) { .mask = m, .name = #m }
  16. static void irq_debug_show_bits(struct seq_file *m, int ind, unsigned int state,
  17. const struct irq_bit_descr *sd, int size)
  18. {
  19. int i;
  20. for (i = 0; i < size; i++, sd++) {
  21. if (state & sd->mask)
  22. seq_printf(m, "%*s%s\n", ind + 12, "", sd->name);
  23. }
  24. }
  25. #ifdef CONFIG_SMP
  26. static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc)
  27. {
  28. struct irq_data *data = irq_desc_get_irq_data(desc);
  29. struct cpumask *msk;
  30. msk = irq_data_get_affinity_mask(data);
  31. seq_printf(m, "affinity: %*pbl\n", cpumask_pr_args(msk));
  32. #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
  33. msk = irq_data_get_effective_affinity_mask(data);
  34. seq_printf(m, "effectiv: %*pbl\n", cpumask_pr_args(msk));
  35. #endif
  36. #ifdef CONFIG_GENERIC_PENDING_IRQ
  37. msk = desc->pending_mask;
  38. seq_printf(m, "pending: %*pbl\n", cpumask_pr_args(msk));
  39. #endif
  40. }
  41. #else
  42. static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc) { }
  43. #endif
  44. static const struct irq_bit_descr irqchip_flags[] = {
  45. BIT_MASK_DESCR(IRQCHIP_SET_TYPE_MASKED),
  46. BIT_MASK_DESCR(IRQCHIP_EOI_IF_HANDLED),
  47. BIT_MASK_DESCR(IRQCHIP_MASK_ON_SUSPEND),
  48. BIT_MASK_DESCR(IRQCHIP_ONOFFLINE_ENABLED),
  49. BIT_MASK_DESCR(IRQCHIP_SKIP_SET_WAKE),
  50. BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE),
  51. BIT_MASK_DESCR(IRQCHIP_EOI_THREADED),
  52. };
  53. static void
  54. irq_debug_show_chip(struct seq_file *m, struct irq_data *data, int ind)
  55. {
  56. struct irq_chip *chip = data->chip;
  57. if (!chip) {
  58. seq_printf(m, "chip: None\n");
  59. return;
  60. }
  61. seq_printf(m, "%*schip: %s\n", ind, "", chip->name);
  62. seq_printf(m, "%*sflags: 0x%lx\n", ind + 1, "", chip->flags);
  63. irq_debug_show_bits(m, ind, chip->flags, irqchip_flags,
  64. ARRAY_SIZE(irqchip_flags));
  65. }
  66. static void
  67. irq_debug_show_data(struct seq_file *m, struct irq_data *data, int ind)
  68. {
  69. seq_printf(m, "%*sdomain: %s\n", ind, "",
  70. data->domain ? data->domain->name : "");
  71. seq_printf(m, "%*shwirq: 0x%lx\n", ind + 1, "", data->hwirq);
  72. irq_debug_show_chip(m, data, ind + 1);
  73. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  74. if (!data->parent_data)
  75. return;
  76. seq_printf(m, "%*sparent:\n", ind + 1, "");
  77. irq_debug_show_data(m, data->parent_data, ind + 4);
  78. #endif
  79. }
  80. static const struct irq_bit_descr irqdata_states[] = {
  81. BIT_MASK_DESCR(IRQ_TYPE_EDGE_RISING),
  82. BIT_MASK_DESCR(IRQ_TYPE_EDGE_FALLING),
  83. BIT_MASK_DESCR(IRQ_TYPE_LEVEL_HIGH),
  84. BIT_MASK_DESCR(IRQ_TYPE_LEVEL_LOW),
  85. BIT_MASK_DESCR(IRQD_LEVEL),
  86. BIT_MASK_DESCR(IRQD_ACTIVATED),
  87. BIT_MASK_DESCR(IRQD_IRQ_STARTED),
  88. BIT_MASK_DESCR(IRQD_IRQ_DISABLED),
  89. BIT_MASK_DESCR(IRQD_IRQ_MASKED),
  90. BIT_MASK_DESCR(IRQD_IRQ_INPROGRESS),
  91. BIT_MASK_DESCR(IRQD_PER_CPU),
  92. BIT_MASK_DESCR(IRQD_NO_BALANCING),
  93. BIT_MASK_DESCR(IRQD_SINGLE_TARGET),
  94. BIT_MASK_DESCR(IRQD_MOVE_PCNTXT),
  95. BIT_MASK_DESCR(IRQD_AFFINITY_SET),
  96. BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING),
  97. BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED),
  98. BIT_MASK_DESCR(IRQD_MANAGED_SHUTDOWN),
  99. BIT_MASK_DESCR(IRQD_FORWARDED_TO_VCPU),
  100. BIT_MASK_DESCR(IRQD_WAKEUP_STATE),
  101. BIT_MASK_DESCR(IRQD_WAKEUP_ARMED),
  102. };
  103. static const struct irq_bit_descr irqdesc_states[] = {
  104. BIT_MASK_DESCR(_IRQ_NOPROBE),
  105. BIT_MASK_DESCR(_IRQ_NOREQUEST),
  106. BIT_MASK_DESCR(_IRQ_NOTHREAD),
  107. BIT_MASK_DESCR(_IRQ_NOAUTOEN),
  108. BIT_MASK_DESCR(_IRQ_NESTED_THREAD),
  109. BIT_MASK_DESCR(_IRQ_PER_CPU_DEVID),
  110. BIT_MASK_DESCR(_IRQ_IS_POLLED),
  111. BIT_MASK_DESCR(_IRQ_DISABLE_UNLAZY),
  112. };
  113. static const struct irq_bit_descr irqdesc_istates[] = {
  114. BIT_MASK_DESCR(IRQS_AUTODETECT),
  115. BIT_MASK_DESCR(IRQS_SPURIOUS_DISABLED),
  116. BIT_MASK_DESCR(IRQS_POLL_INPROGRESS),
  117. BIT_MASK_DESCR(IRQS_ONESHOT),
  118. BIT_MASK_DESCR(IRQS_REPLAY),
  119. BIT_MASK_DESCR(IRQS_WAITING),
  120. BIT_MASK_DESCR(IRQS_PENDING),
  121. BIT_MASK_DESCR(IRQS_SUSPENDED),
  122. };
  123. static int irq_debug_show(struct seq_file *m, void *p)
  124. {
  125. struct irq_desc *desc = m->private;
  126. struct irq_data *data;
  127. raw_spin_lock_irq(&desc->lock);
  128. data = irq_desc_get_irq_data(desc);
  129. seq_printf(m, "handler: %pf\n", desc->handle_irq);
  130. seq_printf(m, "status: 0x%08x\n", desc->status_use_accessors);
  131. irq_debug_show_bits(m, 0, desc->status_use_accessors, irqdesc_states,
  132. ARRAY_SIZE(irqdesc_states));
  133. seq_printf(m, "istate: 0x%08x\n", desc->istate);
  134. irq_debug_show_bits(m, 0, desc->istate, irqdesc_istates,
  135. ARRAY_SIZE(irqdesc_istates));
  136. seq_printf(m, "ddepth: %u\n", desc->depth);
  137. seq_printf(m, "wdepth: %u\n", desc->wake_depth);
  138. seq_printf(m, "dstate: 0x%08x\n", irqd_get(data));
  139. irq_debug_show_bits(m, 0, irqd_get(data), irqdata_states,
  140. ARRAY_SIZE(irqdata_states));
  141. seq_printf(m, "node: %d\n", irq_data_get_node(data));
  142. irq_debug_show_masks(m, desc);
  143. irq_debug_show_data(m, data, 0);
  144. raw_spin_unlock_irq(&desc->lock);
  145. return 0;
  146. }
  147. static int irq_debug_open(struct inode *inode, struct file *file)
  148. {
  149. return single_open(file, irq_debug_show, inode->i_private);
  150. }
  151. static ssize_t irq_debug_write(struct file *file, const char __user *user_buf,
  152. size_t count, loff_t *ppos)
  153. {
  154. struct irq_desc *desc = file_inode(file)->i_private;
  155. char buf[8] = { 0, };
  156. size_t size;
  157. size = min(sizeof(buf) - 1, count);
  158. if (copy_from_user(buf, user_buf, size))
  159. return -EFAULT;
  160. if (!strncmp(buf, "trigger", size)) {
  161. unsigned long flags;
  162. int err;
  163. /* Try the HW interface first */
  164. err = irq_set_irqchip_state(irq_desc_get_irq(desc),
  165. IRQCHIP_STATE_PENDING, true);
  166. if (!err)
  167. return count;
  168. /*
  169. * Otherwise, try to inject via the resend interface,
  170. * which may or may not succeed.
  171. */
  172. chip_bus_lock(desc);
  173. raw_spin_lock_irqsave(&desc->lock, flags);
  174. if (irq_settings_is_level(desc)) {
  175. /* Can't do level, sorry */
  176. err = -EINVAL;
  177. } else {
  178. desc->istate |= IRQS_PENDING;
  179. check_irq_resend(desc);
  180. err = 0;
  181. }
  182. raw_spin_unlock_irqrestore(&desc->lock, flags);
  183. chip_bus_sync_unlock(desc);
  184. return err ? err : count;
  185. }
  186. return count;
  187. }
  188. static const struct file_operations dfs_irq_ops = {
  189. .open = irq_debug_open,
  190. .write = irq_debug_write,
  191. .read = seq_read,
  192. .llseek = seq_lseek,
  193. .release = single_release,
  194. };
  195. void irq_add_debugfs_entry(unsigned int irq, struct irq_desc *desc)
  196. {
  197. char name [10];
  198. if (!irq_dir || !desc || desc->debugfs_file)
  199. return;
  200. sprintf(name, "%d", irq);
  201. desc->debugfs_file = debugfs_create_file(name, 0644, irq_dir, desc,
  202. &dfs_irq_ops);
  203. }
  204. static int __init irq_debugfs_init(void)
  205. {
  206. struct dentry *root_dir;
  207. int irq;
  208. root_dir = debugfs_create_dir("irq", NULL);
  209. if (!root_dir)
  210. return -ENOMEM;
  211. irq_domain_debugfs_init(root_dir);
  212. irq_dir = debugfs_create_dir("irqs", root_dir);
  213. irq_lock_sparse();
  214. for_each_active_irq(irq)
  215. irq_add_debugfs_entry(irq, irq_to_desc(irq));
  216. irq_unlock_sparse();
  217. return 0;
  218. }
  219. __initcall(irq_debugfs_init);