 Takeshi Kihara
|
3c612d2c10
pinctrl: sh-pfc: r8a7795: Fix to reserved MOD_SEL2 bit22
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%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
fc8fd9be2c
pinctrl: sh-pfc: r8a7795: Rename CS1# pin function definitions
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
30cd1c462d
pinctrl: sh-pfc: r8a7795: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
ae03c4ecec
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for TCLK{1,2}_{A,B} pins group
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
67c836b85d
pinctrl: sh-pfc: r8a7795: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin function definitions
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
bad7cc19f2
pinctrl: sh-pfc: r8a7795: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function definitions
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
eada11ac23
pinctrl: sh-pfc: r8a7795: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1 bit10
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
712f36fbb7
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A
|
%!s(int64=7) %!d(string=hai) anos |
|
Takeshi Kihara
|
50d83156e8
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
|
%!s(int64=7) %!d(string=hai) anos |
 Yoshihiro Shimoda
|
933ddbe5f5
pinctrl: sh-pfc: r8a7795: Add USB 2.0 pins, groups and functions
|
%!s(int64=7) %!d(string=hai) anos |
|
Yoshihiro Shimoda
|
f9d130808c
pinctrl: sh-pfc: r8a7795: Change USB3_{OVC,PWEN} definitions
|
%!s(int64=7) %!d(string=hai) anos |
 Geert Uytterhoeven
|
3e6c7727c0
pinctrl: sh-pfc: r8a7795: Add MSIOF pins, groups and functions
|
%!s(int64=8) %!d(string=hai) anos |
|
Takeshi Kihara
|
e2ab177076
pinctrl: sh-pfc: r8a7795: Fix MSIOF3_{SS1,SS2}_E pin function definitions
|
%!s(int64=7) %!d(string=hai) anos |
 Laurent Pinchart
|
c03a133bba
pinctrl: sh-pfc: r8a7795: Add PWM support
|
%!s(int64=7) %!d(string=hai) anos |
|
Laurent Pinchart
|
a20a658593
pinctrl: sh-pfc: r8a7795: Add DU parallel RGB output support
|
%!s(int64=7) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
30c078de6f
pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function
|
%!s(int64=8) %!d(string=hai) anos |
 Kuninori Morimoto
|
68e6389200
pinctrl: sh-pfc: r8a7795: Rename SSI_{WS,SCK}34 to SSI_{WS,SCK}349
|
%!s(int64=7) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
d14a39edf7
pinctrl: sh-pfc: r8a7795: Add SCIF_CLK support
|
%!s(int64=8) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
e7ad4d3c1d
pinctrl: sh-pfc: r8a7795: Add SCIF support
|
%!s(int64=8) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
b205914c8f
pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0
|
%!s(int64=8) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
b332da51a9
pinctrl: sh-pfc: r8a7795: Restore sort order
|
%!s(int64=8) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
4324b6084f
pinctrl: sh-pfc: r8a7795: Fix hscif2_clk_b and hscif4_ctrl
|
%!s(int64=8) %!d(string=hai) anos |
 Niklas Söderlund
|
4c2fb44d60
pinctrl: sh-pfc: r8a7795: Support none GPIO pins bias setting
|
%!s(int64=8) %!d(string=hai) anos |
|
Niklas Söderlund
|
1fa1522f61
pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pins
|
%!s(int64=8) %!d(string=hai) anos |
|
Niklas Söderlund
|
b25719eb93
pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins
|
%!s(int64=8) %!d(string=hai) anos |
|
Niklas Söderlund
|
ea9c740583
pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength
|
%!s(int64=8) %!d(string=hai) anos |
|
Niklas Söderlund
|
d3b861bccd
pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
|
%!s(int64=8) %!d(string=hai) anos |
|
Niklas Söderlund
|
42831cf965
pinctrl: sh-pfc: r8a7795: Simplify get bias logic
|
%!s(int64=8) %!d(string=hai) anos |
|
Laurent Pinchart
|
7955dac1b7
pinctrl: sh-pfc: r8a7795: Add DU support
|
%!s(int64=8) %!d(string=hai) anos |
|
Geert Uytterhoeven
|
adc9ad09f7
pinctrl: sh-pfc: r8a7795: Correct header from R-Car Gen3 to R8A7795
|
%!s(int64=8) %!d(string=hai) anos |
