intel_pmc_ipc.c 21 KB

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  1. /*
  2. * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
  3. *
  4. * (C) Copyright 2014-2015 Intel Corporation
  5. *
  6. * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
  7. * Sreedhara DS <sreedhara.ds@intel.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2
  12. * of the License.
  13. *
  14. * PMC running in ARC processor communicates with other entity running in IA
  15. * core through IPC mechanism which in turn messaging between IA core ad PMC.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/device.h>
  22. #include <linux/pm.h>
  23. #include <linux/pci.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pm_qos.h>
  27. #include <linux/kernel.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include <linux/atomic.h>
  31. #include <linux/notifier.h>
  32. #include <linux/suspend.h>
  33. #include <linux/acpi.h>
  34. #include <asm/intel_pmc_ipc.h>
  35. #include <linux/platform_data/itco_wdt.h>
  36. /*
  37. * IPC registers
  38. * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
  39. * The ARC handles the interrupt and services it, writing optional data to
  40. * the IPC1 registers, updates the IPC_STS response register with the status.
  41. */
  42. #define IPC_CMD 0x0
  43. #define IPC_CMD_MSI 0x100
  44. #define IPC_CMD_SIZE 16
  45. #define IPC_CMD_SUBCMD 12
  46. #define IPC_STATUS 0x04
  47. #define IPC_STATUS_IRQ 0x4
  48. #define IPC_STATUS_ERR 0x2
  49. #define IPC_STATUS_BUSY 0x1
  50. #define IPC_SPTR 0x08
  51. #define IPC_DPTR 0x0C
  52. #define IPC_WRITE_BUFFER 0x80
  53. #define IPC_READ_BUFFER 0x90
  54. /*
  55. * 16-byte buffer for sending data associated with IPC command.
  56. */
  57. #define IPC_DATA_BUFFER_SIZE 16
  58. #define IPC_LOOP_CNT 3000000
  59. #define IPC_MAX_SEC 3
  60. #define IPC_TRIGGER_MODE_IRQ true
  61. /* exported resources from IFWI */
  62. #define PLAT_RESOURCE_IPC_INDEX 0
  63. #define PLAT_RESOURCE_IPC_SIZE 0x1000
  64. #define PLAT_RESOURCE_GCR_OFFSET 0x1008
  65. #define PLAT_RESOURCE_GCR_SIZE 0x4
  66. #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
  67. #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
  68. #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
  69. #define PLAT_RESOURCE_ISP_DATA_INDEX 4
  70. #define PLAT_RESOURCE_ISP_IFACE_INDEX 5
  71. #define PLAT_RESOURCE_GTD_DATA_INDEX 6
  72. #define PLAT_RESOURCE_GTD_IFACE_INDEX 7
  73. #define PLAT_RESOURCE_ACPI_IO_INDEX 0
  74. /*
  75. * BIOS does not create an ACPI device for each PMC function,
  76. * but exports multiple resources from one ACPI device(IPC) for
  77. * multiple functions. This driver is responsible to create a
  78. * platform device and to export resources for those functions.
  79. */
  80. #define TCO_DEVICE_NAME "iTCO_wdt"
  81. #define SMI_EN_OFFSET 0x40
  82. #define SMI_EN_SIZE 4
  83. #define TCO_BASE_OFFSET 0x60
  84. #define TCO_REGS_SIZE 16
  85. #define PUNIT_DEVICE_NAME "intel_punit_ipc"
  86. #define TELEMETRY_DEVICE_NAME "intel_telemetry"
  87. #define TELEM_SSRAM_SIZE 240
  88. #define TELEM_PMC_SSRAM_OFFSET 0x1B00
  89. #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00
  90. #define TCO_PMC_OFFSET 0x8
  91. #define TCO_PMC_SIZE 0x4
  92. static const int iTCO_version = 3;
  93. static struct intel_pmc_ipc_dev {
  94. struct device *dev;
  95. void __iomem *ipc_base;
  96. bool irq_mode;
  97. int irq;
  98. int cmd;
  99. struct completion cmd_complete;
  100. /* The following PMC BARs share the same ACPI device with the IPC */
  101. resource_size_t acpi_io_base;
  102. int acpi_io_size;
  103. struct platform_device *tco_dev;
  104. /* gcr */
  105. resource_size_t gcr_base;
  106. int gcr_size;
  107. /* punit */
  108. struct platform_device *punit_dev;
  109. /* Telemetry */
  110. resource_size_t telem_pmc_ssram_base;
  111. resource_size_t telem_punit_ssram_base;
  112. int telem_pmc_ssram_size;
  113. int telem_punit_ssram_size;
  114. u8 telem_res_inval;
  115. struct platform_device *telemetry_dev;
  116. } ipcdev;
  117. static char *ipc_err_sources[] = {
  118. [IPC_ERR_NONE] =
  119. "no error",
  120. [IPC_ERR_CMD_NOT_SUPPORTED] =
  121. "command not supported",
  122. [IPC_ERR_CMD_NOT_SERVICED] =
  123. "command not serviced",
  124. [IPC_ERR_UNABLE_TO_SERVICE] =
  125. "unable to service",
  126. [IPC_ERR_CMD_INVALID] =
  127. "command invalid",
  128. [IPC_ERR_CMD_FAILED] =
  129. "command failed",
  130. [IPC_ERR_EMSECURITY] =
  131. "Invalid Battery",
  132. [IPC_ERR_UNSIGNEDKERNEL] =
  133. "Unsigned kernel",
  134. };
  135. /* Prevent concurrent calls to the PMC */
  136. static DEFINE_MUTEX(ipclock);
  137. static inline void ipc_send_command(u32 cmd)
  138. {
  139. ipcdev.cmd = cmd;
  140. if (ipcdev.irq_mode) {
  141. reinit_completion(&ipcdev.cmd_complete);
  142. cmd |= IPC_CMD_MSI;
  143. }
  144. writel(cmd, ipcdev.ipc_base + IPC_CMD);
  145. }
  146. static inline u32 ipc_read_status(void)
  147. {
  148. return readl(ipcdev.ipc_base + IPC_STATUS);
  149. }
  150. static inline void ipc_data_writel(u32 data, u32 offset)
  151. {
  152. writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
  153. }
  154. static inline u8 ipc_data_readb(u32 offset)
  155. {
  156. return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  157. }
  158. static inline u32 ipc_data_readl(u32 offset)
  159. {
  160. return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  161. }
  162. static int intel_pmc_ipc_check_status(void)
  163. {
  164. int status;
  165. int ret = 0;
  166. if (ipcdev.irq_mode) {
  167. if (0 == wait_for_completion_timeout(
  168. &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
  169. ret = -ETIMEDOUT;
  170. } else {
  171. int loop_count = IPC_LOOP_CNT;
  172. while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
  173. udelay(1);
  174. if (loop_count == 0)
  175. ret = -ETIMEDOUT;
  176. }
  177. status = ipc_read_status();
  178. if (ret == -ETIMEDOUT) {
  179. dev_err(ipcdev.dev,
  180. "IPC timed out, TS=0x%x, CMD=0x%x\n",
  181. status, ipcdev.cmd);
  182. return ret;
  183. }
  184. if (status & IPC_STATUS_ERR) {
  185. int i;
  186. ret = -EIO;
  187. i = (status >> IPC_CMD_SIZE) & 0xFF;
  188. if (i < ARRAY_SIZE(ipc_err_sources))
  189. dev_err(ipcdev.dev,
  190. "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
  191. ipc_err_sources[i], status, ipcdev.cmd);
  192. else
  193. dev_err(ipcdev.dev,
  194. "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
  195. status, ipcdev.cmd);
  196. if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
  197. ret = -EACCES;
  198. }
  199. return ret;
  200. }
  201. /**
  202. * intel_pmc_ipc_simple_command() - Simple IPC command
  203. * @cmd: IPC command code.
  204. * @sub: IPC command sub type.
  205. *
  206. * Send a simple IPC command to PMC when don't need to specify
  207. * input/output data and source/dest pointers.
  208. *
  209. * Return: an IPC error code or 0 on success.
  210. */
  211. int intel_pmc_ipc_simple_command(int cmd, int sub)
  212. {
  213. int ret;
  214. mutex_lock(&ipclock);
  215. if (ipcdev.dev == NULL) {
  216. mutex_unlock(&ipclock);
  217. return -ENODEV;
  218. }
  219. ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
  220. ret = intel_pmc_ipc_check_status();
  221. mutex_unlock(&ipclock);
  222. return ret;
  223. }
  224. EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
  225. /**
  226. * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
  227. * @cmd: IPC command code.
  228. * @sub: IPC command sub type.
  229. * @in: input data of this IPC command.
  230. * @inlen: input data length in bytes.
  231. * @out: output data of this IPC command.
  232. * @outlen: output data length in dwords.
  233. * @sptr: data writing to SPTR register.
  234. * @dptr: data writing to DPTR register.
  235. *
  236. * Send an IPC command to PMC with input/output data and source/dest pointers.
  237. *
  238. * Return: an IPC error code or 0 on success.
  239. */
  240. int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
  241. u32 outlen, u32 dptr, u32 sptr)
  242. {
  243. u32 wbuf[4] = { 0 };
  244. int ret;
  245. int i;
  246. if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
  247. return -EINVAL;
  248. mutex_lock(&ipclock);
  249. if (ipcdev.dev == NULL) {
  250. mutex_unlock(&ipclock);
  251. return -ENODEV;
  252. }
  253. memcpy(wbuf, in, inlen);
  254. writel(dptr, ipcdev.ipc_base + IPC_DPTR);
  255. writel(sptr, ipcdev.ipc_base + IPC_SPTR);
  256. /* The input data register is 32bit register and inlen is in Byte */
  257. for (i = 0; i < ((inlen + 3) / 4); i++)
  258. ipc_data_writel(wbuf[i], 4 * i);
  259. ipc_send_command((inlen << IPC_CMD_SIZE) |
  260. (sub << IPC_CMD_SUBCMD) | cmd);
  261. ret = intel_pmc_ipc_check_status();
  262. if (!ret) {
  263. /* out is read from 32bit register and outlen is in 32bit */
  264. for (i = 0; i < outlen; i++)
  265. *out++ = ipc_data_readl(4 * i);
  266. }
  267. mutex_unlock(&ipclock);
  268. return ret;
  269. }
  270. EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
  271. /**
  272. * intel_pmc_ipc_command() - IPC command with input/output data
  273. * @cmd: IPC command code.
  274. * @sub: IPC command sub type.
  275. * @in: input data of this IPC command.
  276. * @inlen: input data length in bytes.
  277. * @out: output data of this IPC command.
  278. * @outlen: output data length in dwords.
  279. *
  280. * Send an IPC command to PMC with input/output data.
  281. *
  282. * Return: an IPC error code or 0 on success.
  283. */
  284. int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  285. u32 *out, u32 outlen)
  286. {
  287. return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
  288. }
  289. EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
  290. static irqreturn_t ioc(int irq, void *dev_id)
  291. {
  292. int status;
  293. if (ipcdev.irq_mode) {
  294. status = ipc_read_status();
  295. writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
  296. }
  297. complete(&ipcdev.cmd_complete);
  298. return IRQ_HANDLED;
  299. }
  300. static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  301. {
  302. resource_size_t pci_resource;
  303. int ret;
  304. int len;
  305. ipcdev.dev = &pci_dev_get(pdev)->dev;
  306. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  307. ret = pci_enable_device(pdev);
  308. if (ret)
  309. return ret;
  310. ret = pci_request_regions(pdev, "intel_pmc_ipc");
  311. if (ret)
  312. return ret;
  313. pci_resource = pci_resource_start(pdev, 0);
  314. len = pci_resource_len(pdev, 0);
  315. if (!pci_resource || !len) {
  316. dev_err(&pdev->dev, "Failed to get resource\n");
  317. return -ENOMEM;
  318. }
  319. init_completion(&ipcdev.cmd_complete);
  320. if (request_irq(pdev->irq, ioc, 0, "intel_pmc_ipc", &ipcdev)) {
  321. dev_err(&pdev->dev, "Failed to request irq\n");
  322. return -EBUSY;
  323. }
  324. ipcdev.ipc_base = ioremap_nocache(pci_resource, len);
  325. if (!ipcdev.ipc_base) {
  326. dev_err(&pdev->dev, "Failed to ioremap ipc base\n");
  327. free_irq(pdev->irq, &ipcdev);
  328. ret = -ENOMEM;
  329. }
  330. return ret;
  331. }
  332. static void ipc_pci_remove(struct pci_dev *pdev)
  333. {
  334. free_irq(pdev->irq, &ipcdev);
  335. pci_release_regions(pdev);
  336. pci_dev_put(pdev);
  337. iounmap(ipcdev.ipc_base);
  338. ipcdev.dev = NULL;
  339. }
  340. static const struct pci_device_id ipc_pci_ids[] = {
  341. {PCI_VDEVICE(INTEL, 0x0a94), 0},
  342. {PCI_VDEVICE(INTEL, 0x1a94), 0},
  343. { 0,}
  344. };
  345. MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
  346. static struct pci_driver ipc_pci_driver = {
  347. .name = "intel_pmc_ipc",
  348. .id_table = ipc_pci_ids,
  349. .probe = ipc_pci_probe,
  350. .remove = ipc_pci_remove,
  351. };
  352. static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
  353. struct device_attribute *attr,
  354. const char *buf, size_t count)
  355. {
  356. int subcmd;
  357. int cmd;
  358. int ret;
  359. ret = sscanf(buf, "%d %d", &cmd, &subcmd);
  360. if (ret != 2) {
  361. dev_err(dev, "Error args\n");
  362. return -EINVAL;
  363. }
  364. ret = intel_pmc_ipc_simple_command(cmd, subcmd);
  365. if (ret) {
  366. dev_err(dev, "command %d error with %d\n", cmd, ret);
  367. return ret;
  368. }
  369. return (ssize_t)count;
  370. }
  371. static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
  372. struct device_attribute *attr,
  373. const char *buf, size_t count)
  374. {
  375. unsigned long val;
  376. int subcmd;
  377. int ret;
  378. if (kstrtoul(buf, 0, &val))
  379. return -EINVAL;
  380. if (val)
  381. subcmd = 1;
  382. else
  383. subcmd = 0;
  384. ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
  385. if (ret) {
  386. dev_err(dev, "command north %d error with %d\n", subcmd, ret);
  387. return ret;
  388. }
  389. return (ssize_t)count;
  390. }
  391. static DEVICE_ATTR(simplecmd, S_IWUSR,
  392. NULL, intel_pmc_ipc_simple_cmd_store);
  393. static DEVICE_ATTR(northpeak, S_IWUSR,
  394. NULL, intel_pmc_ipc_northpeak_store);
  395. static struct attribute *intel_ipc_attrs[] = {
  396. &dev_attr_northpeak.attr,
  397. &dev_attr_simplecmd.attr,
  398. NULL
  399. };
  400. static const struct attribute_group intel_ipc_group = {
  401. .attrs = intel_ipc_attrs,
  402. };
  403. static struct resource punit_res_array[] = {
  404. /* Punit BIOS */
  405. {
  406. .flags = IORESOURCE_MEM,
  407. },
  408. {
  409. .flags = IORESOURCE_MEM,
  410. },
  411. /* Punit ISP */
  412. {
  413. .flags = IORESOURCE_MEM,
  414. },
  415. {
  416. .flags = IORESOURCE_MEM,
  417. },
  418. /* Punit GTD */
  419. {
  420. .flags = IORESOURCE_MEM,
  421. },
  422. {
  423. .flags = IORESOURCE_MEM,
  424. },
  425. };
  426. #define TCO_RESOURCE_ACPI_IO 0
  427. #define TCO_RESOURCE_SMI_EN_IO 1
  428. #define TCO_RESOURCE_GCR_MEM 2
  429. static struct resource tco_res[] = {
  430. /* ACPI - TCO */
  431. {
  432. .flags = IORESOURCE_IO,
  433. },
  434. /* ACPI - SMI */
  435. {
  436. .flags = IORESOURCE_IO,
  437. },
  438. /* GCS */
  439. {
  440. .flags = IORESOURCE_MEM,
  441. },
  442. };
  443. static struct itco_wdt_platform_data tco_info = {
  444. .name = "Apollo Lake SoC",
  445. .version = 5,
  446. };
  447. #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
  448. #define TELEMETRY_RESOURCE_PMC_SSRAM 1
  449. static struct resource telemetry_res[] = {
  450. /*Telemetry*/
  451. {
  452. .flags = IORESOURCE_MEM,
  453. },
  454. {
  455. .flags = IORESOURCE_MEM,
  456. },
  457. };
  458. static int ipc_create_punit_device(void)
  459. {
  460. struct platform_device *pdev;
  461. const struct platform_device_info pdevinfo = {
  462. .parent = ipcdev.dev,
  463. .name = PUNIT_DEVICE_NAME,
  464. .id = -1,
  465. .res = punit_res_array,
  466. .num_res = ARRAY_SIZE(punit_res_array),
  467. };
  468. pdev = platform_device_register_full(&pdevinfo);
  469. if (IS_ERR(pdev))
  470. return PTR_ERR(pdev);
  471. ipcdev.punit_dev = pdev;
  472. return 0;
  473. }
  474. static int ipc_create_tco_device(void)
  475. {
  476. struct platform_device *pdev;
  477. struct resource *res;
  478. const struct platform_device_info pdevinfo = {
  479. .parent = ipcdev.dev,
  480. .name = TCO_DEVICE_NAME,
  481. .id = -1,
  482. .res = tco_res,
  483. .num_res = ARRAY_SIZE(tco_res),
  484. .data = &tco_info,
  485. .size_data = sizeof(tco_info),
  486. };
  487. res = tco_res + TCO_RESOURCE_ACPI_IO;
  488. res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET;
  489. res->end = res->start + TCO_REGS_SIZE - 1;
  490. res = tco_res + TCO_RESOURCE_SMI_EN_IO;
  491. res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
  492. res->end = res->start + SMI_EN_SIZE - 1;
  493. res = tco_res + TCO_RESOURCE_GCR_MEM;
  494. res->start = ipcdev.gcr_base + TCO_PMC_OFFSET;
  495. res->end = res->start + TCO_PMC_SIZE - 1;
  496. pdev = platform_device_register_full(&pdevinfo);
  497. if (IS_ERR(pdev))
  498. return PTR_ERR(pdev);
  499. ipcdev.tco_dev = pdev;
  500. return 0;
  501. }
  502. static int ipc_create_telemetry_device(void)
  503. {
  504. struct platform_device *pdev;
  505. struct resource *res;
  506. const struct platform_device_info pdevinfo = {
  507. .parent = ipcdev.dev,
  508. .name = TELEMETRY_DEVICE_NAME,
  509. .id = -1,
  510. .res = telemetry_res,
  511. .num_res = ARRAY_SIZE(telemetry_res),
  512. };
  513. res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM;
  514. res->start = ipcdev.telem_punit_ssram_base;
  515. res->end = res->start + ipcdev.telem_punit_ssram_size - 1;
  516. res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM;
  517. res->start = ipcdev.telem_pmc_ssram_base;
  518. res->end = res->start + ipcdev.telem_pmc_ssram_size - 1;
  519. pdev = platform_device_register_full(&pdevinfo);
  520. if (IS_ERR(pdev))
  521. return PTR_ERR(pdev);
  522. ipcdev.telemetry_dev = pdev;
  523. return 0;
  524. }
  525. static int ipc_create_pmc_devices(void)
  526. {
  527. int ret;
  528. /* If we have ACPI based watchdog use that instead */
  529. if (!acpi_has_watchdog()) {
  530. ret = ipc_create_tco_device();
  531. if (ret) {
  532. dev_err(ipcdev.dev, "Failed to add tco platform device\n");
  533. return ret;
  534. }
  535. }
  536. ret = ipc_create_punit_device();
  537. if (ret) {
  538. dev_err(ipcdev.dev, "Failed to add punit platform device\n");
  539. platform_device_unregister(ipcdev.tco_dev);
  540. }
  541. if (!ipcdev.telem_res_inval) {
  542. ret = ipc_create_telemetry_device();
  543. if (ret)
  544. dev_warn(ipcdev.dev,
  545. "Failed to add telemetry platform device\n");
  546. }
  547. return ret;
  548. }
  549. static int ipc_plat_get_res(struct platform_device *pdev)
  550. {
  551. struct resource *res, *punit_res;
  552. void __iomem *addr;
  553. int size;
  554. res = platform_get_resource(pdev, IORESOURCE_IO,
  555. PLAT_RESOURCE_ACPI_IO_INDEX);
  556. if (!res) {
  557. dev_err(&pdev->dev, "Failed to get io resource\n");
  558. return -ENXIO;
  559. }
  560. size = resource_size(res);
  561. ipcdev.acpi_io_base = res->start;
  562. ipcdev.acpi_io_size = size;
  563. dev_info(&pdev->dev, "io res: %pR\n", res);
  564. punit_res = punit_res_array;
  565. /* This is index 0 to cover BIOS data register */
  566. res = platform_get_resource(pdev, IORESOURCE_MEM,
  567. PLAT_RESOURCE_BIOS_DATA_INDEX);
  568. if (!res) {
  569. dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n");
  570. return -ENXIO;
  571. }
  572. *punit_res = *res;
  573. dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res);
  574. /* This is index 1 to cover BIOS interface register */
  575. res = platform_get_resource(pdev, IORESOURCE_MEM,
  576. PLAT_RESOURCE_BIOS_IFACE_INDEX);
  577. if (!res) {
  578. dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n");
  579. return -ENXIO;
  580. }
  581. *++punit_res = *res;
  582. dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res);
  583. /* This is index 2 to cover ISP data register, optional */
  584. res = platform_get_resource(pdev, IORESOURCE_MEM,
  585. PLAT_RESOURCE_ISP_DATA_INDEX);
  586. ++punit_res;
  587. if (res) {
  588. *punit_res = *res;
  589. dev_info(&pdev->dev, "punit ISP data res: %pR\n", res);
  590. }
  591. /* This is index 3 to cover ISP interface register, optional */
  592. res = platform_get_resource(pdev, IORESOURCE_MEM,
  593. PLAT_RESOURCE_ISP_IFACE_INDEX);
  594. ++punit_res;
  595. if (res) {
  596. *punit_res = *res;
  597. dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res);
  598. }
  599. /* This is index 4 to cover GTD data register, optional */
  600. res = platform_get_resource(pdev, IORESOURCE_MEM,
  601. PLAT_RESOURCE_GTD_DATA_INDEX);
  602. ++punit_res;
  603. if (res) {
  604. *punit_res = *res;
  605. dev_info(&pdev->dev, "punit GTD data res: %pR\n", res);
  606. }
  607. /* This is index 5 to cover GTD interface register, optional */
  608. res = platform_get_resource(pdev, IORESOURCE_MEM,
  609. PLAT_RESOURCE_GTD_IFACE_INDEX);
  610. ++punit_res;
  611. if (res) {
  612. *punit_res = *res;
  613. dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res);
  614. }
  615. res = platform_get_resource(pdev, IORESOURCE_MEM,
  616. PLAT_RESOURCE_IPC_INDEX);
  617. if (!res) {
  618. dev_err(&pdev->dev, "Failed to get ipc resource\n");
  619. return -ENXIO;
  620. }
  621. size = PLAT_RESOURCE_IPC_SIZE;
  622. if (!request_mem_region(res->start, size, pdev->name)) {
  623. dev_err(&pdev->dev, "Failed to request ipc resource\n");
  624. return -EBUSY;
  625. }
  626. addr = ioremap_nocache(res->start, size);
  627. if (!addr) {
  628. dev_err(&pdev->dev, "I/O memory remapping failed\n");
  629. release_mem_region(res->start, size);
  630. return -ENOMEM;
  631. }
  632. ipcdev.ipc_base = addr;
  633. ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET;
  634. ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE;
  635. dev_info(&pdev->dev, "ipc res: %pR\n", res);
  636. ipcdev.telem_res_inval = 0;
  637. res = platform_get_resource(pdev, IORESOURCE_MEM,
  638. PLAT_RESOURCE_TELEM_SSRAM_INDEX);
  639. if (!res) {
  640. dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n");
  641. ipcdev.telem_res_inval = 1;
  642. } else {
  643. ipcdev.telem_punit_ssram_base = res->start +
  644. TELEM_PUNIT_SSRAM_OFFSET;
  645. ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE;
  646. ipcdev.telem_pmc_ssram_base = res->start +
  647. TELEM_PMC_SSRAM_OFFSET;
  648. ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE;
  649. dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res);
  650. }
  651. return 0;
  652. }
  653. #ifdef CONFIG_ACPI
  654. static const struct acpi_device_id ipc_acpi_ids[] = {
  655. { "INT34D2", 0},
  656. { }
  657. };
  658. MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
  659. #endif
  660. static int ipc_plat_probe(struct platform_device *pdev)
  661. {
  662. struct resource *res;
  663. int ret;
  664. ipcdev.dev = &pdev->dev;
  665. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  666. init_completion(&ipcdev.cmd_complete);
  667. ipcdev.irq = platform_get_irq(pdev, 0);
  668. if (ipcdev.irq < 0) {
  669. dev_err(&pdev->dev, "Failed to get irq\n");
  670. return -EINVAL;
  671. }
  672. ret = ipc_plat_get_res(pdev);
  673. if (ret) {
  674. dev_err(&pdev->dev, "Failed to request resource\n");
  675. return ret;
  676. }
  677. ret = ipc_create_pmc_devices();
  678. if (ret) {
  679. dev_err(&pdev->dev, "Failed to create pmc devices\n");
  680. goto err_device;
  681. }
  682. if (request_irq(ipcdev.irq, ioc, IRQF_NO_SUSPEND,
  683. "intel_pmc_ipc", &ipcdev)) {
  684. dev_err(&pdev->dev, "Failed to request irq\n");
  685. ret = -EBUSY;
  686. goto err_irq;
  687. }
  688. ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
  689. if (ret) {
  690. dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
  691. ret);
  692. goto err_sys;
  693. }
  694. return 0;
  695. err_sys:
  696. free_irq(ipcdev.irq, &ipcdev);
  697. err_irq:
  698. platform_device_unregister(ipcdev.tco_dev);
  699. platform_device_unregister(ipcdev.punit_dev);
  700. platform_device_unregister(ipcdev.telemetry_dev);
  701. err_device:
  702. iounmap(ipcdev.ipc_base);
  703. res = platform_get_resource(pdev, IORESOURCE_MEM,
  704. PLAT_RESOURCE_IPC_INDEX);
  705. if (res)
  706. release_mem_region(res->start, PLAT_RESOURCE_IPC_SIZE);
  707. return ret;
  708. }
  709. static int ipc_plat_remove(struct platform_device *pdev)
  710. {
  711. struct resource *res;
  712. sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
  713. free_irq(ipcdev.irq, &ipcdev);
  714. platform_device_unregister(ipcdev.tco_dev);
  715. platform_device_unregister(ipcdev.punit_dev);
  716. platform_device_unregister(ipcdev.telemetry_dev);
  717. iounmap(ipcdev.ipc_base);
  718. res = platform_get_resource(pdev, IORESOURCE_MEM,
  719. PLAT_RESOURCE_IPC_INDEX);
  720. if (res)
  721. release_mem_region(res->start, PLAT_RESOURCE_IPC_SIZE);
  722. ipcdev.dev = NULL;
  723. return 0;
  724. }
  725. static struct platform_driver ipc_plat_driver = {
  726. .remove = ipc_plat_remove,
  727. .probe = ipc_plat_probe,
  728. .driver = {
  729. .name = "pmc-ipc-plat",
  730. .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
  731. },
  732. };
  733. static int __init intel_pmc_ipc_init(void)
  734. {
  735. int ret;
  736. ret = platform_driver_register(&ipc_plat_driver);
  737. if (ret) {
  738. pr_err("Failed to register PMC ipc platform driver\n");
  739. return ret;
  740. }
  741. ret = pci_register_driver(&ipc_pci_driver);
  742. if (ret) {
  743. pr_err("Failed to register PMC ipc pci driver\n");
  744. platform_driver_unregister(&ipc_plat_driver);
  745. return ret;
  746. }
  747. return ret;
  748. }
  749. static void __exit intel_pmc_ipc_exit(void)
  750. {
  751. pci_unregister_driver(&ipc_pci_driver);
  752. platform_driver_unregister(&ipc_plat_driver);
  753. }
  754. MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
  755. MODULE_DESCRIPTION("Intel PMC IPC driver");
  756. MODULE_LICENSE("GPL");
  757. /* Some modules are dependent on this, so init earlier */
  758. fs_initcall(intel_pmc_ipc_init);
  759. module_exit(intel_pmc_ipc_exit);