phy-berlin-usb.c 6.1 KB

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  1. /*
  2. * Copyright (C) 2014 Marvell Technology Group Ltd.
  3. *
  4. * Antoine Tenart <antoine.tenart@free-electrons.com>
  5. * Jisheng Zhang <jszhang@marvell.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of_device.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/reset.h>
  17. #define USB_PHY_PLL 0x04
  18. #define USB_PHY_PLL_CONTROL 0x08
  19. #define USB_PHY_TX_CTRL0 0x10
  20. #define USB_PHY_TX_CTRL1 0x14
  21. #define USB_PHY_TX_CTRL2 0x18
  22. #define USB_PHY_RX_CTRL 0x20
  23. #define USB_PHY_ANALOG 0x34
  24. /* USB_PHY_PLL */
  25. #define CLK_REF_DIV(x) ((x) << 4)
  26. #define FEEDBACK_CLK_DIV(x) ((x) << 8)
  27. /* USB_PHY_PLL_CONTROL */
  28. #define CLK_STABLE BIT(0)
  29. #define PLL_CTRL_PIN BIT(1)
  30. #define PLL_CTRL_REG BIT(2)
  31. #define PLL_ON BIT(3)
  32. #define PHASE_OFF_TOL_125 (0x0 << 5)
  33. #define PHASE_OFF_TOL_250 BIT(5)
  34. #define KVC0_CALIB (0x0 << 9)
  35. #define KVC0_REG_CTRL BIT(9)
  36. #define KVC0_HIGH (0x0 << 10)
  37. #define KVC0_LOW (0x3 << 10)
  38. #define CLK_BLK_EN BIT(13)
  39. /* USB_PHY_TX_CTRL0 */
  40. #define EXT_HS_RCAL_EN BIT(3)
  41. #define EXT_FS_RCAL_EN BIT(4)
  42. #define IMPCAL_VTH_DIV(x) ((x) << 5)
  43. #define EXT_RS_RCAL_DIV(x) ((x) << 8)
  44. #define EXT_FS_RCAL_DIV(x) ((x) << 12)
  45. /* USB_PHY_TX_CTRL1 */
  46. #define TX_VDD15_14 (0x0 << 4)
  47. #define TX_VDD15_15 BIT(4)
  48. #define TX_VDD15_16 (0x2 << 4)
  49. #define TX_VDD15_17 (0x3 << 4)
  50. #define TX_VDD12_VDD (0x0 << 6)
  51. #define TX_VDD12_11 BIT(6)
  52. #define TX_VDD12_12 (0x2 << 6)
  53. #define TX_VDD12_13 (0x3 << 6)
  54. #define LOW_VDD_EN BIT(8)
  55. #define TX_OUT_AMP(x) ((x) << 9)
  56. /* USB_PHY_TX_CTRL2 */
  57. #define TX_CHAN_CTRL_REG(x) ((x) << 0)
  58. #define DRV_SLEWRATE(x) ((x) << 4)
  59. #define IMP_CAL_FS_HS_DLY_0 (0x0 << 6)
  60. #define IMP_CAL_FS_HS_DLY_1 BIT(6)
  61. #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
  62. #define IMP_CAL_FS_HS_DLY_3 (0x3 << 6)
  63. #define FS_DRV_EN_MASK(x) ((x) << 8)
  64. #define HS_DRV_EN_MASK(x) ((x) << 12)
  65. /* USB_PHY_RX_CTRL */
  66. #define PHASE_FREEZE_DLY_2_CL (0x0 << 0)
  67. #define PHASE_FREEZE_DLY_4_CL BIT(0)
  68. #define ACK_LENGTH_8_CL (0x0 << 2)
  69. #define ACK_LENGTH_12_CL BIT(2)
  70. #define ACK_LENGTH_16_CL (0x2 << 2)
  71. #define ACK_LENGTH_20_CL (0x3 << 2)
  72. #define SQ_LENGTH_3 (0x0 << 4)
  73. #define SQ_LENGTH_6 BIT(4)
  74. #define SQ_LENGTH_9 (0x2 << 4)
  75. #define SQ_LENGTH_12 (0x3 << 4)
  76. #define DISCON_THRESHOLD_260 (0x0 << 6)
  77. #define DISCON_THRESHOLD_270 BIT(6)
  78. #define DISCON_THRESHOLD_280 (0x2 << 6)
  79. #define DISCON_THRESHOLD_290 (0x3 << 6)
  80. #define SQ_THRESHOLD(x) ((x) << 8)
  81. #define LPF_COEF(x) ((x) << 12)
  82. #define INTPL_CUR_10 (0x0 << 14)
  83. #define INTPL_CUR_20 BIT(14)
  84. #define INTPL_CUR_30 (0x2 << 14)
  85. #define INTPL_CUR_40 (0x3 << 14)
  86. /* USB_PHY_ANALOG */
  87. #define ANA_PWR_UP BIT(1)
  88. #define ANA_PWR_DOWN BIT(2)
  89. #define V2I_VCO_RATIO(x) ((x) << 7)
  90. #define R_ROTATE_90 (0x0 << 10)
  91. #define R_ROTATE_0 BIT(10)
  92. #define MODE_TEST_EN BIT(11)
  93. #define ANA_TEST_DC_CTRL(x) ((x) << 12)
  94. static const u32 phy_berlin_pll_dividers[] = {
  95. /* Berlin 2 */
  96. CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
  97. /* Berlin 2CD/Q */
  98. CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
  99. };
  100. struct phy_berlin_usb_priv {
  101. void __iomem *base;
  102. struct reset_control *rst_ctrl;
  103. u32 pll_divider;
  104. };
  105. static int phy_berlin_usb_power_on(struct phy *phy)
  106. {
  107. struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
  108. reset_control_reset(priv->rst_ctrl);
  109. writel(priv->pll_divider,
  110. priv->base + USB_PHY_PLL);
  111. writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
  112. CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
  113. writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
  114. priv->base + USB_PHY_ANALOG);
  115. writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
  116. DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
  117. INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
  118. writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
  119. writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
  120. priv->base + USB_PHY_TX_CTRL0);
  121. writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
  122. EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
  123. writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
  124. priv->base + USB_PHY_TX_CTRL0);
  125. writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
  126. FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
  127. return 0;
  128. }
  129. static const struct phy_ops phy_berlin_usb_ops = {
  130. .power_on = phy_berlin_usb_power_on,
  131. .owner = THIS_MODULE,
  132. };
  133. static const struct of_device_id phy_berlin_usb_of_match[] = {
  134. {
  135. .compatible = "marvell,berlin2-usb-phy",
  136. .data = &phy_berlin_pll_dividers[0],
  137. },
  138. {
  139. .compatible = "marvell,berlin2cd-usb-phy",
  140. .data = &phy_berlin_pll_dividers[1],
  141. },
  142. { },
  143. };
  144. MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match);
  145. static int phy_berlin_usb_probe(struct platform_device *pdev)
  146. {
  147. const struct of_device_id *match =
  148. of_match_device(phy_berlin_usb_of_match, &pdev->dev);
  149. struct phy_berlin_usb_priv *priv;
  150. struct resource *res;
  151. struct phy *phy;
  152. struct phy_provider *phy_provider;
  153. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  154. if (!priv)
  155. return -ENOMEM;
  156. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  157. priv->base = devm_ioremap_resource(&pdev->dev, res);
  158. if (IS_ERR(priv->base))
  159. return PTR_ERR(priv->base);
  160. priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
  161. if (IS_ERR(priv->rst_ctrl))
  162. return PTR_ERR(priv->rst_ctrl);
  163. priv->pll_divider = *((u32 *)match->data);
  164. phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
  165. if (IS_ERR(phy)) {
  166. dev_err(&pdev->dev, "failed to create PHY\n");
  167. return PTR_ERR(phy);
  168. }
  169. phy_set_drvdata(phy, priv);
  170. phy_provider =
  171. devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
  172. return PTR_ERR_OR_ZERO(phy_provider);
  173. }
  174. static struct platform_driver phy_berlin_usb_driver = {
  175. .probe = phy_berlin_usb_probe,
  176. .driver = {
  177. .name = "phy-berlin-usb",
  178. .of_match_table = phy_berlin_usb_of_match,
  179. },
  180. };
  181. module_platform_driver(phy_berlin_usb_driver);
  182. MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
  183. MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
  184. MODULE_LICENSE("GPL");