au1550nd.c 12 KB

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  1. /*
  2. * drivers/mtd/nand/au1550nd.c
  3. *
  4. * Copyright (C) 2004 Embedded Edge, LLC
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/slab.h>
  12. #include <linux/gpio.h>
  13. #include <linux/module.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mtd/mtd.h>
  16. #include <linux/mtd/nand.h>
  17. #include <linux/mtd/partitions.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/io.h>
  20. #include <asm/mach-au1x00/au1000.h>
  21. #include <asm/mach-au1x00/au1550nd.h>
  22. struct au1550nd_ctx {
  23. struct nand_chip chip;
  24. int cs;
  25. void __iomem *base;
  26. void (*write_byte)(struct mtd_info *, u_char);
  27. };
  28. /**
  29. * au_read_byte - read one byte from the chip
  30. * @mtd: MTD device structure
  31. *
  32. * read function for 8bit buswidth
  33. */
  34. static u_char au_read_byte(struct mtd_info *mtd)
  35. {
  36. struct nand_chip *this = mtd_to_nand(mtd);
  37. u_char ret = readb(this->IO_ADDR_R);
  38. wmb(); /* drain writebuffer */
  39. return ret;
  40. }
  41. /**
  42. * au_write_byte - write one byte to the chip
  43. * @mtd: MTD device structure
  44. * @byte: pointer to data byte to write
  45. *
  46. * write function for 8it buswidth
  47. */
  48. static void au_write_byte(struct mtd_info *mtd, u_char byte)
  49. {
  50. struct nand_chip *this = mtd_to_nand(mtd);
  51. writeb(byte, this->IO_ADDR_W);
  52. wmb(); /* drain writebuffer */
  53. }
  54. /**
  55. * au_read_byte16 - read one byte endianness aware from the chip
  56. * @mtd: MTD device structure
  57. *
  58. * read function for 16bit buswidth with endianness conversion
  59. */
  60. static u_char au_read_byte16(struct mtd_info *mtd)
  61. {
  62. struct nand_chip *this = mtd_to_nand(mtd);
  63. u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
  64. wmb(); /* drain writebuffer */
  65. return ret;
  66. }
  67. /**
  68. * au_write_byte16 - write one byte endianness aware to the chip
  69. * @mtd: MTD device structure
  70. * @byte: pointer to data byte to write
  71. *
  72. * write function for 16bit buswidth with endianness conversion
  73. */
  74. static void au_write_byte16(struct mtd_info *mtd, u_char byte)
  75. {
  76. struct nand_chip *this = mtd_to_nand(mtd);
  77. writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
  78. wmb(); /* drain writebuffer */
  79. }
  80. /**
  81. * au_read_word - read one word from the chip
  82. * @mtd: MTD device structure
  83. *
  84. * read function for 16bit buswidth without endianness conversion
  85. */
  86. static u16 au_read_word(struct mtd_info *mtd)
  87. {
  88. struct nand_chip *this = mtd_to_nand(mtd);
  89. u16 ret = readw(this->IO_ADDR_R);
  90. wmb(); /* drain writebuffer */
  91. return ret;
  92. }
  93. /**
  94. * au_write_buf - write buffer to chip
  95. * @mtd: MTD device structure
  96. * @buf: data buffer
  97. * @len: number of bytes to write
  98. *
  99. * write function for 8bit buswidth
  100. */
  101. static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  102. {
  103. int i;
  104. struct nand_chip *this = mtd_to_nand(mtd);
  105. for (i = 0; i < len; i++) {
  106. writeb(buf[i], this->IO_ADDR_W);
  107. wmb(); /* drain writebuffer */
  108. }
  109. }
  110. /**
  111. * au_read_buf - read chip data into buffer
  112. * @mtd: MTD device structure
  113. * @buf: buffer to store date
  114. * @len: number of bytes to read
  115. *
  116. * read function for 8bit buswidth
  117. */
  118. static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  119. {
  120. int i;
  121. struct nand_chip *this = mtd_to_nand(mtd);
  122. for (i = 0; i < len; i++) {
  123. buf[i] = readb(this->IO_ADDR_R);
  124. wmb(); /* drain writebuffer */
  125. }
  126. }
  127. /**
  128. * au_write_buf16 - write buffer to chip
  129. * @mtd: MTD device structure
  130. * @buf: data buffer
  131. * @len: number of bytes to write
  132. *
  133. * write function for 16bit buswidth
  134. */
  135. static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
  136. {
  137. int i;
  138. struct nand_chip *this = mtd_to_nand(mtd);
  139. u16 *p = (u16 *) buf;
  140. len >>= 1;
  141. for (i = 0; i < len; i++) {
  142. writew(p[i], this->IO_ADDR_W);
  143. wmb(); /* drain writebuffer */
  144. }
  145. }
  146. /**
  147. * au_read_buf16 - read chip data into buffer
  148. * @mtd: MTD device structure
  149. * @buf: buffer to store date
  150. * @len: number of bytes to read
  151. *
  152. * read function for 16bit buswidth
  153. */
  154. static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
  155. {
  156. int i;
  157. struct nand_chip *this = mtd_to_nand(mtd);
  158. u16 *p = (u16 *) buf;
  159. len >>= 1;
  160. for (i = 0; i < len; i++) {
  161. p[i] = readw(this->IO_ADDR_R);
  162. wmb(); /* drain writebuffer */
  163. }
  164. }
  165. /* Select the chip by setting nCE to low */
  166. #define NAND_CTL_SETNCE 1
  167. /* Deselect the chip by setting nCE to high */
  168. #define NAND_CTL_CLRNCE 2
  169. /* Select the command latch by setting CLE to high */
  170. #define NAND_CTL_SETCLE 3
  171. /* Deselect the command latch by setting CLE to low */
  172. #define NAND_CTL_CLRCLE 4
  173. /* Select the address latch by setting ALE to high */
  174. #define NAND_CTL_SETALE 5
  175. /* Deselect the address latch by setting ALE to low */
  176. #define NAND_CTL_CLRALE 6
  177. static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
  178. {
  179. struct nand_chip *this = mtd_to_nand(mtd);
  180. struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
  181. chip);
  182. switch (cmd) {
  183. case NAND_CTL_SETCLE:
  184. this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
  185. break;
  186. case NAND_CTL_CLRCLE:
  187. this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
  188. break;
  189. case NAND_CTL_SETALE:
  190. this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
  191. break;
  192. case NAND_CTL_CLRALE:
  193. this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
  194. /* FIXME: Nobody knows why this is necessary,
  195. * but it works only that way */
  196. udelay(1);
  197. break;
  198. case NAND_CTL_SETNCE:
  199. /* assert (force assert) chip enable */
  200. alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
  201. break;
  202. case NAND_CTL_CLRNCE:
  203. /* deassert chip enable */
  204. alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
  205. break;
  206. }
  207. this->IO_ADDR_R = this->IO_ADDR_W;
  208. wmb(); /* Drain the writebuffer */
  209. }
  210. int au1550_device_ready(struct mtd_info *mtd)
  211. {
  212. return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
  213. }
  214. /**
  215. * au1550_select_chip - control -CE line
  216. * Forbid driving -CE manually permitting the NAND controller to do this.
  217. * Keeping -CE asserted during the whole sector reads interferes with the
  218. * NOR flash and PCMCIA drivers as it causes contention on the static bus.
  219. * We only have to hold -CE low for the NAND read commands since the flash
  220. * chip needs it to be asserted during chip not ready time but the NAND
  221. * controller keeps it released.
  222. *
  223. * @mtd: MTD device structure
  224. * @chip: chipnumber to select, -1 for deselect
  225. */
  226. static void au1550_select_chip(struct mtd_info *mtd, int chip)
  227. {
  228. }
  229. /**
  230. * au1550_command - Send command to NAND device
  231. * @mtd: MTD device structure
  232. * @command: the command to be sent
  233. * @column: the column address for this command, -1 if none
  234. * @page_addr: the page address for this command, -1 if none
  235. */
  236. static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
  237. {
  238. struct nand_chip *this = mtd_to_nand(mtd);
  239. struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
  240. chip);
  241. int ce_override = 0, i;
  242. unsigned long flags = 0;
  243. /* Begin command latch cycle */
  244. au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
  245. /*
  246. * Write out the command to the device.
  247. */
  248. if (command == NAND_CMD_SEQIN) {
  249. int readcmd;
  250. if (column >= mtd->writesize) {
  251. /* OOB area */
  252. column -= mtd->writesize;
  253. readcmd = NAND_CMD_READOOB;
  254. } else if (column < 256) {
  255. /* First 256 bytes --> READ0 */
  256. readcmd = NAND_CMD_READ0;
  257. } else {
  258. column -= 256;
  259. readcmd = NAND_CMD_READ1;
  260. }
  261. ctx->write_byte(mtd, readcmd);
  262. }
  263. ctx->write_byte(mtd, command);
  264. /* Set ALE and clear CLE to start address cycle */
  265. au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
  266. if (column != -1 || page_addr != -1) {
  267. au1550_hwcontrol(mtd, NAND_CTL_SETALE);
  268. /* Serially input address */
  269. if (column != -1) {
  270. /* Adjust columns for 16 bit buswidth */
  271. if (this->options & NAND_BUSWIDTH_16 &&
  272. !nand_opcode_8bits(command))
  273. column >>= 1;
  274. ctx->write_byte(mtd, column);
  275. }
  276. if (page_addr != -1) {
  277. ctx->write_byte(mtd, (u8)(page_addr & 0xff));
  278. if (command == NAND_CMD_READ0 ||
  279. command == NAND_CMD_READ1 ||
  280. command == NAND_CMD_READOOB) {
  281. /*
  282. * NAND controller will release -CE after
  283. * the last address byte is written, so we'll
  284. * have to forcibly assert it. No interrupts
  285. * are allowed while we do this as we don't
  286. * want the NOR flash or PCMCIA drivers to
  287. * steal our precious bytes of data...
  288. */
  289. ce_override = 1;
  290. local_irq_save(flags);
  291. au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
  292. }
  293. ctx->write_byte(mtd, (u8)(page_addr >> 8));
  294. /* One more address cycle for devices > 32MiB */
  295. if (this->chipsize > (32 << 20))
  296. ctx->write_byte(mtd,
  297. ((page_addr >> 16) & 0x0f));
  298. }
  299. /* Latch in address */
  300. au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
  301. }
  302. /*
  303. * Program and erase have their own busy handlers.
  304. * Status and sequential in need no delay.
  305. */
  306. switch (command) {
  307. case NAND_CMD_PAGEPROG:
  308. case NAND_CMD_ERASE1:
  309. case NAND_CMD_ERASE2:
  310. case NAND_CMD_SEQIN:
  311. case NAND_CMD_STATUS:
  312. return;
  313. case NAND_CMD_RESET:
  314. break;
  315. case NAND_CMD_READ0:
  316. case NAND_CMD_READ1:
  317. case NAND_CMD_READOOB:
  318. /* Check if we're really driving -CE low (just in case) */
  319. if (unlikely(!ce_override))
  320. break;
  321. /* Apply a short delay always to ensure that we do wait tWB. */
  322. ndelay(100);
  323. /* Wait for a chip to become ready... */
  324. for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
  325. udelay(1);
  326. /* Release -CE and re-enable interrupts. */
  327. au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
  328. local_irq_restore(flags);
  329. return;
  330. }
  331. /* Apply this short delay always to ensure that we do wait tWB. */
  332. ndelay(100);
  333. while(!this->dev_ready(mtd));
  334. }
  335. static int find_nand_cs(unsigned long nand_base)
  336. {
  337. void __iomem *base =
  338. (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
  339. unsigned long addr, staddr, start, mask, end;
  340. int i;
  341. for (i = 0; i < 4; i++) {
  342. addr = 0x1000 + (i * 0x10); /* CSx */
  343. staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
  344. /* figure out the decoded range of this CS */
  345. start = (staddr << 4) & 0xfffc0000;
  346. mask = (staddr << 18) & 0xfffc0000;
  347. end = (start | (start - 1)) & ~(start ^ mask);
  348. if ((nand_base >= start) && (nand_base < end))
  349. return i;
  350. }
  351. return -ENODEV;
  352. }
  353. static int au1550nd_probe(struct platform_device *pdev)
  354. {
  355. struct au1550nd_platdata *pd;
  356. struct au1550nd_ctx *ctx;
  357. struct nand_chip *this;
  358. struct mtd_info *mtd;
  359. struct resource *r;
  360. int ret, cs;
  361. pd = dev_get_platdata(&pdev->dev);
  362. if (!pd) {
  363. dev_err(&pdev->dev, "missing platform data\n");
  364. return -ENODEV;
  365. }
  366. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  367. if (!ctx)
  368. return -ENOMEM;
  369. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  370. if (!r) {
  371. dev_err(&pdev->dev, "no NAND memory resource\n");
  372. ret = -ENODEV;
  373. goto out1;
  374. }
  375. if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
  376. dev_err(&pdev->dev, "cannot claim NAND memory area\n");
  377. ret = -ENOMEM;
  378. goto out1;
  379. }
  380. ctx->base = ioremap_nocache(r->start, 0x1000);
  381. if (!ctx->base) {
  382. dev_err(&pdev->dev, "cannot remap NAND memory area\n");
  383. ret = -ENODEV;
  384. goto out2;
  385. }
  386. this = &ctx->chip;
  387. mtd = nand_to_mtd(this);
  388. mtd->dev.parent = &pdev->dev;
  389. /* figure out which CS# r->start belongs to */
  390. cs = find_nand_cs(r->start);
  391. if (cs < 0) {
  392. dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
  393. ret = -ENODEV;
  394. goto out3;
  395. }
  396. ctx->cs = cs;
  397. this->dev_ready = au1550_device_ready;
  398. this->select_chip = au1550_select_chip;
  399. this->cmdfunc = au1550_command;
  400. /* 30 us command delay time */
  401. this->chip_delay = 30;
  402. this->ecc.mode = NAND_ECC_SOFT;
  403. this->ecc.algo = NAND_ECC_HAMMING;
  404. if (pd->devwidth)
  405. this->options |= NAND_BUSWIDTH_16;
  406. this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
  407. ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
  408. this->read_word = au_read_word;
  409. this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
  410. this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
  411. ret = nand_scan(mtd, 1);
  412. if (ret) {
  413. dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
  414. goto out3;
  415. }
  416. mtd_device_register(mtd, pd->parts, pd->num_parts);
  417. platform_set_drvdata(pdev, ctx);
  418. return 0;
  419. out3:
  420. iounmap(ctx->base);
  421. out2:
  422. release_mem_region(r->start, resource_size(r));
  423. out1:
  424. kfree(ctx);
  425. return ret;
  426. }
  427. static int au1550nd_remove(struct platform_device *pdev)
  428. {
  429. struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
  430. struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  431. nand_release(nand_to_mtd(&ctx->chip));
  432. iounmap(ctx->base);
  433. release_mem_region(r->start, 0x1000);
  434. kfree(ctx);
  435. return 0;
  436. }
  437. static struct platform_driver au1550nd_driver = {
  438. .driver = {
  439. .name = "au1550-nand",
  440. },
  441. .probe = au1550nd_probe,
  442. .remove = au1550nd_remove,
  443. };
  444. module_platform_driver(au1550nd_driver);
  445. MODULE_LICENSE("GPL");
  446. MODULE_AUTHOR("Embedded Edge, LLC");
  447. MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");