leds-ss4200.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574
  1. /*
  2. * SS4200-E Hardware API
  3. * Copyright (c) 2009, Intel Corporation.
  4. * Copyright IBM Corporation, 2009
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * Author: Dave Hansen <dave@sr71.net>
  20. */
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/dmi.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/kernel.h>
  26. #include <linux/leds.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include <linux/types.h>
  30. #include <linux/uaccess.h>
  31. MODULE_AUTHOR("Rodney Girod <rgirod@confocus.com>, Dave Hansen <dave@sr71.net>");
  32. MODULE_DESCRIPTION("Intel NAS/Home Server ICH7 GPIO Driver");
  33. MODULE_LICENSE("GPL");
  34. /*
  35. * ICH7 LPC/GPIO PCI Config register offsets
  36. */
  37. #define PMBASE 0x040
  38. #define GPIO_BASE 0x048
  39. #define GPIO_CTRL 0x04c
  40. #define GPIO_EN 0x010
  41. /*
  42. * The ICH7 GPIO register block is 64 bytes in size.
  43. */
  44. #define ICH7_GPIO_SIZE 64
  45. /*
  46. * Define register offsets within the ICH7 register block.
  47. */
  48. #define GPIO_USE_SEL 0x000
  49. #define GP_IO_SEL 0x004
  50. #define GP_LVL 0x00c
  51. #define GPO_BLINK 0x018
  52. #define GPI_INV 0x030
  53. #define GPIO_USE_SEL2 0x034
  54. #define GP_IO_SEL2 0x038
  55. #define GP_LVL2 0x03c
  56. /*
  57. * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.
  58. */
  59. static const struct pci_device_id ich7_lpc_pci_id[] = {
  60. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0) },
  61. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1) },
  62. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_30) },
  63. { } /* NULL entry */
  64. };
  65. MODULE_DEVICE_TABLE(pci, ich7_lpc_pci_id);
  66. static int __init ss4200_led_dmi_callback(const struct dmi_system_id *id)
  67. {
  68. pr_info("detected '%s'\n", id->ident);
  69. return 1;
  70. }
  71. static bool nodetect;
  72. module_param_named(nodetect, nodetect, bool, 0);
  73. MODULE_PARM_DESC(nodetect, "Skip DMI-based hardware detection");
  74. /*
  75. * struct nas_led_whitelist - List of known good models
  76. *
  77. * Contains the known good models this driver is compatible with.
  78. * When adding a new model try to be as strict as possible. This
  79. * makes it possible to keep the false positives (the model is
  80. * detected as working, but in reality it is not) as low as
  81. * possible.
  82. */
  83. static struct dmi_system_id nas_led_whitelist[] __initdata = {
  84. {
  85. .callback = ss4200_led_dmi_callback,
  86. .ident = "Intel SS4200-E",
  87. .matches = {
  88. DMI_MATCH(DMI_SYS_VENDOR, "Intel"),
  89. DMI_MATCH(DMI_PRODUCT_NAME, "SS4200-E"),
  90. DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
  91. }
  92. },
  93. {
  94. /*
  95. * FUJITSU SIEMENS SCALEO Home Server/SS4200-E
  96. * BIOS V090L 12/19/2007
  97. */
  98. .callback = ss4200_led_dmi_callback,
  99. .ident = "Fujitsu Siemens SCALEO Home Server",
  100. .matches = {
  101. DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
  102. DMI_MATCH(DMI_PRODUCT_NAME, "SCALEO Home Server"),
  103. DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")
  104. }
  105. },
  106. {}
  107. };
  108. /*
  109. * Base I/O address assigned to the Power Management register block
  110. */
  111. static u32 g_pm_io_base;
  112. /*
  113. * Base I/O address assigned to the ICH7 GPIO register block
  114. */
  115. static u32 nas_gpio_io_base;
  116. /*
  117. * When we successfully register a region, we are returned a resource.
  118. * We use these to identify which regions we need to release on our way
  119. * back out.
  120. */
  121. static struct resource *gp_gpio_resource;
  122. struct nasgpio_led {
  123. char *name;
  124. u32 gpio_bit;
  125. struct led_classdev led_cdev;
  126. };
  127. /*
  128. * gpio_bit(s) are the ICH7 GPIO bit assignments
  129. */
  130. static struct nasgpio_led nasgpio_leds[] = {
  131. { .name = "hdd1:blue:sata", .gpio_bit = 0 },
  132. { .name = "hdd1:amber:sata", .gpio_bit = 1 },
  133. { .name = "hdd2:blue:sata", .gpio_bit = 2 },
  134. { .name = "hdd2:amber:sata", .gpio_bit = 3 },
  135. { .name = "hdd3:blue:sata", .gpio_bit = 4 },
  136. { .name = "hdd3:amber:sata", .gpio_bit = 5 },
  137. { .name = "hdd4:blue:sata", .gpio_bit = 6 },
  138. { .name = "hdd4:amber:sata", .gpio_bit = 7 },
  139. { .name = "power:blue:power", .gpio_bit = 27},
  140. { .name = "power:amber:power", .gpio_bit = 28},
  141. };
  142. #define NAS_RECOVERY 0x00000400 /* GPIO10 */
  143. static struct nasgpio_led *
  144. led_classdev_to_nasgpio_led(struct led_classdev *led_cdev)
  145. {
  146. return container_of(led_cdev, struct nasgpio_led, led_cdev);
  147. }
  148. static struct nasgpio_led *get_led_named(char *name)
  149. {
  150. int i;
  151. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
  152. if (strcmp(nasgpio_leds[i].name, name))
  153. continue;
  154. return &nasgpio_leds[i];
  155. }
  156. return NULL;
  157. }
  158. /*
  159. * This protects access to the gpio ports.
  160. */
  161. static DEFINE_SPINLOCK(nasgpio_gpio_lock);
  162. /*
  163. * There are two gpio ports, one for blinking and the other
  164. * for power. @port tells us if we're doing blinking or
  165. * power control.
  166. *
  167. * Caller must hold nasgpio_gpio_lock
  168. */
  169. static void __nasgpio_led_set_attr(struct led_classdev *led_cdev,
  170. u32 port, u32 value)
  171. {
  172. struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
  173. u32 gpio_out;
  174. gpio_out = inl(nas_gpio_io_base + port);
  175. if (value)
  176. gpio_out |= (1<<led->gpio_bit);
  177. else
  178. gpio_out &= ~(1<<led->gpio_bit);
  179. outl(gpio_out, nas_gpio_io_base + port);
  180. }
  181. static void nasgpio_led_set_attr(struct led_classdev *led_cdev,
  182. u32 port, u32 value)
  183. {
  184. spin_lock(&nasgpio_gpio_lock);
  185. __nasgpio_led_set_attr(led_cdev, port, value);
  186. spin_unlock(&nasgpio_gpio_lock);
  187. }
  188. static u32 nasgpio_led_get_attr(struct led_classdev *led_cdev, u32 port)
  189. {
  190. struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);
  191. u32 gpio_in;
  192. spin_lock(&nasgpio_gpio_lock);
  193. gpio_in = inl(nas_gpio_io_base + port);
  194. spin_unlock(&nasgpio_gpio_lock);
  195. if (gpio_in & (1<<led->gpio_bit))
  196. return 1;
  197. return 0;
  198. }
  199. /*
  200. * There is actual brightness control in the hardware,
  201. * but it is via smbus commands and not implemented
  202. * in this driver.
  203. */
  204. static void nasgpio_led_set_brightness(struct led_classdev *led_cdev,
  205. enum led_brightness brightness)
  206. {
  207. u32 setting = 0;
  208. if (brightness >= LED_HALF)
  209. setting = 1;
  210. /*
  211. * Hold the lock across both operations. This ensures
  212. * consistency so that both the "turn off blinking"
  213. * and "turn light off" operations complete as a set.
  214. */
  215. spin_lock(&nasgpio_gpio_lock);
  216. /*
  217. * LED class documentation asks that past blink state
  218. * be disabled when brightness is turned to zero.
  219. */
  220. if (brightness == 0)
  221. __nasgpio_led_set_attr(led_cdev, GPO_BLINK, 0);
  222. __nasgpio_led_set_attr(led_cdev, GP_LVL, setting);
  223. spin_unlock(&nasgpio_gpio_lock);
  224. }
  225. static int nasgpio_led_set_blink(struct led_classdev *led_cdev,
  226. unsigned long *delay_on,
  227. unsigned long *delay_off)
  228. {
  229. u32 setting = 1;
  230. if (!(*delay_on == 0 && *delay_off == 0) &&
  231. !(*delay_on == 500 && *delay_off == 500))
  232. return -EINVAL;
  233. /*
  234. * These are very approximate.
  235. */
  236. *delay_on = 500;
  237. *delay_off = 500;
  238. nasgpio_led_set_attr(led_cdev, GPO_BLINK, setting);
  239. return 0;
  240. }
  241. /*
  242. * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have
  243. * already taken care of this, but we will do so in a non destructive manner
  244. * so that we have what we need whether the BIOS did it or not.
  245. */
  246. static int ich7_gpio_init(struct device *dev)
  247. {
  248. int i;
  249. u32 config_data = 0;
  250. u32 all_nas_led = 0;
  251. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
  252. all_nas_led |= (1<<nasgpio_leds[i].gpio_bit);
  253. spin_lock(&nasgpio_gpio_lock);
  254. /*
  255. * We need to enable all of the GPIO lines used by the NAS box,
  256. * so we will read the current Use Selection and add our usage
  257. * to it. This should be benign with regard to the original
  258. * BIOS configuration.
  259. */
  260. config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
  261. dev_dbg(dev, ": Data read from GPIO_USE_SEL = 0x%08x\n", config_data);
  262. config_data |= all_nas_led + NAS_RECOVERY;
  263. outl(config_data, nas_gpio_io_base + GPIO_USE_SEL);
  264. config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);
  265. dev_dbg(dev, ": GPIO_USE_SEL = 0x%08x\n\n", config_data);
  266. /*
  267. * The LED GPIO outputs need to be configured for output, so we
  268. * will ensure that all LED lines are cleared for output and the
  269. * RECOVERY line ready for input. This too should be benign with
  270. * regard to BIOS configuration.
  271. */
  272. config_data = inl(nas_gpio_io_base + GP_IO_SEL);
  273. dev_dbg(dev, ": Data read from GP_IO_SEL = 0x%08x\n",
  274. config_data);
  275. config_data &= ~all_nas_led;
  276. config_data |= NAS_RECOVERY;
  277. outl(config_data, nas_gpio_io_base + GP_IO_SEL);
  278. config_data = inl(nas_gpio_io_base + GP_IO_SEL);
  279. dev_dbg(dev, ": GP_IO_SEL = 0x%08x\n", config_data);
  280. /*
  281. * In our final system, the BIOS will initialize the state of all
  282. * of the LEDs. For now, we turn them all off (or Low).
  283. */
  284. config_data = inl(nas_gpio_io_base + GP_LVL);
  285. dev_dbg(dev, ": Data read from GP_LVL = 0x%08x\n", config_data);
  286. /*
  287. * In our final system, the BIOS will initialize the blink state of all
  288. * of the LEDs. For now, we turn blink off for all of them.
  289. */
  290. config_data = inl(nas_gpio_io_base + GPO_BLINK);
  291. dev_dbg(dev, ": Data read from GPO_BLINK = 0x%08x\n", config_data);
  292. /*
  293. * At this moment, I am unsure if anything needs to happen with GPI_INV
  294. */
  295. config_data = inl(nas_gpio_io_base + GPI_INV);
  296. dev_dbg(dev, ": Data read from GPI_INV = 0x%08x\n", config_data);
  297. spin_unlock(&nasgpio_gpio_lock);
  298. return 0;
  299. }
  300. static void ich7_lpc_cleanup(struct device *dev)
  301. {
  302. /*
  303. * If we were given exclusive use of the GPIO
  304. * I/O Address range, we must return it.
  305. */
  306. if (gp_gpio_resource) {
  307. dev_dbg(dev, ": Releasing GPIO I/O addresses\n");
  308. release_region(nas_gpio_io_base, ICH7_GPIO_SIZE);
  309. gp_gpio_resource = NULL;
  310. }
  311. }
  312. /*
  313. * The OS has determined that the LPC of the Intel ICH7 Southbridge is present
  314. * so we can retrive the required operational information and prepare the GPIO.
  315. */
  316. static struct pci_dev *nas_gpio_pci_dev;
  317. static int ich7_lpc_probe(struct pci_dev *dev,
  318. const struct pci_device_id *id)
  319. {
  320. int status;
  321. u32 gc = 0;
  322. status = pci_enable_device(dev);
  323. if (status) {
  324. dev_err(&dev->dev, "pci_enable_device failed\n");
  325. return -EIO;
  326. }
  327. nas_gpio_pci_dev = dev;
  328. status = pci_read_config_dword(dev, PMBASE, &g_pm_io_base);
  329. if (status)
  330. goto out;
  331. g_pm_io_base &= 0x00000ff80;
  332. status = pci_read_config_dword(dev, GPIO_CTRL, &gc);
  333. if (!(GPIO_EN & gc)) {
  334. status = -EEXIST;
  335. dev_info(&dev->dev,
  336. "ERROR: The LPC GPIO Block has not been enabled.\n");
  337. goto out;
  338. }
  339. status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);
  340. if (0 > status) {
  341. dev_info(&dev->dev, "Unable to read GPIOBASE.\n");
  342. goto out;
  343. }
  344. dev_dbg(&dev->dev, ": GPIOBASE = 0x%08x\n", nas_gpio_io_base);
  345. nas_gpio_io_base &= 0x00000ffc0;
  346. /*
  347. * Insure that we have exclusive access to the GPIO I/O address range.
  348. */
  349. gp_gpio_resource = request_region(nas_gpio_io_base, ICH7_GPIO_SIZE,
  350. KBUILD_MODNAME);
  351. if (NULL == gp_gpio_resource) {
  352. dev_info(&dev->dev,
  353. "ERROR Unable to register GPIO I/O addresses.\n");
  354. status = -1;
  355. goto out;
  356. }
  357. /*
  358. * Initialize the GPIO for NAS/Home Server Use
  359. */
  360. ich7_gpio_init(&dev->dev);
  361. out:
  362. if (status) {
  363. ich7_lpc_cleanup(&dev->dev);
  364. pci_disable_device(dev);
  365. }
  366. return status;
  367. }
  368. static void ich7_lpc_remove(struct pci_dev *dev)
  369. {
  370. ich7_lpc_cleanup(&dev->dev);
  371. pci_disable_device(dev);
  372. }
  373. /*
  374. * pci_driver structure passed to the PCI modules
  375. */
  376. static struct pci_driver nas_gpio_pci_driver = {
  377. .name = KBUILD_MODNAME,
  378. .id_table = ich7_lpc_pci_id,
  379. .probe = ich7_lpc_probe,
  380. .remove = ich7_lpc_remove,
  381. };
  382. static struct led_classdev *get_classdev_for_led_nr(int nr)
  383. {
  384. struct nasgpio_led *nas_led = &nasgpio_leds[nr];
  385. struct led_classdev *led = &nas_led->led_cdev;
  386. return led;
  387. }
  388. static void set_power_light_amber_noblink(void)
  389. {
  390. struct nasgpio_led *amber = get_led_named("power:amber:power");
  391. struct nasgpio_led *blue = get_led_named("power:blue:power");
  392. if (!amber || !blue)
  393. return;
  394. /*
  395. * LED_OFF implies disabling future blinking
  396. */
  397. pr_debug("setting blue off and amber on\n");
  398. nasgpio_led_set_brightness(&blue->led_cdev, LED_OFF);
  399. nasgpio_led_set_brightness(&amber->led_cdev, LED_FULL);
  400. }
  401. static ssize_t nas_led_blink_show(struct device *dev,
  402. struct device_attribute *attr, char *buf)
  403. {
  404. struct led_classdev *led = dev_get_drvdata(dev);
  405. int blinking = 0;
  406. if (nasgpio_led_get_attr(led, GPO_BLINK))
  407. blinking = 1;
  408. return sprintf(buf, "%u\n", blinking);
  409. }
  410. static ssize_t nas_led_blink_store(struct device *dev,
  411. struct device_attribute *attr,
  412. const char *buf, size_t size)
  413. {
  414. int ret;
  415. struct led_classdev *led = dev_get_drvdata(dev);
  416. unsigned long blink_state;
  417. ret = kstrtoul(buf, 10, &blink_state);
  418. if (ret)
  419. return ret;
  420. nasgpio_led_set_attr(led, GPO_BLINK, blink_state);
  421. return size;
  422. }
  423. static DEVICE_ATTR(blink, 0644, nas_led_blink_show, nas_led_blink_store);
  424. static struct attribute *nasgpio_led_attrs[] = {
  425. &dev_attr_blink.attr,
  426. NULL
  427. };
  428. ATTRIBUTE_GROUPS(nasgpio_led);
  429. static int register_nasgpio_led(int led_nr)
  430. {
  431. int ret;
  432. struct nasgpio_led *nas_led = &nasgpio_leds[led_nr];
  433. struct led_classdev *led = get_classdev_for_led_nr(led_nr);
  434. led->name = nas_led->name;
  435. led->brightness = LED_OFF;
  436. if (nasgpio_led_get_attr(led, GP_LVL))
  437. led->brightness = LED_FULL;
  438. led->brightness_set = nasgpio_led_set_brightness;
  439. led->blink_set = nasgpio_led_set_blink;
  440. led->groups = nasgpio_led_groups;
  441. ret = led_classdev_register(&nas_gpio_pci_dev->dev, led);
  442. if (ret)
  443. return ret;
  444. return 0;
  445. }
  446. static void unregister_nasgpio_led(int led_nr)
  447. {
  448. struct led_classdev *led = get_classdev_for_led_nr(led_nr);
  449. led_classdev_unregister(led);
  450. }
  451. /*
  452. * module load/initialization
  453. */
  454. static int __init nas_gpio_init(void)
  455. {
  456. int i;
  457. int ret = 0;
  458. int nr_devices = 0;
  459. nr_devices = dmi_check_system(nas_led_whitelist);
  460. if (nodetect) {
  461. pr_info("skipping hardware autodetection\n");
  462. pr_info("Please send 'dmidecode' output to dave@sr71.net\n");
  463. nr_devices++;
  464. }
  465. if (nr_devices <= 0) {
  466. pr_info("no LED devices found\n");
  467. return -ENODEV;
  468. }
  469. pr_info("registering PCI driver\n");
  470. ret = pci_register_driver(&nas_gpio_pci_driver);
  471. if (ret)
  472. return ret;
  473. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {
  474. ret = register_nasgpio_led(i);
  475. if (ret)
  476. goto out_err;
  477. }
  478. /*
  479. * When the system powers on, the BIOS leaves the power
  480. * light blue and blinking. This will turn it solid
  481. * amber once the driver is loaded.
  482. */
  483. set_power_light_amber_noblink();
  484. return 0;
  485. out_err:
  486. for (i--; i >= 0; i--)
  487. unregister_nasgpio_led(i);
  488. pci_unregister_driver(&nas_gpio_pci_driver);
  489. return ret;
  490. }
  491. /*
  492. * module unload
  493. */
  494. static void __exit nas_gpio_exit(void)
  495. {
  496. int i;
  497. pr_info("Unregistering driver\n");
  498. for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)
  499. unregister_nasgpio_led(i);
  500. pci_unregister_driver(&nas_gpio_pci_driver);
  501. }
  502. module_init(nas_gpio_init);
  503. module_exit(nas_gpio_exit);