bcm_iproc_tsc.c 14 KB

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  1. /*
  2. * Copyright (C) 2015 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/input.h>
  16. #include <linux/delay.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/keyboard.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/slab.h>
  21. #include <linux/of.h>
  22. #include <asm/irq.h>
  23. #include <linux/io.h>
  24. #include <linux/clk.h>
  25. #include <linux/serio.h>
  26. #include <linux/mfd/syscon.h>
  27. #include <linux/regmap.h>
  28. #define IPROC_TS_NAME "iproc-ts"
  29. #define PEN_DOWN_STATUS 1
  30. #define PEN_UP_STATUS 0
  31. #define X_MIN 0
  32. #define Y_MIN 0
  33. #define X_MAX 0xFFF
  34. #define Y_MAX 0xFFF
  35. /* Value given by controller for invalid coordinate. */
  36. #define INVALID_COORD 0xFFFFFFFF
  37. /* Register offsets */
  38. #define REGCTL1 0x00
  39. #define REGCTL2 0x04
  40. #define INTERRUPT_THRES 0x08
  41. #define INTERRUPT_MASK 0x0c
  42. #define INTERRUPT_STATUS 0x10
  43. #define CONTROLLER_STATUS 0x14
  44. #define FIFO_DATA 0x18
  45. #define FIFO_DATA_X_Y_MASK 0xFFFF
  46. #define ANALOG_CONTROL 0x1c
  47. #define AUX_DATA 0x20
  48. #define DEBOUNCE_CNTR_STAT 0x24
  49. #define SCAN_CNTR_STAT 0x28
  50. #define REM_CNTR_STAT 0x2c
  51. #define SETTLING_TIMER_STAT 0x30
  52. #define SPARE_REG 0x34
  53. #define SOFT_BYPASS_CONTROL 0x38
  54. #define SOFT_BYPASS_DATA 0x3c
  55. /* Bit values for INTERRUPT_MASK and INTERRUPT_STATUS regs */
  56. #define TS_PEN_INTR_MASK BIT(0)
  57. #define TS_FIFO_INTR_MASK BIT(2)
  58. /* Bit values for CONTROLLER_STATUS reg1 */
  59. #define TS_PEN_DOWN BIT(0)
  60. /* Shift values for control reg1 */
  61. #define SCANNING_PERIOD_SHIFT 24
  62. #define DEBOUNCE_TIMEOUT_SHIFT 16
  63. #define SETTLING_TIMEOUT_SHIFT 8
  64. #define TOUCH_TIMEOUT_SHIFT 0
  65. /* Shift values for coordinates from fifo */
  66. #define X_COORD_SHIFT 0
  67. #define Y_COORD_SHIFT 16
  68. /* Bit values for REGCTL2 */
  69. #define TS_CONTROLLER_EN_BIT BIT(16)
  70. #define TS_CONTROLLER_AVGDATA_SHIFT 8
  71. #define TS_CONTROLLER_AVGDATA_MASK (0x7 << TS_CONTROLLER_AVGDATA_SHIFT)
  72. #define TS_CONTROLLER_PWR_LDO BIT(5)
  73. #define TS_CONTROLLER_PWR_ADC BIT(4)
  74. #define TS_CONTROLLER_PWR_BGP BIT(3)
  75. #define TS_CONTROLLER_PWR_TS BIT(2)
  76. #define TS_WIRE_MODE_BIT BIT(1)
  77. #define dbg_reg(dev, priv, reg) \
  78. do { \
  79. u32 val; \
  80. regmap_read(priv->regmap, reg, &val); \
  81. dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \
  82. } while (0)
  83. struct tsc_param {
  84. /* Each step is 1024 us. Valid 1-256 */
  85. u32 scanning_period;
  86. /* Each step is 512 us. Valid 0-255 */
  87. u32 debounce_timeout;
  88. /*
  89. * The settling duration (in ms) is the amount of time the tsc
  90. * waits to allow the voltage to settle after turning on the
  91. * drivers in detection mode. Valid values: 0-11
  92. * 0 = 0.008 ms
  93. * 1 = 0.01 ms
  94. * 2 = 0.02 ms
  95. * 3 = 0.04 ms
  96. * 4 = 0.08 ms
  97. * 5 = 0.16 ms
  98. * 6 = 0.32 ms
  99. * 7 = 0.64 ms
  100. * 8 = 1.28 ms
  101. * 9 = 2.56 ms
  102. * 10 = 5.12 ms
  103. * 11 = 10.24 ms
  104. */
  105. u32 settling_timeout;
  106. /* touch timeout in sample counts */
  107. u32 touch_timeout;
  108. /*
  109. * Number of data samples which are averaged before a final data point
  110. * is placed into the FIFO
  111. */
  112. u32 average_data;
  113. /* FIFO threshold */
  114. u32 fifo_threshold;
  115. /* Optional standard touchscreen properties. */
  116. u32 max_x;
  117. u32 max_y;
  118. u32 fuzz_x;
  119. u32 fuzz_y;
  120. bool invert_x;
  121. bool invert_y;
  122. };
  123. struct iproc_ts_priv {
  124. struct platform_device *pdev;
  125. struct input_dev *idev;
  126. struct regmap *regmap;
  127. struct clk *tsc_clk;
  128. int pen_status;
  129. struct tsc_param cfg_params;
  130. };
  131. /*
  132. * Set default values the same as hardware reset values
  133. * except for fifo_threshold with is set to 1.
  134. */
  135. static const struct tsc_param iproc_default_config = {
  136. .scanning_period = 0x5, /* 1 to 256 */
  137. .debounce_timeout = 0x28, /* 0 to 255 */
  138. .settling_timeout = 0x7, /* 0 to 11 */
  139. .touch_timeout = 0xa, /* 0 to 255 */
  140. .average_data = 5, /* entry 5 = 32 pts */
  141. .fifo_threshold = 1, /* 0 to 31 */
  142. .max_x = X_MAX,
  143. .max_y = Y_MAX,
  144. };
  145. static void ts_reg_dump(struct iproc_ts_priv *priv)
  146. {
  147. struct device *dev = &priv->pdev->dev;
  148. dbg_reg(dev, priv, REGCTL1);
  149. dbg_reg(dev, priv, REGCTL2);
  150. dbg_reg(dev, priv, INTERRUPT_THRES);
  151. dbg_reg(dev, priv, INTERRUPT_MASK);
  152. dbg_reg(dev, priv, INTERRUPT_STATUS);
  153. dbg_reg(dev, priv, CONTROLLER_STATUS);
  154. dbg_reg(dev, priv, FIFO_DATA);
  155. dbg_reg(dev, priv, ANALOG_CONTROL);
  156. dbg_reg(dev, priv, AUX_DATA);
  157. dbg_reg(dev, priv, DEBOUNCE_CNTR_STAT);
  158. dbg_reg(dev, priv, SCAN_CNTR_STAT);
  159. dbg_reg(dev, priv, REM_CNTR_STAT);
  160. dbg_reg(dev, priv, SETTLING_TIMER_STAT);
  161. dbg_reg(dev, priv, SPARE_REG);
  162. dbg_reg(dev, priv, SOFT_BYPASS_CONTROL);
  163. dbg_reg(dev, priv, SOFT_BYPASS_DATA);
  164. }
  165. static irqreturn_t iproc_touchscreen_interrupt(int irq, void *data)
  166. {
  167. struct platform_device *pdev = data;
  168. struct iproc_ts_priv *priv = platform_get_drvdata(pdev);
  169. u32 intr_status;
  170. u32 raw_coordinate;
  171. u16 x;
  172. u16 y;
  173. int i;
  174. bool needs_sync = false;
  175. regmap_read(priv->regmap, INTERRUPT_STATUS, &intr_status);
  176. intr_status &= TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK;
  177. if (intr_status == 0)
  178. return IRQ_NONE;
  179. /* Clear all interrupt status bits, write-1-clear */
  180. regmap_write(priv->regmap, INTERRUPT_STATUS, intr_status);
  181. /* Pen up/down */
  182. if (intr_status & TS_PEN_INTR_MASK) {
  183. regmap_read(priv->regmap, CONTROLLER_STATUS, &priv->pen_status);
  184. if (priv->pen_status & TS_PEN_DOWN)
  185. priv->pen_status = PEN_DOWN_STATUS;
  186. else
  187. priv->pen_status = PEN_UP_STATUS;
  188. input_report_key(priv->idev, BTN_TOUCH, priv->pen_status);
  189. needs_sync = true;
  190. dev_dbg(&priv->pdev->dev,
  191. "pen up-down (%d)\n", priv->pen_status);
  192. }
  193. /* coordinates in FIFO exceed the theshold */
  194. if (intr_status & TS_FIFO_INTR_MASK) {
  195. for (i = 0; i < priv->cfg_params.fifo_threshold; i++) {
  196. regmap_read(priv->regmap, FIFO_DATA, &raw_coordinate);
  197. if (raw_coordinate == INVALID_COORD)
  198. continue;
  199. /*
  200. * The x and y coordinate are 16 bits each
  201. * with the x in the lower 16 bits and y in the
  202. * upper 16 bits.
  203. */
  204. x = (raw_coordinate >> X_COORD_SHIFT) &
  205. FIFO_DATA_X_Y_MASK;
  206. y = (raw_coordinate >> Y_COORD_SHIFT) &
  207. FIFO_DATA_X_Y_MASK;
  208. /* We only want to retain the 12 msb of the 16 */
  209. x = (x >> 4) & 0x0FFF;
  210. y = (y >> 4) & 0x0FFF;
  211. /* Adjust x y according to LCD tsc mount angle. */
  212. if (priv->cfg_params.invert_x)
  213. x = priv->cfg_params.max_x - x;
  214. if (priv->cfg_params.invert_y)
  215. y = priv->cfg_params.max_y - y;
  216. input_report_abs(priv->idev, ABS_X, x);
  217. input_report_abs(priv->idev, ABS_Y, y);
  218. needs_sync = true;
  219. dev_dbg(&priv->pdev->dev, "xy (0x%x 0x%x)\n", x, y);
  220. }
  221. }
  222. if (needs_sync)
  223. input_sync(priv->idev);
  224. return IRQ_HANDLED;
  225. }
  226. static int iproc_ts_start(struct input_dev *idev)
  227. {
  228. u32 val;
  229. u32 mask;
  230. int error;
  231. struct iproc_ts_priv *priv = input_get_drvdata(idev);
  232. /* Enable clock */
  233. error = clk_prepare_enable(priv->tsc_clk);
  234. if (error) {
  235. dev_err(&priv->pdev->dev, "%s clk_prepare_enable failed %d\n",
  236. __func__, error);
  237. return error;
  238. }
  239. /*
  240. * Interrupt is generated when:
  241. * FIFO reaches the int_th value, and pen event(up/down)
  242. */
  243. val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK;
  244. regmap_update_bits(priv->regmap, INTERRUPT_MASK, val, val);
  245. val = priv->cfg_params.fifo_threshold;
  246. regmap_write(priv->regmap, INTERRUPT_THRES, val);
  247. /* Initialize control reg1 */
  248. val = 0;
  249. val |= priv->cfg_params.scanning_period << SCANNING_PERIOD_SHIFT;
  250. val |= priv->cfg_params.debounce_timeout << DEBOUNCE_TIMEOUT_SHIFT;
  251. val |= priv->cfg_params.settling_timeout << SETTLING_TIMEOUT_SHIFT;
  252. val |= priv->cfg_params.touch_timeout << TOUCH_TIMEOUT_SHIFT;
  253. regmap_write(priv->regmap, REGCTL1, val);
  254. /* Try to clear all interrupt status */
  255. val = TS_FIFO_INTR_MASK | TS_PEN_INTR_MASK;
  256. regmap_update_bits(priv->regmap, INTERRUPT_STATUS, val, val);
  257. /* Initialize control reg2 */
  258. val = TS_CONTROLLER_EN_BIT | TS_WIRE_MODE_BIT;
  259. val |= priv->cfg_params.average_data << TS_CONTROLLER_AVGDATA_SHIFT;
  260. mask = (TS_CONTROLLER_AVGDATA_MASK);
  261. mask |= (TS_CONTROLLER_PWR_LDO | /* PWR up LDO */
  262. TS_CONTROLLER_PWR_ADC | /* PWR up ADC */
  263. TS_CONTROLLER_PWR_BGP | /* PWR up BGP */
  264. TS_CONTROLLER_PWR_TS); /* PWR up TS */
  265. mask |= val;
  266. regmap_update_bits(priv->regmap, REGCTL2, mask, val);
  267. ts_reg_dump(priv);
  268. return 0;
  269. }
  270. static void iproc_ts_stop(struct input_dev *dev)
  271. {
  272. u32 val;
  273. struct iproc_ts_priv *priv = input_get_drvdata(dev);
  274. /*
  275. * Disable FIFO int_th and pen event(up/down)Interrupts only
  276. * as the interrupt mask register is shared between ADC, TS and
  277. * flextimer.
  278. */
  279. val = TS_PEN_INTR_MASK | TS_FIFO_INTR_MASK;
  280. regmap_update_bits(priv->regmap, INTERRUPT_MASK, val, 0);
  281. /* Only power down touch screen controller */
  282. val = TS_CONTROLLER_PWR_TS;
  283. regmap_update_bits(priv->regmap, REGCTL2, val, val);
  284. clk_disable(priv->tsc_clk);
  285. }
  286. static int iproc_get_tsc_config(struct device *dev, struct iproc_ts_priv *priv)
  287. {
  288. struct device_node *np = dev->of_node;
  289. u32 val;
  290. priv->cfg_params = iproc_default_config;
  291. if (!np)
  292. return 0;
  293. if (of_property_read_u32(np, "scanning_period", &val) >= 0) {
  294. if (val < 1 || val > 256) {
  295. dev_err(dev, "scanning_period (%u) must be [1-256]\n",
  296. val);
  297. return -EINVAL;
  298. }
  299. priv->cfg_params.scanning_period = val;
  300. }
  301. if (of_property_read_u32(np, "debounce_timeout", &val) >= 0) {
  302. if (val > 255) {
  303. dev_err(dev, "debounce_timeout (%u) must be [0-255]\n",
  304. val);
  305. return -EINVAL;
  306. }
  307. priv->cfg_params.debounce_timeout = val;
  308. }
  309. if (of_property_read_u32(np, "settling_timeout", &val) >= 0) {
  310. if (val > 11) {
  311. dev_err(dev, "settling_timeout (%u) must be [0-11]\n",
  312. val);
  313. return -EINVAL;
  314. }
  315. priv->cfg_params.settling_timeout = val;
  316. }
  317. if (of_property_read_u32(np, "touch_timeout", &val) >= 0) {
  318. if (val > 255) {
  319. dev_err(dev, "touch_timeout (%u) must be [0-255]\n",
  320. val);
  321. return -EINVAL;
  322. }
  323. priv->cfg_params.touch_timeout = val;
  324. }
  325. if (of_property_read_u32(np, "average_data", &val) >= 0) {
  326. if (val > 8) {
  327. dev_err(dev, "average_data (%u) must be [0-8]\n", val);
  328. return -EINVAL;
  329. }
  330. priv->cfg_params.average_data = val;
  331. }
  332. if (of_property_read_u32(np, "fifo_threshold", &val) >= 0) {
  333. if (val > 31) {
  334. dev_err(dev, "fifo_threshold (%u)) must be [0-31]\n",
  335. val);
  336. return -EINVAL;
  337. }
  338. priv->cfg_params.fifo_threshold = val;
  339. }
  340. /* Parse optional properties. */
  341. of_property_read_u32(np, "touchscreen-size-x", &priv->cfg_params.max_x);
  342. of_property_read_u32(np, "touchscreen-size-y", &priv->cfg_params.max_y);
  343. of_property_read_u32(np, "touchscreen-fuzz-x",
  344. &priv->cfg_params.fuzz_x);
  345. of_property_read_u32(np, "touchscreen-fuzz-y",
  346. &priv->cfg_params.fuzz_y);
  347. priv->cfg_params.invert_x =
  348. of_property_read_bool(np, "touchscreen-inverted-x");
  349. priv->cfg_params.invert_y =
  350. of_property_read_bool(np, "touchscreen-inverted-y");
  351. return 0;
  352. }
  353. static int iproc_ts_probe(struct platform_device *pdev)
  354. {
  355. struct iproc_ts_priv *priv;
  356. struct input_dev *idev;
  357. int irq;
  358. int error;
  359. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  360. if (!priv)
  361. return -ENOMEM;
  362. /* touchscreen controller memory mapped regs via syscon*/
  363. priv->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  364. "ts_syscon");
  365. if (IS_ERR(priv->regmap)) {
  366. error = PTR_ERR(priv->regmap);
  367. dev_err(&pdev->dev, "unable to map I/O memory:%d\n", error);
  368. return error;
  369. }
  370. priv->tsc_clk = devm_clk_get(&pdev->dev, "tsc_clk");
  371. if (IS_ERR(priv->tsc_clk)) {
  372. error = PTR_ERR(priv->tsc_clk);
  373. dev_err(&pdev->dev,
  374. "failed getting clock tsc_clk: %d\n", error);
  375. return error;
  376. }
  377. priv->pdev = pdev;
  378. error = iproc_get_tsc_config(&pdev->dev, priv);
  379. if (error) {
  380. dev_err(&pdev->dev, "get_tsc_config failed: %d\n", error);
  381. return error;
  382. }
  383. idev = devm_input_allocate_device(&pdev->dev);
  384. if (!idev) {
  385. dev_err(&pdev->dev, "failed to allocate input device\n");
  386. return -ENOMEM;
  387. }
  388. priv->idev = idev;
  389. priv->pen_status = PEN_UP_STATUS;
  390. /* Set input device info */
  391. idev->name = IPROC_TS_NAME;
  392. idev->dev.parent = &pdev->dev;
  393. idev->id.bustype = BUS_HOST;
  394. idev->id.vendor = SERIO_UNKNOWN;
  395. idev->id.product = 0;
  396. idev->id.version = 0;
  397. idev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
  398. __set_bit(BTN_TOUCH, idev->keybit);
  399. input_set_abs_params(idev, ABS_X, X_MIN, priv->cfg_params.max_x,
  400. priv->cfg_params.fuzz_x, 0);
  401. input_set_abs_params(idev, ABS_Y, Y_MIN, priv->cfg_params.max_y,
  402. priv->cfg_params.fuzz_y, 0);
  403. idev->open = iproc_ts_start;
  404. idev->close = iproc_ts_stop;
  405. input_set_drvdata(idev, priv);
  406. platform_set_drvdata(pdev, priv);
  407. /* get interrupt */
  408. irq = platform_get_irq(pdev, 0);
  409. if (irq < 0) {
  410. dev_err(&pdev->dev, "platform_get_irq failed: %d\n", irq);
  411. return irq;
  412. }
  413. error = devm_request_irq(&pdev->dev, irq,
  414. iproc_touchscreen_interrupt,
  415. IRQF_SHARED, IPROC_TS_NAME, pdev);
  416. if (error)
  417. return error;
  418. error = input_register_device(priv->idev);
  419. if (error) {
  420. dev_err(&pdev->dev,
  421. "failed to register input device: %d\n", error);
  422. return error;
  423. }
  424. return 0;
  425. }
  426. static const struct of_device_id iproc_ts_of_match[] = {
  427. {.compatible = "brcm,iproc-touchscreen", },
  428. { },
  429. };
  430. MODULE_DEVICE_TABLE(of, iproc_ts_of_match);
  431. static struct platform_driver iproc_ts_driver = {
  432. .probe = iproc_ts_probe,
  433. .driver = {
  434. .name = IPROC_TS_NAME,
  435. .of_match_table = of_match_ptr(iproc_ts_of_match),
  436. },
  437. };
  438. module_platform_driver(iproc_ts_driver);
  439. MODULE_DESCRIPTION("IPROC Touchscreen driver");
  440. MODULE_AUTHOR("Broadcom");
  441. MODULE_LICENSE("GPL v2");