sun4i_dotclock.c 4.2 KB

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  1. /*
  2. * Copyright (C) 2016 Free Electrons
  3. * Copyright (C) 2016 NextThing Co
  4. *
  5. * Maxime Ripard <maxime.ripard@free-electrons.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. */
  12. #include <linux/clk-provider.h>
  13. #include <linux/regmap.h>
  14. #include "sun4i_tcon.h"
  15. #include "sun4i_dotclock.h"
  16. struct sun4i_dclk {
  17. struct clk_hw hw;
  18. struct regmap *regmap;
  19. };
  20. static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw)
  21. {
  22. return container_of(hw, struct sun4i_dclk, hw);
  23. }
  24. static void sun4i_dclk_disable(struct clk_hw *hw)
  25. {
  26. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  27. regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  28. BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0);
  29. }
  30. static int sun4i_dclk_enable(struct clk_hw *hw)
  31. {
  32. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  33. return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  34. BIT(SUN4I_TCON0_DCLK_GATE_BIT),
  35. BIT(SUN4I_TCON0_DCLK_GATE_BIT));
  36. }
  37. static int sun4i_dclk_is_enabled(struct clk_hw *hw)
  38. {
  39. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  40. u32 val;
  41. regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
  42. return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT);
  43. }
  44. static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
  45. unsigned long parent_rate)
  46. {
  47. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  48. u32 val;
  49. regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
  50. val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
  51. val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;
  52. if (!val)
  53. val = 1;
  54. return parent_rate / val;
  55. }
  56. static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
  57. unsigned long *parent_rate)
  58. {
  59. unsigned long best_parent = 0;
  60. u8 best_div = 1;
  61. int i;
  62. for (i = 6; i <= 127; i++) {
  63. unsigned long ideal = rate * i;
  64. unsigned long rounded;
  65. rounded = clk_hw_round_rate(clk_hw_get_parent(hw),
  66. ideal);
  67. if (rounded == ideal) {
  68. best_parent = rounded;
  69. best_div = i;
  70. goto out;
  71. }
  72. if (abs(rate - rounded / i) <
  73. abs(rate - best_parent / best_div)) {
  74. best_parent = rounded;
  75. best_div = i;
  76. }
  77. }
  78. out:
  79. *parent_rate = best_parent;
  80. return best_parent / best_div;
  81. }
  82. static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
  83. unsigned long parent_rate)
  84. {
  85. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  86. u8 div = parent_rate / rate;
  87. return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
  88. GENMASK(6, 0), div);
  89. }
  90. static int sun4i_dclk_get_phase(struct clk_hw *hw)
  91. {
  92. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  93. u32 val;
  94. regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val);
  95. val >>= 28;
  96. val &= 3;
  97. return val * 120;
  98. }
  99. static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
  100. {
  101. struct sun4i_dclk *dclk = hw_to_dclk(hw);
  102. u32 val = degrees / 120;
  103. val <<= 28;
  104. regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
  105. GENMASK(29, 28),
  106. val);
  107. return 0;
  108. }
  109. static const struct clk_ops sun4i_dclk_ops = {
  110. .disable = sun4i_dclk_disable,
  111. .enable = sun4i_dclk_enable,
  112. .is_enabled = sun4i_dclk_is_enabled,
  113. .recalc_rate = sun4i_dclk_recalc_rate,
  114. .round_rate = sun4i_dclk_round_rate,
  115. .set_rate = sun4i_dclk_set_rate,
  116. .get_phase = sun4i_dclk_get_phase,
  117. .set_phase = sun4i_dclk_set_phase,
  118. };
  119. int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon)
  120. {
  121. const char *clk_name, *parent_name;
  122. struct clk_init_data init;
  123. struct sun4i_dclk *dclk;
  124. int ret;
  125. parent_name = __clk_get_name(tcon->sclk0);
  126. ret = of_property_read_string_index(dev->of_node,
  127. "clock-output-names", 0,
  128. &clk_name);
  129. if (ret)
  130. return ret;
  131. dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
  132. if (!dclk)
  133. return -ENOMEM;
  134. init.name = clk_name;
  135. init.ops = &sun4i_dclk_ops;
  136. init.parent_names = &parent_name;
  137. init.num_parents = 1;
  138. init.flags = CLK_SET_RATE_PARENT;
  139. dclk->regmap = tcon->regs;
  140. dclk->hw.init = &init;
  141. tcon->dclk = clk_register(dev, &dclk->hw);
  142. if (IS_ERR(tcon->dclk))
  143. return PTR_ERR(tcon->dclk);
  144. return 0;
  145. }
  146. EXPORT_SYMBOL(sun4i_dclk_create);
  147. int sun4i_dclk_free(struct sun4i_tcon *tcon)
  148. {
  149. clk_unregister(tcon->dclk);
  150. return 0;
  151. }
  152. EXPORT_SYMBOL(sun4i_dclk_free);