mtk_drm_drv.c 14 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Author: YT SHEN <yt.shen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <drm/drmP.h>
  15. #include <drm/drm_atomic.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include <drm/drm_gem.h>
  19. #include <drm/drm_gem_cma_helper.h>
  20. #include <linux/component.h>
  21. #include <linux/iommu.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/pm_runtime.h>
  25. #include "mtk_drm_crtc.h"
  26. #include "mtk_drm_ddp.h"
  27. #include "mtk_drm_ddp_comp.h"
  28. #include "mtk_drm_drv.h"
  29. #include "mtk_drm_fb.h"
  30. #include "mtk_drm_gem.h"
  31. #define DRIVER_NAME "mediatek"
  32. #define DRIVER_DESC "Mediatek SoC DRM"
  33. #define DRIVER_DATE "20150513"
  34. #define DRIVER_MAJOR 1
  35. #define DRIVER_MINOR 0
  36. static void mtk_atomic_schedule(struct mtk_drm_private *private,
  37. struct drm_atomic_state *state)
  38. {
  39. private->commit.state = state;
  40. schedule_work(&private->commit.work);
  41. }
  42. static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
  43. {
  44. struct drm_plane *plane;
  45. struct drm_plane_state *plane_state;
  46. int i;
  47. for_each_plane_in_state(state, plane, plane_state, i)
  48. mtk_fb_wait(plane->state->fb);
  49. }
  50. static void mtk_atomic_complete(struct mtk_drm_private *private,
  51. struct drm_atomic_state *state)
  52. {
  53. struct drm_device *drm = private->drm;
  54. mtk_atomic_wait_for_fences(state);
  55. /*
  56. * Mediatek drm supports runtime PM, so plane registers cannot be
  57. * written when their crtc is disabled.
  58. *
  59. * The comment for drm_atomic_helper_commit states:
  60. * For drivers supporting runtime PM the recommended sequence is
  61. *
  62. * drm_atomic_helper_commit_modeset_disables(dev, state);
  63. * drm_atomic_helper_commit_modeset_enables(dev, state);
  64. * drm_atomic_helper_commit_planes(dev, state,
  65. * DRM_PLANE_COMMIT_ACTIVE_ONLY);
  66. *
  67. * See the kerneldoc entries for these three functions for more details.
  68. */
  69. drm_atomic_helper_commit_modeset_disables(drm, state);
  70. drm_atomic_helper_commit_modeset_enables(drm, state);
  71. drm_atomic_helper_commit_planes(drm, state,
  72. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  73. drm_atomic_helper_wait_for_vblanks(drm, state);
  74. drm_atomic_helper_cleanup_planes(drm, state);
  75. drm_atomic_state_free(state);
  76. }
  77. static void mtk_atomic_work(struct work_struct *work)
  78. {
  79. struct mtk_drm_private *private = container_of(work,
  80. struct mtk_drm_private, commit.work);
  81. mtk_atomic_complete(private, private->commit.state);
  82. }
  83. static int mtk_atomic_commit(struct drm_device *drm,
  84. struct drm_atomic_state *state,
  85. bool async)
  86. {
  87. struct mtk_drm_private *private = drm->dev_private;
  88. int ret;
  89. ret = drm_atomic_helper_prepare_planes(drm, state);
  90. if (ret)
  91. return ret;
  92. mutex_lock(&private->commit.lock);
  93. flush_work(&private->commit.work);
  94. drm_atomic_helper_swap_state(state, true);
  95. if (async)
  96. mtk_atomic_schedule(private, state);
  97. else
  98. mtk_atomic_complete(private, state);
  99. mutex_unlock(&private->commit.lock);
  100. return 0;
  101. }
  102. static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  103. .fb_create = mtk_drm_mode_fb_create,
  104. .atomic_check = drm_atomic_helper_check,
  105. .atomic_commit = mtk_atomic_commit,
  106. };
  107. static const enum mtk_ddp_comp_id mtk_ddp_main[] = {
  108. DDP_COMPONENT_OVL0,
  109. DDP_COMPONENT_COLOR0,
  110. DDP_COMPONENT_AAL,
  111. DDP_COMPONENT_OD,
  112. DDP_COMPONENT_RDMA0,
  113. DDP_COMPONENT_UFOE,
  114. DDP_COMPONENT_DSI0,
  115. DDP_COMPONENT_PWM0,
  116. };
  117. static const enum mtk_ddp_comp_id mtk_ddp_ext[] = {
  118. DDP_COMPONENT_OVL1,
  119. DDP_COMPONENT_COLOR1,
  120. DDP_COMPONENT_GAMMA,
  121. DDP_COMPONENT_RDMA1,
  122. DDP_COMPONENT_DPI0,
  123. };
  124. static int mtk_drm_kms_init(struct drm_device *drm)
  125. {
  126. struct mtk_drm_private *private = drm->dev_private;
  127. struct platform_device *pdev;
  128. struct device_node *np;
  129. int ret;
  130. if (!iommu_present(&platform_bus_type))
  131. return -EPROBE_DEFER;
  132. pdev = of_find_device_by_node(private->mutex_node);
  133. if (!pdev) {
  134. dev_err(drm->dev, "Waiting for disp-mutex device %s\n",
  135. private->mutex_node->full_name);
  136. of_node_put(private->mutex_node);
  137. return -EPROBE_DEFER;
  138. }
  139. private->mutex_dev = &pdev->dev;
  140. drm_mode_config_init(drm);
  141. drm->mode_config.min_width = 64;
  142. drm->mode_config.min_height = 64;
  143. /*
  144. * set max width and height as default value(4096x4096).
  145. * this value would be used to check framebuffer size limitation
  146. * at drm_mode_addfb().
  147. */
  148. drm->mode_config.max_width = 4096;
  149. drm->mode_config.max_height = 4096;
  150. drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
  151. ret = component_bind_all(drm->dev, drm);
  152. if (ret)
  153. goto err_config_cleanup;
  154. /*
  155. * We currently support two fixed data streams, each optional,
  156. * and each statically assigned to a crtc:
  157. * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
  158. */
  159. ret = mtk_drm_crtc_create(drm, mtk_ddp_main, ARRAY_SIZE(mtk_ddp_main));
  160. if (ret < 0)
  161. goto err_component_unbind;
  162. /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
  163. ret = mtk_drm_crtc_create(drm, mtk_ddp_ext, ARRAY_SIZE(mtk_ddp_ext));
  164. if (ret < 0)
  165. goto err_component_unbind;
  166. /* Use OVL device for all DMA memory allocations */
  167. np = private->comp_node[mtk_ddp_main[0]] ?:
  168. private->comp_node[mtk_ddp_ext[0]];
  169. pdev = of_find_device_by_node(np);
  170. if (!pdev) {
  171. ret = -ENODEV;
  172. dev_err(drm->dev, "Need at least one OVL device\n");
  173. goto err_component_unbind;
  174. }
  175. private->dma_dev = &pdev->dev;
  176. /*
  177. * We don't use the drm_irq_install() helpers provided by the DRM
  178. * core, so we need to set this manually in order to allow the
  179. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  180. */
  181. drm->irq_enabled = true;
  182. ret = drm_vblank_init(drm, MAX_CRTC);
  183. if (ret < 0)
  184. goto err_component_unbind;
  185. drm_kms_helper_poll_init(drm);
  186. drm_mode_config_reset(drm);
  187. return 0;
  188. err_component_unbind:
  189. component_unbind_all(drm->dev, drm);
  190. err_config_cleanup:
  191. drm_mode_config_cleanup(drm);
  192. return ret;
  193. }
  194. static void mtk_drm_kms_deinit(struct drm_device *drm)
  195. {
  196. drm_kms_helper_poll_fini(drm);
  197. drm_vblank_cleanup(drm);
  198. component_unbind_all(drm->dev, drm);
  199. drm_mode_config_cleanup(drm);
  200. }
  201. static const struct file_operations mtk_drm_fops = {
  202. .owner = THIS_MODULE,
  203. .open = drm_open,
  204. .release = drm_release,
  205. .unlocked_ioctl = drm_ioctl,
  206. .mmap = mtk_drm_gem_mmap,
  207. .poll = drm_poll,
  208. .read = drm_read,
  209. #ifdef CONFIG_COMPAT
  210. .compat_ioctl = drm_compat_ioctl,
  211. #endif
  212. };
  213. static struct drm_driver mtk_drm_driver = {
  214. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  215. DRIVER_ATOMIC,
  216. .get_vblank_counter = drm_vblank_count,
  217. .enable_vblank = mtk_drm_crtc_enable_vblank,
  218. .disable_vblank = mtk_drm_crtc_disable_vblank,
  219. .gem_free_object_unlocked = mtk_drm_gem_free_object,
  220. .gem_vm_ops = &drm_gem_cma_vm_ops,
  221. .dumb_create = mtk_drm_gem_dumb_create,
  222. .dumb_map_offset = mtk_drm_gem_dumb_map_offset,
  223. .dumb_destroy = drm_gem_dumb_destroy,
  224. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  225. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  226. .gem_prime_export = drm_gem_prime_export,
  227. .gem_prime_import = drm_gem_prime_import,
  228. .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
  229. .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
  230. .gem_prime_mmap = mtk_drm_gem_mmap_buf,
  231. .fops = &mtk_drm_fops,
  232. .name = DRIVER_NAME,
  233. .desc = DRIVER_DESC,
  234. .date = DRIVER_DATE,
  235. .major = DRIVER_MAJOR,
  236. .minor = DRIVER_MINOR,
  237. };
  238. static int compare_of(struct device *dev, void *data)
  239. {
  240. return dev->of_node == data;
  241. }
  242. static int mtk_drm_bind(struct device *dev)
  243. {
  244. struct mtk_drm_private *private = dev_get_drvdata(dev);
  245. struct drm_device *drm;
  246. int ret;
  247. drm = drm_dev_alloc(&mtk_drm_driver, dev);
  248. if (IS_ERR(drm))
  249. return PTR_ERR(drm);
  250. drm->dev_private = private;
  251. private->drm = drm;
  252. ret = mtk_drm_kms_init(drm);
  253. if (ret < 0)
  254. goto err_free;
  255. ret = drm_dev_register(drm, 0);
  256. if (ret < 0)
  257. goto err_deinit;
  258. return 0;
  259. err_deinit:
  260. mtk_drm_kms_deinit(drm);
  261. err_free:
  262. drm_dev_unref(drm);
  263. return ret;
  264. }
  265. static void mtk_drm_unbind(struct device *dev)
  266. {
  267. struct mtk_drm_private *private = dev_get_drvdata(dev);
  268. drm_dev_unregister(private->drm);
  269. drm_dev_unref(private->drm);
  270. private->drm = NULL;
  271. }
  272. static const struct component_master_ops mtk_drm_ops = {
  273. .bind = mtk_drm_bind,
  274. .unbind = mtk_drm_unbind,
  275. };
  276. static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  277. { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL },
  278. { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA },
  279. { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA },
  280. { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR },
  281. { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL},
  282. { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, },
  283. { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE },
  284. { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
  285. { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
  286. { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
  287. { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
  288. { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD },
  289. { }
  290. };
  291. static int mtk_drm_probe(struct platform_device *pdev)
  292. {
  293. struct device *dev = &pdev->dev;
  294. struct mtk_drm_private *private;
  295. struct resource *mem;
  296. struct device_node *node;
  297. struct component_match *match = NULL;
  298. int ret;
  299. int i;
  300. private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
  301. if (!private)
  302. return -ENOMEM;
  303. mutex_init(&private->commit.lock);
  304. INIT_WORK(&private->commit.work, mtk_atomic_work);
  305. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  306. private->config_regs = devm_ioremap_resource(dev, mem);
  307. if (IS_ERR(private->config_regs)) {
  308. ret = PTR_ERR(private->config_regs);
  309. dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
  310. ret);
  311. return ret;
  312. }
  313. /* Iterate over sibling DISP function blocks */
  314. for_each_child_of_node(dev->of_node->parent, node) {
  315. const struct of_device_id *of_id;
  316. enum mtk_ddp_comp_type comp_type;
  317. int comp_id;
  318. of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
  319. if (!of_id)
  320. continue;
  321. if (!of_device_is_available(node)) {
  322. dev_dbg(dev, "Skipping disabled component %s\n",
  323. node->full_name);
  324. continue;
  325. }
  326. comp_type = (enum mtk_ddp_comp_type)of_id->data;
  327. if (comp_type == MTK_DISP_MUTEX) {
  328. private->mutex_node = of_node_get(node);
  329. continue;
  330. }
  331. comp_id = mtk_ddp_comp_get_id(node, comp_type);
  332. if (comp_id < 0) {
  333. dev_warn(dev, "Skipping unknown component %s\n",
  334. node->full_name);
  335. continue;
  336. }
  337. private->comp_node[comp_id] = of_node_get(node);
  338. /*
  339. * Currently only the OVL, RDMA, DSI, and DPI blocks have
  340. * separate component platform drivers and initialize their own
  341. * DDP component structure. The others are initialized here.
  342. */
  343. if (comp_type == MTK_DISP_OVL ||
  344. comp_type == MTK_DISP_RDMA ||
  345. comp_type == MTK_DSI ||
  346. comp_type == MTK_DPI) {
  347. dev_info(dev, "Adding component match for %s\n",
  348. node->full_name);
  349. component_match_add(dev, &match, compare_of, node);
  350. } else {
  351. struct mtk_ddp_comp *comp;
  352. comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
  353. if (!comp) {
  354. ret = -ENOMEM;
  355. goto err_node;
  356. }
  357. ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
  358. if (ret)
  359. goto err_node;
  360. private->ddp_comp[comp_id] = comp;
  361. }
  362. }
  363. if (!private->mutex_node) {
  364. dev_err(dev, "Failed to find disp-mutex node\n");
  365. ret = -ENODEV;
  366. goto err_node;
  367. }
  368. pm_runtime_enable(dev);
  369. platform_set_drvdata(pdev, private);
  370. ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
  371. if (ret)
  372. goto err_pm;
  373. return 0;
  374. err_pm:
  375. pm_runtime_disable(dev);
  376. err_node:
  377. of_node_put(private->mutex_node);
  378. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  379. of_node_put(private->comp_node[i]);
  380. return ret;
  381. }
  382. static int mtk_drm_remove(struct platform_device *pdev)
  383. {
  384. struct mtk_drm_private *private = platform_get_drvdata(pdev);
  385. struct drm_device *drm = private->drm;
  386. int i;
  387. drm_dev_unregister(drm);
  388. mtk_drm_kms_deinit(drm);
  389. drm_dev_unref(drm);
  390. component_master_del(&pdev->dev, &mtk_drm_ops);
  391. pm_runtime_disable(&pdev->dev);
  392. of_node_put(private->mutex_node);
  393. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  394. of_node_put(private->comp_node[i]);
  395. return 0;
  396. }
  397. #ifdef CONFIG_PM_SLEEP
  398. static int mtk_drm_sys_suspend(struct device *dev)
  399. {
  400. struct mtk_drm_private *private = dev_get_drvdata(dev);
  401. struct drm_device *drm = private->drm;
  402. drm_kms_helper_poll_disable(drm);
  403. private->suspend_state = drm_atomic_helper_suspend(drm);
  404. if (IS_ERR(private->suspend_state)) {
  405. drm_kms_helper_poll_enable(drm);
  406. return PTR_ERR(private->suspend_state);
  407. }
  408. DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
  409. return 0;
  410. }
  411. static int mtk_drm_sys_resume(struct device *dev)
  412. {
  413. struct mtk_drm_private *private = dev_get_drvdata(dev);
  414. struct drm_device *drm = private->drm;
  415. drm_atomic_helper_resume(drm, private->suspend_state);
  416. drm_kms_helper_poll_enable(drm);
  417. DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
  418. return 0;
  419. }
  420. #endif
  421. static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
  422. mtk_drm_sys_resume);
  423. static const struct of_device_id mtk_drm_of_ids[] = {
  424. { .compatible = "mediatek,mt8173-mmsys", },
  425. { }
  426. };
  427. static struct platform_driver mtk_drm_platform_driver = {
  428. .probe = mtk_drm_probe,
  429. .remove = mtk_drm_remove,
  430. .driver = {
  431. .name = "mediatek-drm",
  432. .of_match_table = mtk_drm_of_ids,
  433. .pm = &mtk_drm_pm_ops,
  434. },
  435. };
  436. static struct platform_driver * const mtk_drm_drivers[] = {
  437. &mtk_ddp_driver,
  438. &mtk_disp_ovl_driver,
  439. &mtk_disp_rdma_driver,
  440. &mtk_dpi_driver,
  441. &mtk_drm_platform_driver,
  442. &mtk_dsi_driver,
  443. &mtk_mipi_tx_driver,
  444. };
  445. static int __init mtk_drm_init(void)
  446. {
  447. int ret;
  448. int i;
  449. for (i = 0; i < ARRAY_SIZE(mtk_drm_drivers); i++) {
  450. ret = platform_driver_register(mtk_drm_drivers[i]);
  451. if (ret < 0) {
  452. pr_err("Failed to register %s driver: %d\n",
  453. mtk_drm_drivers[i]->driver.name, ret);
  454. goto err;
  455. }
  456. }
  457. return 0;
  458. err:
  459. while (--i >= 0)
  460. platform_driver_unregister(mtk_drm_drivers[i]);
  461. return ret;
  462. }
  463. static void __exit mtk_drm_exit(void)
  464. {
  465. int i;
  466. for (i = ARRAY_SIZE(mtk_drm_drivers) - 1; i >= 0; i--)
  467. platform_driver_unregister(mtk_drm_drivers[i]);
  468. }
  469. module_init(mtk_drm_init);
  470. module_exit(mtk_drm_exit);
  471. MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
  472. MODULE_DESCRIPTION("Mediatek SoC DRM driver");
  473. MODULE_LICENSE("GPL v2");