drm_edid.c 130 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440
  1. /*
  2. * Copyright (c) 2006 Luc Verhaegen (quirks list)
  3. * Copyright (c) 2007-2008 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. * Copyright 2010 Red Hat, Inc.
  6. *
  7. * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
  8. * FB layer.
  9. * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice (including the
  19. * next paragraph) shall be included in all copies or substantial portions
  20. * of the Software.
  21. *
  22. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28. * DEALINGS IN THE SOFTWARE.
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/hdmi.h>
  33. #include <linux/i2c.h>
  34. #include <linux/module.h>
  35. #include <linux/vga_switcheroo.h>
  36. #include <drm/drmP.h>
  37. #include <drm/drm_edid.h>
  38. #include <drm/drm_displayid.h>
  39. #define version_greater(edid, maj, min) \
  40. (((edid)->version > (maj)) || \
  41. ((edid)->version == (maj) && (edid)->revision > (min)))
  42. #define EDID_EST_TIMINGS 16
  43. #define EDID_STD_TIMINGS 8
  44. #define EDID_DETAILED_TIMINGS 4
  45. /*
  46. * EDID blocks out in the wild have a variety of bugs, try to collect
  47. * them here (note that userspace may work around broken monitors first,
  48. * but fixes should make their way here so that the kernel "just works"
  49. * on as many displays as possible).
  50. */
  51. /* First detailed mode wrong, use largest 60Hz mode */
  52. #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
  53. /* Reported 135MHz pixel clock is too high, needs adjustment */
  54. #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
  55. /* Prefer the largest mode at 75 Hz */
  56. #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
  57. /* Detail timing is in cm not mm */
  58. #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
  59. /* Detailed timing descriptors have bogus size values, so just take the
  60. * maximum size and use that.
  61. */
  62. #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
  63. /* Monitor forgot to set the first detailed is preferred bit. */
  64. #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
  65. /* use +hsync +vsync for detailed mode */
  66. #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
  67. /* Force reduced-blanking timings for detailed modes */
  68. #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
  69. /* Force 8bpc */
  70. #define EDID_QUIRK_FORCE_8BPC (1 << 8)
  71. /* Force 12bpc */
  72. #define EDID_QUIRK_FORCE_12BPC (1 << 9)
  73. /* Force 6bpc */
  74. #define EDID_QUIRK_FORCE_6BPC (1 << 10)
  75. /* Force 10bpc */
  76. #define EDID_QUIRK_FORCE_10BPC (1 << 11)
  77. struct detailed_mode_closure {
  78. struct drm_connector *connector;
  79. struct edid *edid;
  80. bool preferred;
  81. u32 quirks;
  82. int modes;
  83. };
  84. #define LEVEL_DMT 0
  85. #define LEVEL_GTF 1
  86. #define LEVEL_GTF2 2
  87. #define LEVEL_CVT 3
  88. static const struct edid_quirk {
  89. char vendor[4];
  90. int product_id;
  91. u32 quirks;
  92. } edid_quirk_list[] = {
  93. /* Acer AL1706 */
  94. { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
  95. /* Acer F51 */
  96. { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
  97. /* Unknown Acer */
  98. { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
  99. /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
  100. { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
  101. /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
  102. { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
  103. /* Belinea 10 15 55 */
  104. { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
  105. { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
  106. /* Envision Peripherals, Inc. EN-7100e */
  107. { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
  108. /* Envision EN2028 */
  109. { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
  110. /* Funai Electronics PM36B */
  111. { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
  112. EDID_QUIRK_DETAILED_IN_CM },
  113. /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
  114. { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
  115. /* LG Philips LCD LP154W01-A5 */
  116. { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
  117. { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
  118. /* Philips 107p5 CRT */
  119. { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
  120. /* Proview AY765C */
  121. { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
  122. /* Samsung SyncMaster 205BW. Note: irony */
  123. { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
  124. /* Samsung SyncMaster 22[5-6]BW */
  125. { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
  126. { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
  127. /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
  128. { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
  129. /* ViewSonic VA2026w */
  130. { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
  131. /* Medion MD 30217 PG */
  132. { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
  133. /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
  134. { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
  135. /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
  136. { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
  137. };
  138. /*
  139. * Autogenerated from the DMT spec.
  140. * This table is copied from xfree86/modes/xf86EdidModes.c.
  141. */
  142. static const struct drm_display_mode drm_dmt_modes[] = {
  143. /* 0x01 - 640x350@85Hz */
  144. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
  145. 736, 832, 0, 350, 382, 385, 445, 0,
  146. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  147. /* 0x02 - 640x400@85Hz */
  148. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
  149. 736, 832, 0, 400, 401, 404, 445, 0,
  150. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  151. /* 0x03 - 720x400@85Hz */
  152. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
  153. 828, 936, 0, 400, 401, 404, 446, 0,
  154. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  155. /* 0x04 - 640x480@60Hz */
  156. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  157. 752, 800, 0, 480, 490, 492, 525, 0,
  158. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  159. /* 0x05 - 640x480@72Hz */
  160. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
  161. 704, 832, 0, 480, 489, 492, 520, 0,
  162. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  163. /* 0x06 - 640x480@75Hz */
  164. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
  165. 720, 840, 0, 480, 481, 484, 500, 0,
  166. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  167. /* 0x07 - 640x480@85Hz */
  168. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
  169. 752, 832, 0, 480, 481, 484, 509, 0,
  170. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  171. /* 0x08 - 800x600@56Hz */
  172. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
  173. 896, 1024, 0, 600, 601, 603, 625, 0,
  174. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  175. /* 0x09 - 800x600@60Hz */
  176. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  177. 968, 1056, 0, 600, 601, 605, 628, 0,
  178. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  179. /* 0x0a - 800x600@72Hz */
  180. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
  181. 976, 1040, 0, 600, 637, 643, 666, 0,
  182. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  183. /* 0x0b - 800x600@75Hz */
  184. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
  185. 896, 1056, 0, 600, 601, 604, 625, 0,
  186. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  187. /* 0x0c - 800x600@85Hz */
  188. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
  189. 896, 1048, 0, 600, 601, 604, 631, 0,
  190. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  191. /* 0x0d - 800x600@120Hz RB */
  192. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
  193. 880, 960, 0, 600, 603, 607, 636, 0,
  194. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  195. /* 0x0e - 848x480@60Hz */
  196. { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
  197. 976, 1088, 0, 480, 486, 494, 517, 0,
  198. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  199. /* 0x0f - 1024x768@43Hz, interlace */
  200. { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
  201. 1208, 1264, 0, 768, 768, 776, 817, 0,
  202. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  203. DRM_MODE_FLAG_INTERLACE) },
  204. /* 0x10 - 1024x768@60Hz */
  205. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  206. 1184, 1344, 0, 768, 771, 777, 806, 0,
  207. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  208. /* 0x11 - 1024x768@70Hz */
  209. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
  210. 1184, 1328, 0, 768, 771, 777, 806, 0,
  211. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  212. /* 0x12 - 1024x768@75Hz */
  213. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
  214. 1136, 1312, 0, 768, 769, 772, 800, 0,
  215. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  216. /* 0x13 - 1024x768@85Hz */
  217. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
  218. 1168, 1376, 0, 768, 769, 772, 808, 0,
  219. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  220. /* 0x14 - 1024x768@120Hz RB */
  221. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
  222. 1104, 1184, 0, 768, 771, 775, 813, 0,
  223. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  224. /* 0x15 - 1152x864@75Hz */
  225. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  226. 1344, 1600, 0, 864, 865, 868, 900, 0,
  227. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  228. /* 0x55 - 1280x720@60Hz */
  229. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
  230. 1430, 1650, 0, 720, 725, 730, 750, 0,
  231. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  232. /* 0x16 - 1280x768@60Hz RB */
  233. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
  234. 1360, 1440, 0, 768, 771, 778, 790, 0,
  235. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  236. /* 0x17 - 1280x768@60Hz */
  237. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  238. 1472, 1664, 0, 768, 771, 778, 798, 0,
  239. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  240. /* 0x18 - 1280x768@75Hz */
  241. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
  242. 1488, 1696, 0, 768, 771, 778, 805, 0,
  243. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  244. /* 0x19 - 1280x768@85Hz */
  245. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
  246. 1496, 1712, 0, 768, 771, 778, 809, 0,
  247. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  248. /* 0x1a - 1280x768@120Hz RB */
  249. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
  250. 1360, 1440, 0, 768, 771, 778, 813, 0,
  251. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  252. /* 0x1b - 1280x800@60Hz RB */
  253. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
  254. 1360, 1440, 0, 800, 803, 809, 823, 0,
  255. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  256. /* 0x1c - 1280x800@60Hz */
  257. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  258. 1480, 1680, 0, 800, 803, 809, 831, 0,
  259. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  260. /* 0x1d - 1280x800@75Hz */
  261. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
  262. 1488, 1696, 0, 800, 803, 809, 838, 0,
  263. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  264. /* 0x1e - 1280x800@85Hz */
  265. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
  266. 1496, 1712, 0, 800, 803, 809, 843, 0,
  267. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  268. /* 0x1f - 1280x800@120Hz RB */
  269. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
  270. 1360, 1440, 0, 800, 803, 809, 847, 0,
  271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  272. /* 0x20 - 1280x960@60Hz */
  273. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  274. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  275. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  276. /* 0x21 - 1280x960@85Hz */
  277. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
  278. 1504, 1728, 0, 960, 961, 964, 1011, 0,
  279. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  280. /* 0x22 - 1280x960@120Hz RB */
  281. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
  282. 1360, 1440, 0, 960, 963, 967, 1017, 0,
  283. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  284. /* 0x23 - 1280x1024@60Hz */
  285. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  286. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  287. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  288. /* 0x24 - 1280x1024@75Hz */
  289. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
  290. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  291. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  292. /* 0x25 - 1280x1024@85Hz */
  293. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
  294. 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
  295. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  296. /* 0x26 - 1280x1024@120Hz RB */
  297. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
  298. 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
  299. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  300. /* 0x27 - 1360x768@60Hz */
  301. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  302. 1536, 1792, 0, 768, 771, 777, 795, 0,
  303. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  304. /* 0x28 - 1360x768@120Hz RB */
  305. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
  306. 1440, 1520, 0, 768, 771, 776, 813, 0,
  307. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  308. /* 0x51 - 1366x768@60Hz */
  309. { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
  310. 1579, 1792, 0, 768, 771, 774, 798, 0,
  311. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  312. /* 0x56 - 1366x768@60Hz */
  313. { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
  314. 1436, 1500, 0, 768, 769, 772, 800, 0,
  315. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  316. /* 0x29 - 1400x1050@60Hz RB */
  317. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
  318. 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
  319. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  320. /* 0x2a - 1400x1050@60Hz */
  321. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  322. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  323. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  324. /* 0x2b - 1400x1050@75Hz */
  325. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
  326. 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
  327. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  328. /* 0x2c - 1400x1050@85Hz */
  329. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
  330. 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
  331. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  332. /* 0x2d - 1400x1050@120Hz RB */
  333. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
  334. 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
  335. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  336. /* 0x2e - 1440x900@60Hz RB */
  337. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
  338. 1520, 1600, 0, 900, 903, 909, 926, 0,
  339. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  340. /* 0x2f - 1440x900@60Hz */
  341. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  342. 1672, 1904, 0, 900, 903, 909, 934, 0,
  343. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  344. /* 0x30 - 1440x900@75Hz */
  345. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
  346. 1688, 1936, 0, 900, 903, 909, 942, 0,
  347. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  348. /* 0x31 - 1440x900@85Hz */
  349. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
  350. 1696, 1952, 0, 900, 903, 909, 948, 0,
  351. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  352. /* 0x32 - 1440x900@120Hz RB */
  353. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
  354. 1520, 1600, 0, 900, 903, 909, 953, 0,
  355. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  356. /* 0x53 - 1600x900@60Hz */
  357. { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
  358. 1704, 1800, 0, 900, 901, 904, 1000, 0,
  359. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  360. /* 0x33 - 1600x1200@60Hz */
  361. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  362. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  363. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  364. /* 0x34 - 1600x1200@65Hz */
  365. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
  366. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  367. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  368. /* 0x35 - 1600x1200@70Hz */
  369. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
  370. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  371. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  372. /* 0x36 - 1600x1200@75Hz */
  373. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
  374. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  375. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  376. /* 0x37 - 1600x1200@85Hz */
  377. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
  378. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  379. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  380. /* 0x38 - 1600x1200@120Hz RB */
  381. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
  382. 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
  383. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  384. /* 0x39 - 1680x1050@60Hz RB */
  385. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
  386. 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
  387. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  388. /* 0x3a - 1680x1050@60Hz */
  389. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  390. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  391. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  392. /* 0x3b - 1680x1050@75Hz */
  393. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
  394. 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
  395. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  396. /* 0x3c - 1680x1050@85Hz */
  397. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
  398. 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
  399. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  400. /* 0x3d - 1680x1050@120Hz RB */
  401. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
  402. 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
  403. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  404. /* 0x3e - 1792x1344@60Hz */
  405. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  406. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  407. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  408. /* 0x3f - 1792x1344@75Hz */
  409. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
  410. 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
  411. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  412. /* 0x40 - 1792x1344@120Hz RB */
  413. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
  414. 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
  415. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  416. /* 0x41 - 1856x1392@60Hz */
  417. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  418. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  419. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  420. /* 0x42 - 1856x1392@75Hz */
  421. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
  422. 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
  423. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  424. /* 0x43 - 1856x1392@120Hz RB */
  425. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
  426. 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
  427. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  428. /* 0x52 - 1920x1080@60Hz */
  429. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  430. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  431. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  432. /* 0x44 - 1920x1200@60Hz RB */
  433. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
  434. 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
  435. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  436. /* 0x45 - 1920x1200@60Hz */
  437. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  438. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  439. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  440. /* 0x46 - 1920x1200@75Hz */
  441. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
  442. 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
  443. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  444. /* 0x47 - 1920x1200@85Hz */
  445. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
  446. 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
  447. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  448. /* 0x48 - 1920x1200@120Hz RB */
  449. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
  450. 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
  451. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  452. /* 0x49 - 1920x1440@60Hz */
  453. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  454. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  455. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  456. /* 0x4a - 1920x1440@75Hz */
  457. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
  458. 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
  459. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  460. /* 0x4b - 1920x1440@120Hz RB */
  461. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
  462. 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
  463. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  464. /* 0x54 - 2048x1152@60Hz */
  465. { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
  466. 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
  467. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  468. /* 0x4c - 2560x1600@60Hz RB */
  469. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
  470. 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
  471. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  472. /* 0x4d - 2560x1600@60Hz */
  473. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  474. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  475. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  476. /* 0x4e - 2560x1600@75Hz */
  477. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
  478. 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
  479. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  480. /* 0x4f - 2560x1600@85Hz */
  481. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
  482. 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
  483. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  484. /* 0x50 - 2560x1600@120Hz RB */
  485. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
  486. 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
  487. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  488. /* 0x57 - 4096x2160@60Hz RB */
  489. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
  490. 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
  491. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  492. /* 0x58 - 4096x2160@59.94Hz RB */
  493. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
  494. 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
  495. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  496. };
  497. /*
  498. * These more or less come from the DMT spec. The 720x400 modes are
  499. * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
  500. * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
  501. * should be 1152x870, again for the Mac, but instead we use the x864 DMT
  502. * mode.
  503. *
  504. * The DMT modes have been fact-checked; the rest are mild guesses.
  505. */
  506. static const struct drm_display_mode edid_est_modes[] = {
  507. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  508. 968, 1056, 0, 600, 601, 605, 628, 0,
  509. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
  510. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
  511. 896, 1024, 0, 600, 601, 603, 625, 0,
  512. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
  513. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
  514. 720, 840, 0, 480, 481, 484, 500, 0,
  515. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
  516. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
  517. 704, 832, 0, 480, 489, 492, 520, 0,
  518. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
  519. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
  520. 768, 864, 0, 480, 483, 486, 525, 0,
  521. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
  522. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  523. 752, 800, 0, 480, 490, 492, 525, 0,
  524. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
  525. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
  526. 846, 900, 0, 400, 421, 423, 449, 0,
  527. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
  528. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
  529. 846, 900, 0, 400, 412, 414, 449, 0,
  530. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
  531. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
  532. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  533. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
  534. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
  535. 1136, 1312, 0, 768, 769, 772, 800, 0,
  536. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
  537. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
  538. 1184, 1328, 0, 768, 771, 777, 806, 0,
  539. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
  540. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  541. 1184, 1344, 0, 768, 771, 777, 806, 0,
  542. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
  543. { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
  544. 1208, 1264, 0, 768, 768, 776, 817, 0,
  545. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
  546. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
  547. 928, 1152, 0, 624, 625, 628, 667, 0,
  548. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
  549. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
  550. 896, 1056, 0, 600, 601, 604, 625, 0,
  551. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
  552. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
  553. 976, 1040, 0, 600, 637, 643, 666, 0,
  554. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
  555. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  556. 1344, 1600, 0, 864, 865, 868, 900, 0,
  557. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
  558. };
  559. struct minimode {
  560. short w;
  561. short h;
  562. short r;
  563. short rb;
  564. };
  565. static const struct minimode est3_modes[] = {
  566. /* byte 6 */
  567. { 640, 350, 85, 0 },
  568. { 640, 400, 85, 0 },
  569. { 720, 400, 85, 0 },
  570. { 640, 480, 85, 0 },
  571. { 848, 480, 60, 0 },
  572. { 800, 600, 85, 0 },
  573. { 1024, 768, 85, 0 },
  574. { 1152, 864, 75, 0 },
  575. /* byte 7 */
  576. { 1280, 768, 60, 1 },
  577. { 1280, 768, 60, 0 },
  578. { 1280, 768, 75, 0 },
  579. { 1280, 768, 85, 0 },
  580. { 1280, 960, 60, 0 },
  581. { 1280, 960, 85, 0 },
  582. { 1280, 1024, 60, 0 },
  583. { 1280, 1024, 85, 0 },
  584. /* byte 8 */
  585. { 1360, 768, 60, 0 },
  586. { 1440, 900, 60, 1 },
  587. { 1440, 900, 60, 0 },
  588. { 1440, 900, 75, 0 },
  589. { 1440, 900, 85, 0 },
  590. { 1400, 1050, 60, 1 },
  591. { 1400, 1050, 60, 0 },
  592. { 1400, 1050, 75, 0 },
  593. /* byte 9 */
  594. { 1400, 1050, 85, 0 },
  595. { 1680, 1050, 60, 1 },
  596. { 1680, 1050, 60, 0 },
  597. { 1680, 1050, 75, 0 },
  598. { 1680, 1050, 85, 0 },
  599. { 1600, 1200, 60, 0 },
  600. { 1600, 1200, 65, 0 },
  601. { 1600, 1200, 70, 0 },
  602. /* byte 10 */
  603. { 1600, 1200, 75, 0 },
  604. { 1600, 1200, 85, 0 },
  605. { 1792, 1344, 60, 0 },
  606. { 1792, 1344, 75, 0 },
  607. { 1856, 1392, 60, 0 },
  608. { 1856, 1392, 75, 0 },
  609. { 1920, 1200, 60, 1 },
  610. { 1920, 1200, 60, 0 },
  611. /* byte 11 */
  612. { 1920, 1200, 75, 0 },
  613. { 1920, 1200, 85, 0 },
  614. { 1920, 1440, 60, 0 },
  615. { 1920, 1440, 75, 0 },
  616. };
  617. static const struct minimode extra_modes[] = {
  618. { 1024, 576, 60, 0 },
  619. { 1366, 768, 60, 0 },
  620. { 1600, 900, 60, 0 },
  621. { 1680, 945, 60, 0 },
  622. { 1920, 1080, 60, 0 },
  623. { 2048, 1152, 60, 0 },
  624. { 2048, 1536, 60, 0 },
  625. };
  626. /*
  627. * Probably taken from CEA-861 spec.
  628. * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
  629. *
  630. * Index using the VIC.
  631. */
  632. static const struct drm_display_mode edid_cea_modes[] = {
  633. /* 0 - dummy, VICs start at 1 */
  634. { },
  635. /* 1 - 640x480@60Hz */
  636. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  637. 752, 800, 0, 480, 490, 492, 525, 0,
  638. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  639. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  640. /* 2 - 720x480@60Hz */
  641. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
  642. 798, 858, 0, 480, 489, 495, 525, 0,
  643. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  644. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  645. /* 3 - 720x480@60Hz */
  646. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
  647. 798, 858, 0, 480, 489, 495, 525, 0,
  648. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  649. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  650. /* 4 - 1280x720@60Hz */
  651. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
  652. 1430, 1650, 0, 720, 725, 730, 750, 0,
  653. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  654. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  655. /* 5 - 1920x1080i@60Hz */
  656. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
  657. 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
  658. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  659. DRM_MODE_FLAG_INTERLACE),
  660. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  661. /* 6 - 720(1440)x480i@60Hz */
  662. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  663. 801, 858, 0, 480, 488, 494, 525, 0,
  664. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  665. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  666. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  667. /* 7 - 720(1440)x480i@60Hz */
  668. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  669. 801, 858, 0, 480, 488, 494, 525, 0,
  670. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  671. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  672. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  673. /* 8 - 720(1440)x240@60Hz */
  674. { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  675. 801, 858, 0, 240, 244, 247, 262, 0,
  676. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  677. DRM_MODE_FLAG_DBLCLK),
  678. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  679. /* 9 - 720(1440)x240@60Hz */
  680. { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
  681. 801, 858, 0, 240, 244, 247, 262, 0,
  682. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  683. DRM_MODE_FLAG_DBLCLK),
  684. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  685. /* 10 - 2880x480i@60Hz */
  686. { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  687. 3204, 3432, 0, 480, 488, 494, 525, 0,
  688. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  689. DRM_MODE_FLAG_INTERLACE),
  690. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  691. /* 11 - 2880x480i@60Hz */
  692. { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  693. 3204, 3432, 0, 480, 488, 494, 525, 0,
  694. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  695. DRM_MODE_FLAG_INTERLACE),
  696. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  697. /* 12 - 2880x240@60Hz */
  698. { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  699. 3204, 3432, 0, 240, 244, 247, 262, 0,
  700. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  701. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  702. /* 13 - 2880x240@60Hz */
  703. { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
  704. 3204, 3432, 0, 240, 244, 247, 262, 0,
  705. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  706. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  707. /* 14 - 1440x480@60Hz */
  708. { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
  709. 1596, 1716, 0, 480, 489, 495, 525, 0,
  710. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  711. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  712. /* 15 - 1440x480@60Hz */
  713. { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
  714. 1596, 1716, 0, 480, 489, 495, 525, 0,
  715. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  716. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  717. /* 16 - 1920x1080@60Hz */
  718. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  719. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  720. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  721. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  722. /* 17 - 720x576@50Hz */
  723. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  724. 796, 864, 0, 576, 581, 586, 625, 0,
  725. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  726. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  727. /* 18 - 720x576@50Hz */
  728. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  729. 796, 864, 0, 576, 581, 586, 625, 0,
  730. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  731. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  732. /* 19 - 1280x720@50Hz */
  733. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
  734. 1760, 1980, 0, 720, 725, 730, 750, 0,
  735. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  736. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  737. /* 20 - 1920x1080i@50Hz */
  738. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
  739. 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
  740. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  741. DRM_MODE_FLAG_INTERLACE),
  742. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  743. /* 21 - 720(1440)x576i@50Hz */
  744. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  745. 795, 864, 0, 576, 580, 586, 625, 0,
  746. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  747. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  748. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  749. /* 22 - 720(1440)x576i@50Hz */
  750. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  751. 795, 864, 0, 576, 580, 586, 625, 0,
  752. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  753. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  754. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  755. /* 23 - 720(1440)x288@50Hz */
  756. { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  757. 795, 864, 0, 288, 290, 293, 312, 0,
  758. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  759. DRM_MODE_FLAG_DBLCLK),
  760. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  761. /* 24 - 720(1440)x288@50Hz */
  762. { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
  763. 795, 864, 0, 288, 290, 293, 312, 0,
  764. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  765. DRM_MODE_FLAG_DBLCLK),
  766. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  767. /* 25 - 2880x576i@50Hz */
  768. { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  769. 3180, 3456, 0, 576, 580, 586, 625, 0,
  770. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  771. DRM_MODE_FLAG_INTERLACE),
  772. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  773. /* 26 - 2880x576i@50Hz */
  774. { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  775. 3180, 3456, 0, 576, 580, 586, 625, 0,
  776. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  777. DRM_MODE_FLAG_INTERLACE),
  778. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  779. /* 27 - 2880x288@50Hz */
  780. { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  781. 3180, 3456, 0, 288, 290, 293, 312, 0,
  782. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  783. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  784. /* 28 - 2880x288@50Hz */
  785. { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
  786. 3180, 3456, 0, 288, 290, 293, 312, 0,
  787. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  788. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  789. /* 29 - 1440x576@50Hz */
  790. { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
  791. 1592, 1728, 0, 576, 581, 586, 625, 0,
  792. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  793. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  794. /* 30 - 1440x576@50Hz */
  795. { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
  796. 1592, 1728, 0, 576, 581, 586, 625, 0,
  797. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  798. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  799. /* 31 - 1920x1080@50Hz */
  800. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
  801. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  802. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  803. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  804. /* 32 - 1920x1080@24Hz */
  805. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
  806. 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
  807. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  808. .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  809. /* 33 - 1920x1080@25Hz */
  810. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
  811. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  812. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  813. .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  814. /* 34 - 1920x1080@30Hz */
  815. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
  816. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  817. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  818. .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  819. /* 35 - 2880x480@60Hz */
  820. { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
  821. 3192, 3432, 0, 480, 489, 495, 525, 0,
  822. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  823. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  824. /* 36 - 2880x480@60Hz */
  825. { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
  826. 3192, 3432, 0, 480, 489, 495, 525, 0,
  827. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  828. .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  829. /* 37 - 2880x576@50Hz */
  830. { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
  831. 3184, 3456, 0, 576, 581, 586, 625, 0,
  832. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  833. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  834. /* 38 - 2880x576@50Hz */
  835. { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
  836. 3184, 3456, 0, 576, 581, 586, 625, 0,
  837. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  838. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  839. /* 39 - 1920x1080i@50Hz */
  840. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
  841. 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
  842. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
  843. DRM_MODE_FLAG_INTERLACE),
  844. .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  845. /* 40 - 1920x1080i@100Hz */
  846. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
  847. 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
  848. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  849. DRM_MODE_FLAG_INTERLACE),
  850. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  851. /* 41 - 1280x720@100Hz */
  852. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
  853. 1760, 1980, 0, 720, 725, 730, 750, 0,
  854. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  855. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  856. /* 42 - 720x576@100Hz */
  857. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  858. 796, 864, 0, 576, 581, 586, 625, 0,
  859. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  860. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  861. /* 43 - 720x576@100Hz */
  862. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  863. 796, 864, 0, 576, 581, 586, 625, 0,
  864. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  865. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  866. /* 44 - 720(1440)x576i@100Hz */
  867. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  868. 795, 864, 0, 576, 580, 586, 625, 0,
  869. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  870. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  871. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  872. /* 45 - 720(1440)x576i@100Hz */
  873. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
  874. 795, 864, 0, 576, 580, 586, 625, 0,
  875. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  876. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  877. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  878. /* 46 - 1920x1080i@120Hz */
  879. { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
  880. 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
  881. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
  882. DRM_MODE_FLAG_INTERLACE),
  883. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  884. /* 47 - 1280x720@120Hz */
  885. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
  886. 1430, 1650, 0, 720, 725, 730, 750, 0,
  887. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  888. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  889. /* 48 - 720x480@120Hz */
  890. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
  891. 798, 858, 0, 480, 489, 495, 525, 0,
  892. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  893. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  894. /* 49 - 720x480@120Hz */
  895. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
  896. 798, 858, 0, 480, 489, 495, 525, 0,
  897. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  898. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  899. /* 50 - 720(1440)x480i@120Hz */
  900. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
  901. 801, 858, 0, 480, 488, 494, 525, 0,
  902. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  903. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  904. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  905. /* 51 - 720(1440)x480i@120Hz */
  906. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
  907. 801, 858, 0, 480, 488, 494, 525, 0,
  908. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  909. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  910. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  911. /* 52 - 720x576@200Hz */
  912. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
  913. 796, 864, 0, 576, 581, 586, 625, 0,
  914. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  915. .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  916. /* 53 - 720x576@200Hz */
  917. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
  918. 796, 864, 0, 576, 581, 586, 625, 0,
  919. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  920. .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  921. /* 54 - 720(1440)x576i@200Hz */
  922. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  923. 795, 864, 0, 576, 580, 586, 625, 0,
  924. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  925. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  926. .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  927. /* 55 - 720(1440)x576i@200Hz */
  928. { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
  929. 795, 864, 0, 576, 580, 586, 625, 0,
  930. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  931. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  932. .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  933. /* 56 - 720x480@240Hz */
  934. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
  935. 798, 858, 0, 480, 489, 495, 525, 0,
  936. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  937. .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  938. /* 57 - 720x480@240Hz */
  939. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
  940. 798, 858, 0, 480, 489, 495, 525, 0,
  941. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  942. .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  943. /* 58 - 720(1440)x480i@240 */
  944. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
  945. 801, 858, 0, 480, 488, 494, 525, 0,
  946. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  947. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  948. .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
  949. /* 59 - 720(1440)x480i@240 */
  950. { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
  951. 801, 858, 0, 480, 488, 494, 525, 0,
  952. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
  953. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
  954. .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  955. /* 60 - 1280x720@24Hz */
  956. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
  957. 3080, 3300, 0, 720, 725, 730, 750, 0,
  958. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  959. .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  960. /* 61 - 1280x720@25Hz */
  961. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
  962. 3740, 3960, 0, 720, 725, 730, 750, 0,
  963. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  964. .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  965. /* 62 - 1280x720@30Hz */
  966. { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
  967. 3080, 3300, 0, 720, 725, 730, 750, 0,
  968. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  969. .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  970. /* 63 - 1920x1080@120Hz */
  971. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
  972. 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
  973. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  974. .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  975. /* 64 - 1920x1080@100Hz */
  976. { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
  977. 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
  978. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  979. .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
  980. };
  981. /*
  982. * HDMI 1.4 4k modes. Index using the VIC.
  983. */
  984. static const struct drm_display_mode edid_4k_modes[] = {
  985. /* 0 - dummy, VICs start at 1 */
  986. { },
  987. /* 1 - 3840x2160@30Hz */
  988. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
  989. 3840, 4016, 4104, 4400, 0,
  990. 2160, 2168, 2178, 2250, 0,
  991. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  992. .vrefresh = 30, },
  993. /* 2 - 3840x2160@25Hz */
  994. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
  995. 3840, 4896, 4984, 5280, 0,
  996. 2160, 2168, 2178, 2250, 0,
  997. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  998. .vrefresh = 25, },
  999. /* 3 - 3840x2160@24Hz */
  1000. { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
  1001. 3840, 5116, 5204, 5500, 0,
  1002. 2160, 2168, 2178, 2250, 0,
  1003. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1004. .vrefresh = 24, },
  1005. /* 4 - 4096x2160@24Hz (SMPTE) */
  1006. { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
  1007. 4096, 5116, 5204, 5500, 0,
  1008. 2160, 2168, 2178, 2250, 0,
  1009. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
  1010. .vrefresh = 24, },
  1011. };
  1012. /*** DDC fetch and block validation ***/
  1013. static const u8 edid_header[] = {
  1014. 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
  1015. };
  1016. /**
  1017. * drm_edid_header_is_valid - sanity check the header of the base EDID block
  1018. * @raw_edid: pointer to raw base EDID block
  1019. *
  1020. * Sanity check the header of the base EDID block.
  1021. *
  1022. * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
  1023. */
  1024. int drm_edid_header_is_valid(const u8 *raw_edid)
  1025. {
  1026. int i, score = 0;
  1027. for (i = 0; i < sizeof(edid_header); i++)
  1028. if (raw_edid[i] == edid_header[i])
  1029. score++;
  1030. return score;
  1031. }
  1032. EXPORT_SYMBOL(drm_edid_header_is_valid);
  1033. static int edid_fixup __read_mostly = 6;
  1034. module_param_named(edid_fixup, edid_fixup, int, 0400);
  1035. MODULE_PARM_DESC(edid_fixup,
  1036. "Minimum number of valid EDID header bytes (0-8, default 6)");
  1037. static void drm_get_displayid(struct drm_connector *connector,
  1038. struct edid *edid);
  1039. static int drm_edid_block_checksum(const u8 *raw_edid)
  1040. {
  1041. int i;
  1042. u8 csum = 0;
  1043. for (i = 0; i < EDID_LENGTH; i++)
  1044. csum += raw_edid[i];
  1045. return csum;
  1046. }
  1047. static bool drm_edid_is_zero(const u8 *in_edid, int length)
  1048. {
  1049. if (memchr_inv(in_edid, 0, length))
  1050. return false;
  1051. return true;
  1052. }
  1053. /**
  1054. * drm_edid_block_valid - Sanity check the EDID block (base or extension)
  1055. * @raw_edid: pointer to raw EDID block
  1056. * @block: type of block to validate (0 for base, extension otherwise)
  1057. * @print_bad_edid: if true, dump bad EDID blocks to the console
  1058. * @edid_corrupt: if true, the header or checksum is invalid
  1059. *
  1060. * Validate a base or extension EDID block and optionally dump bad blocks to
  1061. * the console.
  1062. *
  1063. * Return: True if the block is valid, false otherwise.
  1064. */
  1065. bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
  1066. bool *edid_corrupt)
  1067. {
  1068. u8 csum;
  1069. struct edid *edid = (struct edid *)raw_edid;
  1070. if (WARN_ON(!raw_edid))
  1071. return false;
  1072. if (edid_fixup > 8 || edid_fixup < 0)
  1073. edid_fixup = 6;
  1074. if (block == 0) {
  1075. int score = drm_edid_header_is_valid(raw_edid);
  1076. if (score == 8) {
  1077. if (edid_corrupt)
  1078. *edid_corrupt = false;
  1079. } else if (score >= edid_fixup) {
  1080. /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
  1081. * The corrupt flag needs to be set here otherwise, the
  1082. * fix-up code here will correct the problem, the
  1083. * checksum is correct and the test fails
  1084. */
  1085. if (edid_corrupt)
  1086. *edid_corrupt = true;
  1087. DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
  1088. memcpy(raw_edid, edid_header, sizeof(edid_header));
  1089. } else {
  1090. if (edid_corrupt)
  1091. *edid_corrupt = true;
  1092. goto bad;
  1093. }
  1094. }
  1095. csum = drm_edid_block_checksum(raw_edid);
  1096. if (csum) {
  1097. if (print_bad_edid) {
  1098. DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
  1099. }
  1100. if (edid_corrupt)
  1101. *edid_corrupt = true;
  1102. /* allow CEA to slide through, switches mangle this */
  1103. if (raw_edid[0] != 0x02)
  1104. goto bad;
  1105. }
  1106. /* per-block-type checks */
  1107. switch (raw_edid[0]) {
  1108. case 0: /* base */
  1109. if (edid->version != 1) {
  1110. DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
  1111. goto bad;
  1112. }
  1113. if (edid->revision > 4)
  1114. DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
  1115. break;
  1116. default:
  1117. break;
  1118. }
  1119. return true;
  1120. bad:
  1121. if (print_bad_edid) {
  1122. if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
  1123. printk(KERN_ERR "EDID block is all zeroes\n");
  1124. } else {
  1125. printk(KERN_ERR "Raw EDID:\n");
  1126. print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
  1127. raw_edid, EDID_LENGTH, false);
  1128. }
  1129. }
  1130. return false;
  1131. }
  1132. EXPORT_SYMBOL(drm_edid_block_valid);
  1133. /**
  1134. * drm_edid_is_valid - sanity check EDID data
  1135. * @edid: EDID data
  1136. *
  1137. * Sanity-check an entire EDID record (including extensions)
  1138. *
  1139. * Return: True if the EDID data is valid, false otherwise.
  1140. */
  1141. bool drm_edid_is_valid(struct edid *edid)
  1142. {
  1143. int i;
  1144. u8 *raw = (u8 *)edid;
  1145. if (!edid)
  1146. return false;
  1147. for (i = 0; i <= edid->extensions; i++)
  1148. if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
  1149. return false;
  1150. return true;
  1151. }
  1152. EXPORT_SYMBOL(drm_edid_is_valid);
  1153. #define DDC_SEGMENT_ADDR 0x30
  1154. /**
  1155. * drm_do_probe_ddc_edid() - get EDID information via I2C
  1156. * @data: I2C device adapter
  1157. * @buf: EDID data buffer to be filled
  1158. * @block: 128 byte EDID block to start fetching from
  1159. * @len: EDID data buffer length to fetch
  1160. *
  1161. * Try to fetch EDID information by calling I2C driver functions.
  1162. *
  1163. * Return: 0 on success or -1 on failure.
  1164. */
  1165. static int
  1166. drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
  1167. {
  1168. struct i2c_adapter *adapter = data;
  1169. unsigned char start = block * EDID_LENGTH;
  1170. unsigned char segment = block >> 1;
  1171. unsigned char xfers = segment ? 3 : 2;
  1172. int ret, retries = 5;
  1173. /*
  1174. * The core I2C driver will automatically retry the transfer if the
  1175. * adapter reports EAGAIN. However, we find that bit-banging transfers
  1176. * are susceptible to errors under a heavily loaded machine and
  1177. * generate spurious NAKs and timeouts. Retrying the transfer
  1178. * of the individual block a few times seems to overcome this.
  1179. */
  1180. do {
  1181. struct i2c_msg msgs[] = {
  1182. {
  1183. .addr = DDC_SEGMENT_ADDR,
  1184. .flags = 0,
  1185. .len = 1,
  1186. .buf = &segment,
  1187. }, {
  1188. .addr = DDC_ADDR,
  1189. .flags = 0,
  1190. .len = 1,
  1191. .buf = &start,
  1192. }, {
  1193. .addr = DDC_ADDR,
  1194. .flags = I2C_M_RD,
  1195. .len = len,
  1196. .buf = buf,
  1197. }
  1198. };
  1199. /*
  1200. * Avoid sending the segment addr to not upset non-compliant
  1201. * DDC monitors.
  1202. */
  1203. ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
  1204. if (ret == -ENXIO) {
  1205. DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
  1206. adapter->name);
  1207. break;
  1208. }
  1209. } while (ret != xfers && --retries);
  1210. return ret == xfers ? 0 : -1;
  1211. }
  1212. /**
  1213. * drm_do_get_edid - get EDID data using a custom EDID block read function
  1214. * @connector: connector we're probing
  1215. * @get_edid_block: EDID block read function
  1216. * @data: private data passed to the block read function
  1217. *
  1218. * When the I2C adapter connected to the DDC bus is hidden behind a device that
  1219. * exposes a different interface to read EDID blocks this function can be used
  1220. * to get EDID data using a custom block read function.
  1221. *
  1222. * As in the general case the DDC bus is accessible by the kernel at the I2C
  1223. * level, drivers must make all reasonable efforts to expose it as an I2C
  1224. * adapter and use drm_get_edid() instead of abusing this function.
  1225. *
  1226. * Return: Pointer to valid EDID or NULL if we couldn't find any.
  1227. */
  1228. struct edid *drm_do_get_edid(struct drm_connector *connector,
  1229. int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
  1230. size_t len),
  1231. void *data)
  1232. {
  1233. int i, j = 0, valid_extensions = 0;
  1234. u8 *block, *new;
  1235. bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
  1236. if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
  1237. return NULL;
  1238. /* base block fetch */
  1239. for (i = 0; i < 4; i++) {
  1240. if (get_edid_block(data, block, 0, EDID_LENGTH))
  1241. goto out;
  1242. if (drm_edid_block_valid(block, 0, print_bad_edid,
  1243. &connector->edid_corrupt))
  1244. break;
  1245. if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
  1246. connector->null_edid_counter++;
  1247. goto carp;
  1248. }
  1249. }
  1250. if (i == 4)
  1251. goto carp;
  1252. /* if there's no extensions, we're done */
  1253. if (block[0x7e] == 0)
  1254. return (struct edid *)block;
  1255. new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
  1256. if (!new)
  1257. goto out;
  1258. block = new;
  1259. for (j = 1; j <= block[0x7e]; j++) {
  1260. for (i = 0; i < 4; i++) {
  1261. if (get_edid_block(data,
  1262. block + (valid_extensions + 1) * EDID_LENGTH,
  1263. j, EDID_LENGTH))
  1264. goto out;
  1265. if (drm_edid_block_valid(block + (valid_extensions + 1)
  1266. * EDID_LENGTH, j,
  1267. print_bad_edid,
  1268. NULL)) {
  1269. valid_extensions++;
  1270. break;
  1271. }
  1272. }
  1273. if (i == 4 && print_bad_edid) {
  1274. dev_warn(connector->dev->dev,
  1275. "%s: Ignoring invalid EDID block %d.\n",
  1276. connector->name, j);
  1277. connector->bad_edid_counter++;
  1278. }
  1279. }
  1280. if (valid_extensions != block[0x7e]) {
  1281. block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
  1282. block[0x7e] = valid_extensions;
  1283. new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
  1284. if (!new)
  1285. goto out;
  1286. block = new;
  1287. }
  1288. return (struct edid *)block;
  1289. carp:
  1290. if (print_bad_edid) {
  1291. dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
  1292. connector->name, j);
  1293. }
  1294. connector->bad_edid_counter++;
  1295. out:
  1296. kfree(block);
  1297. return NULL;
  1298. }
  1299. EXPORT_SYMBOL_GPL(drm_do_get_edid);
  1300. /**
  1301. * drm_probe_ddc() - probe DDC presence
  1302. * @adapter: I2C adapter to probe
  1303. *
  1304. * Return: True on success, false on failure.
  1305. */
  1306. bool
  1307. drm_probe_ddc(struct i2c_adapter *adapter)
  1308. {
  1309. unsigned char out;
  1310. return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
  1311. }
  1312. EXPORT_SYMBOL(drm_probe_ddc);
  1313. /**
  1314. * drm_get_edid - get EDID data, if available
  1315. * @connector: connector we're probing
  1316. * @adapter: I2C adapter to use for DDC
  1317. *
  1318. * Poke the given I2C channel to grab EDID data if possible. If found,
  1319. * attach it to the connector.
  1320. *
  1321. * Return: Pointer to valid EDID or NULL if we couldn't find any.
  1322. */
  1323. struct edid *drm_get_edid(struct drm_connector *connector,
  1324. struct i2c_adapter *adapter)
  1325. {
  1326. struct edid *edid;
  1327. if (!drm_probe_ddc(adapter))
  1328. return NULL;
  1329. edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
  1330. if (edid)
  1331. drm_get_displayid(connector, edid);
  1332. return edid;
  1333. }
  1334. EXPORT_SYMBOL(drm_get_edid);
  1335. /**
  1336. * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
  1337. * @connector: connector we're probing
  1338. * @adapter: I2C adapter to use for DDC
  1339. *
  1340. * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
  1341. * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
  1342. * switch DDC to the GPU which is retrieving EDID.
  1343. *
  1344. * Return: Pointer to valid EDID or %NULL if we couldn't find any.
  1345. */
  1346. struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
  1347. struct i2c_adapter *adapter)
  1348. {
  1349. struct pci_dev *pdev = connector->dev->pdev;
  1350. struct edid *edid;
  1351. vga_switcheroo_lock_ddc(pdev);
  1352. edid = drm_get_edid(connector, adapter);
  1353. vga_switcheroo_unlock_ddc(pdev);
  1354. return edid;
  1355. }
  1356. EXPORT_SYMBOL(drm_get_edid_switcheroo);
  1357. /**
  1358. * drm_edid_duplicate - duplicate an EDID and the extensions
  1359. * @edid: EDID to duplicate
  1360. *
  1361. * Return: Pointer to duplicated EDID or NULL on allocation failure.
  1362. */
  1363. struct edid *drm_edid_duplicate(const struct edid *edid)
  1364. {
  1365. return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
  1366. }
  1367. EXPORT_SYMBOL(drm_edid_duplicate);
  1368. /*** EDID parsing ***/
  1369. /**
  1370. * edid_vendor - match a string against EDID's obfuscated vendor field
  1371. * @edid: EDID to match
  1372. * @vendor: vendor string
  1373. *
  1374. * Returns true if @vendor is in @edid, false otherwise
  1375. */
  1376. static bool edid_vendor(struct edid *edid, const char *vendor)
  1377. {
  1378. char edid_vendor[3];
  1379. edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
  1380. edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
  1381. ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
  1382. edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
  1383. return !strncmp(edid_vendor, vendor, 3);
  1384. }
  1385. /**
  1386. * edid_get_quirks - return quirk flags for a given EDID
  1387. * @edid: EDID to process
  1388. *
  1389. * This tells subsequent routines what fixes they need to apply.
  1390. */
  1391. static u32 edid_get_quirks(struct edid *edid)
  1392. {
  1393. const struct edid_quirk *quirk;
  1394. int i;
  1395. for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
  1396. quirk = &edid_quirk_list[i];
  1397. if (edid_vendor(edid, quirk->vendor) &&
  1398. (EDID_PRODUCT_ID(edid) == quirk->product_id))
  1399. return quirk->quirks;
  1400. }
  1401. return 0;
  1402. }
  1403. #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
  1404. #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
  1405. /**
  1406. * edid_fixup_preferred - set preferred modes based on quirk list
  1407. * @connector: has mode list to fix up
  1408. * @quirks: quirks list
  1409. *
  1410. * Walk the mode list for @connector, clearing the preferred status
  1411. * on existing modes and setting it anew for the right mode ala @quirks.
  1412. */
  1413. static void edid_fixup_preferred(struct drm_connector *connector,
  1414. u32 quirks)
  1415. {
  1416. struct drm_display_mode *t, *cur_mode, *preferred_mode;
  1417. int target_refresh = 0;
  1418. int cur_vrefresh, preferred_vrefresh;
  1419. if (list_empty(&connector->probed_modes))
  1420. return;
  1421. if (quirks & EDID_QUIRK_PREFER_LARGE_60)
  1422. target_refresh = 60;
  1423. if (quirks & EDID_QUIRK_PREFER_LARGE_75)
  1424. target_refresh = 75;
  1425. preferred_mode = list_first_entry(&connector->probed_modes,
  1426. struct drm_display_mode, head);
  1427. list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
  1428. cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
  1429. if (cur_mode == preferred_mode)
  1430. continue;
  1431. /* Largest mode is preferred */
  1432. if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
  1433. preferred_mode = cur_mode;
  1434. cur_vrefresh = cur_mode->vrefresh ?
  1435. cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
  1436. preferred_vrefresh = preferred_mode->vrefresh ?
  1437. preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
  1438. /* At a given size, try to get closest to target refresh */
  1439. if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
  1440. MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
  1441. MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
  1442. preferred_mode = cur_mode;
  1443. }
  1444. }
  1445. preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
  1446. }
  1447. static bool
  1448. mode_is_rb(const struct drm_display_mode *mode)
  1449. {
  1450. return (mode->htotal - mode->hdisplay == 160) &&
  1451. (mode->hsync_end - mode->hdisplay == 80) &&
  1452. (mode->hsync_end - mode->hsync_start == 32) &&
  1453. (mode->vsync_start - mode->vdisplay == 3);
  1454. }
  1455. /*
  1456. * drm_mode_find_dmt - Create a copy of a mode if present in DMT
  1457. * @dev: Device to duplicate against
  1458. * @hsize: Mode width
  1459. * @vsize: Mode height
  1460. * @fresh: Mode refresh rate
  1461. * @rb: Mode reduced-blanking-ness
  1462. *
  1463. * Walk the DMT mode list looking for a match for the given parameters.
  1464. *
  1465. * Return: A newly allocated copy of the mode, or NULL if not found.
  1466. */
  1467. struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
  1468. int hsize, int vsize, int fresh,
  1469. bool rb)
  1470. {
  1471. int i;
  1472. for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
  1473. const struct drm_display_mode *ptr = &drm_dmt_modes[i];
  1474. if (hsize != ptr->hdisplay)
  1475. continue;
  1476. if (vsize != ptr->vdisplay)
  1477. continue;
  1478. if (fresh != drm_mode_vrefresh(ptr))
  1479. continue;
  1480. if (rb != mode_is_rb(ptr))
  1481. continue;
  1482. return drm_mode_duplicate(dev, ptr);
  1483. }
  1484. return NULL;
  1485. }
  1486. EXPORT_SYMBOL(drm_mode_find_dmt);
  1487. typedef void detailed_cb(struct detailed_timing *timing, void *closure);
  1488. static void
  1489. cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
  1490. {
  1491. int i, n = 0;
  1492. u8 d = ext[0x02];
  1493. u8 *det_base = ext + d;
  1494. n = (127 - d) / 18;
  1495. for (i = 0; i < n; i++)
  1496. cb((struct detailed_timing *)(det_base + 18 * i), closure);
  1497. }
  1498. static void
  1499. vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
  1500. {
  1501. unsigned int i, n = min((int)ext[0x02], 6);
  1502. u8 *det_base = ext + 5;
  1503. if (ext[0x01] != 1)
  1504. return; /* unknown version */
  1505. for (i = 0; i < n; i++)
  1506. cb((struct detailed_timing *)(det_base + 18 * i), closure);
  1507. }
  1508. static void
  1509. drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
  1510. {
  1511. int i;
  1512. struct edid *edid = (struct edid *)raw_edid;
  1513. if (edid == NULL)
  1514. return;
  1515. for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
  1516. cb(&(edid->detailed_timings[i]), closure);
  1517. for (i = 1; i <= raw_edid[0x7e]; i++) {
  1518. u8 *ext = raw_edid + (i * EDID_LENGTH);
  1519. switch (*ext) {
  1520. case CEA_EXT:
  1521. cea_for_each_detailed_block(ext, cb, closure);
  1522. break;
  1523. case VTB_EXT:
  1524. vtb_for_each_detailed_block(ext, cb, closure);
  1525. break;
  1526. default:
  1527. break;
  1528. }
  1529. }
  1530. }
  1531. static void
  1532. is_rb(struct detailed_timing *t, void *data)
  1533. {
  1534. u8 *r = (u8 *)t;
  1535. if (r[3] == EDID_DETAIL_MONITOR_RANGE)
  1536. if (r[15] & 0x10)
  1537. *(bool *)data = true;
  1538. }
  1539. /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
  1540. static bool
  1541. drm_monitor_supports_rb(struct edid *edid)
  1542. {
  1543. if (edid->revision >= 4) {
  1544. bool ret = false;
  1545. drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
  1546. return ret;
  1547. }
  1548. return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
  1549. }
  1550. static void
  1551. find_gtf2(struct detailed_timing *t, void *data)
  1552. {
  1553. u8 *r = (u8 *)t;
  1554. if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
  1555. *(u8 **)data = r;
  1556. }
  1557. /* Secondary GTF curve kicks in above some break frequency */
  1558. static int
  1559. drm_gtf2_hbreak(struct edid *edid)
  1560. {
  1561. u8 *r = NULL;
  1562. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  1563. return r ? (r[12] * 2) : 0;
  1564. }
  1565. static int
  1566. drm_gtf2_2c(struct edid *edid)
  1567. {
  1568. u8 *r = NULL;
  1569. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  1570. return r ? r[13] : 0;
  1571. }
  1572. static int
  1573. drm_gtf2_m(struct edid *edid)
  1574. {
  1575. u8 *r = NULL;
  1576. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  1577. return r ? (r[15] << 8) + r[14] : 0;
  1578. }
  1579. static int
  1580. drm_gtf2_k(struct edid *edid)
  1581. {
  1582. u8 *r = NULL;
  1583. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  1584. return r ? r[16] : 0;
  1585. }
  1586. static int
  1587. drm_gtf2_2j(struct edid *edid)
  1588. {
  1589. u8 *r = NULL;
  1590. drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
  1591. return r ? r[17] : 0;
  1592. }
  1593. /**
  1594. * standard_timing_level - get std. timing level(CVT/GTF/DMT)
  1595. * @edid: EDID block to scan
  1596. */
  1597. static int standard_timing_level(struct edid *edid)
  1598. {
  1599. if (edid->revision >= 2) {
  1600. if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
  1601. return LEVEL_CVT;
  1602. if (drm_gtf2_hbreak(edid))
  1603. return LEVEL_GTF2;
  1604. return LEVEL_GTF;
  1605. }
  1606. return LEVEL_DMT;
  1607. }
  1608. /*
  1609. * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
  1610. * monitors fill with ascii space (0x20) instead.
  1611. */
  1612. static int
  1613. bad_std_timing(u8 a, u8 b)
  1614. {
  1615. return (a == 0x00 && b == 0x00) ||
  1616. (a == 0x01 && b == 0x01) ||
  1617. (a == 0x20 && b == 0x20);
  1618. }
  1619. /**
  1620. * drm_mode_std - convert standard mode info (width, height, refresh) into mode
  1621. * @connector: connector of for the EDID block
  1622. * @edid: EDID block to scan
  1623. * @t: standard timing params
  1624. *
  1625. * Take the standard timing params (in this case width, aspect, and refresh)
  1626. * and convert them into a real mode using CVT/GTF/DMT.
  1627. */
  1628. static struct drm_display_mode *
  1629. drm_mode_std(struct drm_connector *connector, struct edid *edid,
  1630. struct std_timing *t)
  1631. {
  1632. struct drm_device *dev = connector->dev;
  1633. struct drm_display_mode *m, *mode = NULL;
  1634. int hsize, vsize;
  1635. int vrefresh_rate;
  1636. unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
  1637. >> EDID_TIMING_ASPECT_SHIFT;
  1638. unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
  1639. >> EDID_TIMING_VFREQ_SHIFT;
  1640. int timing_level = standard_timing_level(edid);
  1641. if (bad_std_timing(t->hsize, t->vfreq_aspect))
  1642. return NULL;
  1643. /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
  1644. hsize = t->hsize * 8 + 248;
  1645. /* vrefresh_rate = vfreq + 60 */
  1646. vrefresh_rate = vfreq + 60;
  1647. /* the vdisplay is calculated based on the aspect ratio */
  1648. if (aspect_ratio == 0) {
  1649. if (edid->revision < 3)
  1650. vsize = hsize;
  1651. else
  1652. vsize = (hsize * 10) / 16;
  1653. } else if (aspect_ratio == 1)
  1654. vsize = (hsize * 3) / 4;
  1655. else if (aspect_ratio == 2)
  1656. vsize = (hsize * 4) / 5;
  1657. else
  1658. vsize = (hsize * 9) / 16;
  1659. /* HDTV hack, part 1 */
  1660. if (vrefresh_rate == 60 &&
  1661. ((hsize == 1360 && vsize == 765) ||
  1662. (hsize == 1368 && vsize == 769))) {
  1663. hsize = 1366;
  1664. vsize = 768;
  1665. }
  1666. /*
  1667. * If this connector already has a mode for this size and refresh
  1668. * rate (because it came from detailed or CVT info), use that
  1669. * instead. This way we don't have to guess at interlace or
  1670. * reduced blanking.
  1671. */
  1672. list_for_each_entry(m, &connector->probed_modes, head)
  1673. if (m->hdisplay == hsize && m->vdisplay == vsize &&
  1674. drm_mode_vrefresh(m) == vrefresh_rate)
  1675. return NULL;
  1676. /* HDTV hack, part 2 */
  1677. if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
  1678. mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
  1679. false);
  1680. mode->hdisplay = 1366;
  1681. mode->hsync_start = mode->hsync_start - 1;
  1682. mode->hsync_end = mode->hsync_end - 1;
  1683. return mode;
  1684. }
  1685. /* check whether it can be found in default mode table */
  1686. if (drm_monitor_supports_rb(edid)) {
  1687. mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
  1688. true);
  1689. if (mode)
  1690. return mode;
  1691. }
  1692. mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
  1693. if (mode)
  1694. return mode;
  1695. /* okay, generate it */
  1696. switch (timing_level) {
  1697. case LEVEL_DMT:
  1698. break;
  1699. case LEVEL_GTF:
  1700. mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
  1701. break;
  1702. case LEVEL_GTF2:
  1703. /*
  1704. * This is potentially wrong if there's ever a monitor with
  1705. * more than one ranges section, each claiming a different
  1706. * secondary GTF curve. Please don't do that.
  1707. */
  1708. mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
  1709. if (!mode)
  1710. return NULL;
  1711. if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
  1712. drm_mode_destroy(dev, mode);
  1713. mode = drm_gtf_mode_complex(dev, hsize, vsize,
  1714. vrefresh_rate, 0, 0,
  1715. drm_gtf2_m(edid),
  1716. drm_gtf2_2c(edid),
  1717. drm_gtf2_k(edid),
  1718. drm_gtf2_2j(edid));
  1719. }
  1720. break;
  1721. case LEVEL_CVT:
  1722. mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
  1723. false);
  1724. break;
  1725. }
  1726. return mode;
  1727. }
  1728. /*
  1729. * EDID is delightfully ambiguous about how interlaced modes are to be
  1730. * encoded. Our internal representation is of frame height, but some
  1731. * HDTV detailed timings are encoded as field height.
  1732. *
  1733. * The format list here is from CEA, in frame size. Technically we
  1734. * should be checking refresh rate too. Whatever.
  1735. */
  1736. static void
  1737. drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
  1738. struct detailed_pixel_timing *pt)
  1739. {
  1740. int i;
  1741. static const struct {
  1742. int w, h;
  1743. } cea_interlaced[] = {
  1744. { 1920, 1080 },
  1745. { 720, 480 },
  1746. { 1440, 480 },
  1747. { 2880, 480 },
  1748. { 720, 576 },
  1749. { 1440, 576 },
  1750. { 2880, 576 },
  1751. };
  1752. if (!(pt->misc & DRM_EDID_PT_INTERLACED))
  1753. return;
  1754. for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
  1755. if ((mode->hdisplay == cea_interlaced[i].w) &&
  1756. (mode->vdisplay == cea_interlaced[i].h / 2)) {
  1757. mode->vdisplay *= 2;
  1758. mode->vsync_start *= 2;
  1759. mode->vsync_end *= 2;
  1760. mode->vtotal *= 2;
  1761. mode->vtotal |= 1;
  1762. }
  1763. }
  1764. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  1765. }
  1766. /**
  1767. * drm_mode_detailed - create a new mode from an EDID detailed timing section
  1768. * @dev: DRM device (needed to create new mode)
  1769. * @edid: EDID block
  1770. * @timing: EDID detailed timing info
  1771. * @quirks: quirks to apply
  1772. *
  1773. * An EDID detailed timing block contains enough info for us to create and
  1774. * return a new struct drm_display_mode.
  1775. */
  1776. static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
  1777. struct edid *edid,
  1778. struct detailed_timing *timing,
  1779. u32 quirks)
  1780. {
  1781. struct drm_display_mode *mode;
  1782. struct detailed_pixel_timing *pt = &timing->data.pixel_data;
  1783. unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
  1784. unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
  1785. unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
  1786. unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
  1787. unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
  1788. unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
  1789. unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
  1790. unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
  1791. /* ignore tiny modes */
  1792. if (hactive < 64 || vactive < 64)
  1793. return NULL;
  1794. if (pt->misc & DRM_EDID_PT_STEREO) {
  1795. DRM_DEBUG_KMS("stereo mode not supported\n");
  1796. return NULL;
  1797. }
  1798. if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
  1799. DRM_DEBUG_KMS("composite sync not supported\n");
  1800. }
  1801. /* it is incorrect if hsync/vsync width is zero */
  1802. if (!hsync_pulse_width || !vsync_pulse_width) {
  1803. DRM_DEBUG_KMS("Incorrect Detailed timing. "
  1804. "Wrong Hsync/Vsync pulse width\n");
  1805. return NULL;
  1806. }
  1807. if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
  1808. mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
  1809. if (!mode)
  1810. return NULL;
  1811. goto set_size;
  1812. }
  1813. mode = drm_mode_create(dev);
  1814. if (!mode)
  1815. return NULL;
  1816. if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
  1817. timing->pixel_clock = cpu_to_le16(1088);
  1818. mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
  1819. mode->hdisplay = hactive;
  1820. mode->hsync_start = mode->hdisplay + hsync_offset;
  1821. mode->hsync_end = mode->hsync_start + hsync_pulse_width;
  1822. mode->htotal = mode->hdisplay + hblank;
  1823. mode->vdisplay = vactive;
  1824. mode->vsync_start = mode->vdisplay + vsync_offset;
  1825. mode->vsync_end = mode->vsync_start + vsync_pulse_width;
  1826. mode->vtotal = mode->vdisplay + vblank;
  1827. /* Some EDIDs have bogus h/vtotal values */
  1828. if (mode->hsync_end > mode->htotal)
  1829. mode->htotal = mode->hsync_end + 1;
  1830. if (mode->vsync_end > mode->vtotal)
  1831. mode->vtotal = mode->vsync_end + 1;
  1832. drm_mode_do_interlace_quirk(mode, pt);
  1833. if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
  1834. pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
  1835. }
  1836. mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
  1837. DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
  1838. mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
  1839. DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
  1840. set_size:
  1841. mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
  1842. mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
  1843. if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
  1844. mode->width_mm *= 10;
  1845. mode->height_mm *= 10;
  1846. }
  1847. if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
  1848. mode->width_mm = edid->width_cm * 10;
  1849. mode->height_mm = edid->height_cm * 10;
  1850. }
  1851. mode->type = DRM_MODE_TYPE_DRIVER;
  1852. mode->vrefresh = drm_mode_vrefresh(mode);
  1853. drm_mode_set_name(mode);
  1854. return mode;
  1855. }
  1856. static bool
  1857. mode_in_hsync_range(const struct drm_display_mode *mode,
  1858. struct edid *edid, u8 *t)
  1859. {
  1860. int hsync, hmin, hmax;
  1861. hmin = t[7];
  1862. if (edid->revision >= 4)
  1863. hmin += ((t[4] & 0x04) ? 255 : 0);
  1864. hmax = t[8];
  1865. if (edid->revision >= 4)
  1866. hmax += ((t[4] & 0x08) ? 255 : 0);
  1867. hsync = drm_mode_hsync(mode);
  1868. return (hsync <= hmax && hsync >= hmin);
  1869. }
  1870. static bool
  1871. mode_in_vsync_range(const struct drm_display_mode *mode,
  1872. struct edid *edid, u8 *t)
  1873. {
  1874. int vsync, vmin, vmax;
  1875. vmin = t[5];
  1876. if (edid->revision >= 4)
  1877. vmin += ((t[4] & 0x01) ? 255 : 0);
  1878. vmax = t[6];
  1879. if (edid->revision >= 4)
  1880. vmax += ((t[4] & 0x02) ? 255 : 0);
  1881. vsync = drm_mode_vrefresh(mode);
  1882. return (vsync <= vmax && vsync >= vmin);
  1883. }
  1884. static u32
  1885. range_pixel_clock(struct edid *edid, u8 *t)
  1886. {
  1887. /* unspecified */
  1888. if (t[9] == 0 || t[9] == 255)
  1889. return 0;
  1890. /* 1.4 with CVT support gives us real precision, yay */
  1891. if (edid->revision >= 4 && t[10] == 0x04)
  1892. return (t[9] * 10000) - ((t[12] >> 2) * 250);
  1893. /* 1.3 is pathetic, so fuzz up a bit */
  1894. return t[9] * 10000 + 5001;
  1895. }
  1896. static bool
  1897. mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
  1898. struct detailed_timing *timing)
  1899. {
  1900. u32 max_clock;
  1901. u8 *t = (u8 *)timing;
  1902. if (!mode_in_hsync_range(mode, edid, t))
  1903. return false;
  1904. if (!mode_in_vsync_range(mode, edid, t))
  1905. return false;
  1906. if ((max_clock = range_pixel_clock(edid, t)))
  1907. if (mode->clock > max_clock)
  1908. return false;
  1909. /* 1.4 max horizontal check */
  1910. if (edid->revision >= 4 && t[10] == 0x04)
  1911. if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
  1912. return false;
  1913. if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
  1914. return false;
  1915. return true;
  1916. }
  1917. static bool valid_inferred_mode(const struct drm_connector *connector,
  1918. const struct drm_display_mode *mode)
  1919. {
  1920. const struct drm_display_mode *m;
  1921. bool ok = false;
  1922. list_for_each_entry(m, &connector->probed_modes, head) {
  1923. if (mode->hdisplay == m->hdisplay &&
  1924. mode->vdisplay == m->vdisplay &&
  1925. drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
  1926. return false; /* duplicated */
  1927. if (mode->hdisplay <= m->hdisplay &&
  1928. mode->vdisplay <= m->vdisplay)
  1929. ok = true;
  1930. }
  1931. return ok;
  1932. }
  1933. static int
  1934. drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
  1935. struct detailed_timing *timing)
  1936. {
  1937. int i, modes = 0;
  1938. struct drm_display_mode *newmode;
  1939. struct drm_device *dev = connector->dev;
  1940. for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
  1941. if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
  1942. valid_inferred_mode(connector, drm_dmt_modes + i)) {
  1943. newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
  1944. if (newmode) {
  1945. drm_mode_probed_add(connector, newmode);
  1946. modes++;
  1947. }
  1948. }
  1949. }
  1950. return modes;
  1951. }
  1952. /* fix up 1366x768 mode from 1368x768;
  1953. * GFT/CVT can't express 1366 width which isn't dividable by 8
  1954. */
  1955. static void fixup_mode_1366x768(struct drm_display_mode *mode)
  1956. {
  1957. if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
  1958. mode->hdisplay = 1366;
  1959. mode->hsync_start--;
  1960. mode->hsync_end--;
  1961. drm_mode_set_name(mode);
  1962. }
  1963. }
  1964. static int
  1965. drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
  1966. struct detailed_timing *timing)
  1967. {
  1968. int i, modes = 0;
  1969. struct drm_display_mode *newmode;
  1970. struct drm_device *dev = connector->dev;
  1971. for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
  1972. const struct minimode *m = &extra_modes[i];
  1973. newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
  1974. if (!newmode)
  1975. return modes;
  1976. fixup_mode_1366x768(newmode);
  1977. if (!mode_in_range(newmode, edid, timing) ||
  1978. !valid_inferred_mode(connector, newmode)) {
  1979. drm_mode_destroy(dev, newmode);
  1980. continue;
  1981. }
  1982. drm_mode_probed_add(connector, newmode);
  1983. modes++;
  1984. }
  1985. return modes;
  1986. }
  1987. static int
  1988. drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
  1989. struct detailed_timing *timing)
  1990. {
  1991. int i, modes = 0;
  1992. struct drm_display_mode *newmode;
  1993. struct drm_device *dev = connector->dev;
  1994. bool rb = drm_monitor_supports_rb(edid);
  1995. for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
  1996. const struct minimode *m = &extra_modes[i];
  1997. newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
  1998. if (!newmode)
  1999. return modes;
  2000. fixup_mode_1366x768(newmode);
  2001. if (!mode_in_range(newmode, edid, timing) ||
  2002. !valid_inferred_mode(connector, newmode)) {
  2003. drm_mode_destroy(dev, newmode);
  2004. continue;
  2005. }
  2006. drm_mode_probed_add(connector, newmode);
  2007. modes++;
  2008. }
  2009. return modes;
  2010. }
  2011. static void
  2012. do_inferred_modes(struct detailed_timing *timing, void *c)
  2013. {
  2014. struct detailed_mode_closure *closure = c;
  2015. struct detailed_non_pixel *data = &timing->data.other_data;
  2016. struct detailed_data_monitor_range *range = &data->data.range;
  2017. if (data->type != EDID_DETAIL_MONITOR_RANGE)
  2018. return;
  2019. closure->modes += drm_dmt_modes_for_range(closure->connector,
  2020. closure->edid,
  2021. timing);
  2022. if (!version_greater(closure->edid, 1, 1))
  2023. return; /* GTF not defined yet */
  2024. switch (range->flags) {
  2025. case 0x02: /* secondary gtf, XXX could do more */
  2026. case 0x00: /* default gtf */
  2027. closure->modes += drm_gtf_modes_for_range(closure->connector,
  2028. closure->edid,
  2029. timing);
  2030. break;
  2031. case 0x04: /* cvt, only in 1.4+ */
  2032. if (!version_greater(closure->edid, 1, 3))
  2033. break;
  2034. closure->modes += drm_cvt_modes_for_range(closure->connector,
  2035. closure->edid,
  2036. timing);
  2037. break;
  2038. case 0x01: /* just the ranges, no formula */
  2039. default:
  2040. break;
  2041. }
  2042. }
  2043. static int
  2044. add_inferred_modes(struct drm_connector *connector, struct edid *edid)
  2045. {
  2046. struct detailed_mode_closure closure = {
  2047. .connector = connector,
  2048. .edid = edid,
  2049. };
  2050. if (version_greater(edid, 1, 0))
  2051. drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
  2052. &closure);
  2053. return closure.modes;
  2054. }
  2055. static int
  2056. drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
  2057. {
  2058. int i, j, m, modes = 0;
  2059. struct drm_display_mode *mode;
  2060. u8 *est = ((u8 *)timing) + 6;
  2061. for (i = 0; i < 6; i++) {
  2062. for (j = 7; j >= 0; j--) {
  2063. m = (i * 8) + (7 - j);
  2064. if (m >= ARRAY_SIZE(est3_modes))
  2065. break;
  2066. if (est[i] & (1 << j)) {
  2067. mode = drm_mode_find_dmt(connector->dev,
  2068. est3_modes[m].w,
  2069. est3_modes[m].h,
  2070. est3_modes[m].r,
  2071. est3_modes[m].rb);
  2072. if (mode) {
  2073. drm_mode_probed_add(connector, mode);
  2074. modes++;
  2075. }
  2076. }
  2077. }
  2078. }
  2079. return modes;
  2080. }
  2081. static void
  2082. do_established_modes(struct detailed_timing *timing, void *c)
  2083. {
  2084. struct detailed_mode_closure *closure = c;
  2085. struct detailed_non_pixel *data = &timing->data.other_data;
  2086. if (data->type == EDID_DETAIL_EST_TIMINGS)
  2087. closure->modes += drm_est3_modes(closure->connector, timing);
  2088. }
  2089. /**
  2090. * add_established_modes - get est. modes from EDID and add them
  2091. * @connector: connector to add mode(s) to
  2092. * @edid: EDID block to scan
  2093. *
  2094. * Each EDID block contains a bitmap of the supported "established modes" list
  2095. * (defined above). Tease them out and add them to the global modes list.
  2096. */
  2097. static int
  2098. add_established_modes(struct drm_connector *connector, struct edid *edid)
  2099. {
  2100. struct drm_device *dev = connector->dev;
  2101. unsigned long est_bits = edid->established_timings.t1 |
  2102. (edid->established_timings.t2 << 8) |
  2103. ((edid->established_timings.mfg_rsvd & 0x80) << 9);
  2104. int i, modes = 0;
  2105. struct detailed_mode_closure closure = {
  2106. .connector = connector,
  2107. .edid = edid,
  2108. };
  2109. for (i = 0; i <= EDID_EST_TIMINGS; i++) {
  2110. if (est_bits & (1<<i)) {
  2111. struct drm_display_mode *newmode;
  2112. newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
  2113. if (newmode) {
  2114. drm_mode_probed_add(connector, newmode);
  2115. modes++;
  2116. }
  2117. }
  2118. }
  2119. if (version_greater(edid, 1, 0))
  2120. drm_for_each_detailed_block((u8 *)edid,
  2121. do_established_modes, &closure);
  2122. return modes + closure.modes;
  2123. }
  2124. static void
  2125. do_standard_modes(struct detailed_timing *timing, void *c)
  2126. {
  2127. struct detailed_mode_closure *closure = c;
  2128. struct detailed_non_pixel *data = &timing->data.other_data;
  2129. struct drm_connector *connector = closure->connector;
  2130. struct edid *edid = closure->edid;
  2131. if (data->type == EDID_DETAIL_STD_MODES) {
  2132. int i;
  2133. for (i = 0; i < 6; i++) {
  2134. struct std_timing *std;
  2135. struct drm_display_mode *newmode;
  2136. std = &data->data.timings[i];
  2137. newmode = drm_mode_std(connector, edid, std);
  2138. if (newmode) {
  2139. drm_mode_probed_add(connector, newmode);
  2140. closure->modes++;
  2141. }
  2142. }
  2143. }
  2144. }
  2145. /**
  2146. * add_standard_modes - get std. modes from EDID and add them
  2147. * @connector: connector to add mode(s) to
  2148. * @edid: EDID block to scan
  2149. *
  2150. * Standard modes can be calculated using the appropriate standard (DMT,
  2151. * GTF or CVT. Grab them from @edid and add them to the list.
  2152. */
  2153. static int
  2154. add_standard_modes(struct drm_connector *connector, struct edid *edid)
  2155. {
  2156. int i, modes = 0;
  2157. struct detailed_mode_closure closure = {
  2158. .connector = connector,
  2159. .edid = edid,
  2160. };
  2161. for (i = 0; i < EDID_STD_TIMINGS; i++) {
  2162. struct drm_display_mode *newmode;
  2163. newmode = drm_mode_std(connector, edid,
  2164. &edid->standard_timings[i]);
  2165. if (newmode) {
  2166. drm_mode_probed_add(connector, newmode);
  2167. modes++;
  2168. }
  2169. }
  2170. if (version_greater(edid, 1, 0))
  2171. drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
  2172. &closure);
  2173. /* XXX should also look for standard codes in VTB blocks */
  2174. return modes + closure.modes;
  2175. }
  2176. static int drm_cvt_modes(struct drm_connector *connector,
  2177. struct detailed_timing *timing)
  2178. {
  2179. int i, j, modes = 0;
  2180. struct drm_display_mode *newmode;
  2181. struct drm_device *dev = connector->dev;
  2182. struct cvt_timing *cvt;
  2183. const int rates[] = { 60, 85, 75, 60, 50 };
  2184. const u8 empty[3] = { 0, 0, 0 };
  2185. for (i = 0; i < 4; i++) {
  2186. int uninitialized_var(width), height;
  2187. cvt = &(timing->data.other_data.data.cvt[i]);
  2188. if (!memcmp(cvt->code, empty, 3))
  2189. continue;
  2190. height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
  2191. switch (cvt->code[1] & 0x0c) {
  2192. case 0x00:
  2193. width = height * 4 / 3;
  2194. break;
  2195. case 0x04:
  2196. width = height * 16 / 9;
  2197. break;
  2198. case 0x08:
  2199. width = height * 16 / 10;
  2200. break;
  2201. case 0x0c:
  2202. width = height * 15 / 9;
  2203. break;
  2204. }
  2205. for (j = 1; j < 5; j++) {
  2206. if (cvt->code[2] & (1 << j)) {
  2207. newmode = drm_cvt_mode(dev, width, height,
  2208. rates[j], j == 0,
  2209. false, false);
  2210. if (newmode) {
  2211. drm_mode_probed_add(connector, newmode);
  2212. modes++;
  2213. }
  2214. }
  2215. }
  2216. }
  2217. return modes;
  2218. }
  2219. static void
  2220. do_cvt_mode(struct detailed_timing *timing, void *c)
  2221. {
  2222. struct detailed_mode_closure *closure = c;
  2223. struct detailed_non_pixel *data = &timing->data.other_data;
  2224. if (data->type == EDID_DETAIL_CVT_3BYTE)
  2225. closure->modes += drm_cvt_modes(closure->connector, timing);
  2226. }
  2227. static int
  2228. add_cvt_modes(struct drm_connector *connector, struct edid *edid)
  2229. {
  2230. struct detailed_mode_closure closure = {
  2231. .connector = connector,
  2232. .edid = edid,
  2233. };
  2234. if (version_greater(edid, 1, 2))
  2235. drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
  2236. /* XXX should also look for CVT codes in VTB blocks */
  2237. return closure.modes;
  2238. }
  2239. static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
  2240. static void
  2241. do_detailed_mode(struct detailed_timing *timing, void *c)
  2242. {
  2243. struct detailed_mode_closure *closure = c;
  2244. struct drm_display_mode *newmode;
  2245. if (timing->pixel_clock) {
  2246. newmode = drm_mode_detailed(closure->connector->dev,
  2247. closure->edid, timing,
  2248. closure->quirks);
  2249. if (!newmode)
  2250. return;
  2251. if (closure->preferred)
  2252. newmode->type |= DRM_MODE_TYPE_PREFERRED;
  2253. /*
  2254. * Detailed modes are limited to 10kHz pixel clock resolution,
  2255. * so fix up anything that looks like CEA/HDMI mode, but the clock
  2256. * is just slightly off.
  2257. */
  2258. fixup_detailed_cea_mode_clock(newmode);
  2259. drm_mode_probed_add(closure->connector, newmode);
  2260. closure->modes++;
  2261. closure->preferred = 0;
  2262. }
  2263. }
  2264. /*
  2265. * add_detailed_modes - Add modes from detailed timings
  2266. * @connector: attached connector
  2267. * @edid: EDID block to scan
  2268. * @quirks: quirks to apply
  2269. */
  2270. static int
  2271. add_detailed_modes(struct drm_connector *connector, struct edid *edid,
  2272. u32 quirks)
  2273. {
  2274. struct detailed_mode_closure closure = {
  2275. .connector = connector,
  2276. .edid = edid,
  2277. .preferred = 1,
  2278. .quirks = quirks,
  2279. };
  2280. if (closure.preferred && !version_greater(edid, 1, 3))
  2281. closure.preferred =
  2282. (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
  2283. drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
  2284. return closure.modes;
  2285. }
  2286. #define AUDIO_BLOCK 0x01
  2287. #define VIDEO_BLOCK 0x02
  2288. #define VENDOR_BLOCK 0x03
  2289. #define SPEAKER_BLOCK 0x04
  2290. #define VIDEO_CAPABILITY_BLOCK 0x07
  2291. #define EDID_BASIC_AUDIO (1 << 6)
  2292. #define EDID_CEA_YCRCB444 (1 << 5)
  2293. #define EDID_CEA_YCRCB422 (1 << 4)
  2294. #define EDID_CEA_VCDB_QS (1 << 6)
  2295. /*
  2296. * Search EDID for CEA extension block.
  2297. */
  2298. static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
  2299. {
  2300. u8 *edid_ext = NULL;
  2301. int i;
  2302. /* No EDID or EDID extensions */
  2303. if (edid == NULL || edid->extensions == 0)
  2304. return NULL;
  2305. /* Find CEA extension */
  2306. for (i = 0; i < edid->extensions; i++) {
  2307. edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
  2308. if (edid_ext[0] == ext_id)
  2309. break;
  2310. }
  2311. if (i == edid->extensions)
  2312. return NULL;
  2313. return edid_ext;
  2314. }
  2315. static u8 *drm_find_cea_extension(struct edid *edid)
  2316. {
  2317. return drm_find_edid_extension(edid, CEA_EXT);
  2318. }
  2319. static u8 *drm_find_displayid_extension(struct edid *edid)
  2320. {
  2321. return drm_find_edid_extension(edid, DISPLAYID_EXT);
  2322. }
  2323. /*
  2324. * Calculate the alternate clock for the CEA mode
  2325. * (60Hz vs. 59.94Hz etc.)
  2326. */
  2327. static unsigned int
  2328. cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
  2329. {
  2330. unsigned int clock = cea_mode->clock;
  2331. if (cea_mode->vrefresh % 6 != 0)
  2332. return clock;
  2333. /*
  2334. * edid_cea_modes contains the 59.94Hz
  2335. * variant for 240 and 480 line modes,
  2336. * and the 60Hz variant otherwise.
  2337. */
  2338. if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
  2339. clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
  2340. else
  2341. clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
  2342. return clock;
  2343. }
  2344. static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
  2345. unsigned int clock_tolerance)
  2346. {
  2347. u8 vic;
  2348. if (!to_match->clock)
  2349. return 0;
  2350. for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
  2351. const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
  2352. unsigned int clock1, clock2;
  2353. /* Check both 60Hz and 59.94Hz */
  2354. clock1 = cea_mode->clock;
  2355. clock2 = cea_mode_alternate_clock(cea_mode);
  2356. if (abs(to_match->clock - clock1) > clock_tolerance &&
  2357. abs(to_match->clock - clock2) > clock_tolerance)
  2358. continue;
  2359. if (drm_mode_equal_no_clocks(to_match, cea_mode))
  2360. return vic;
  2361. }
  2362. return 0;
  2363. }
  2364. /**
  2365. * drm_match_cea_mode - look for a CEA mode matching given mode
  2366. * @to_match: display mode
  2367. *
  2368. * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
  2369. * mode.
  2370. */
  2371. u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
  2372. {
  2373. u8 vic;
  2374. if (!to_match->clock)
  2375. return 0;
  2376. for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
  2377. const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
  2378. unsigned int clock1, clock2;
  2379. /* Check both 60Hz and 59.94Hz */
  2380. clock1 = cea_mode->clock;
  2381. clock2 = cea_mode_alternate_clock(cea_mode);
  2382. if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
  2383. KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
  2384. drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
  2385. return vic;
  2386. }
  2387. return 0;
  2388. }
  2389. EXPORT_SYMBOL(drm_match_cea_mode);
  2390. static bool drm_valid_cea_vic(u8 vic)
  2391. {
  2392. return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
  2393. }
  2394. /**
  2395. * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
  2396. * the input VIC from the CEA mode list
  2397. * @video_code: ID given to each of the CEA modes
  2398. *
  2399. * Returns picture aspect ratio
  2400. */
  2401. enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
  2402. {
  2403. return edid_cea_modes[video_code].picture_aspect_ratio;
  2404. }
  2405. EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
  2406. /*
  2407. * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
  2408. * specific block).
  2409. *
  2410. * It's almost like cea_mode_alternate_clock(), we just need to add an
  2411. * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
  2412. * one.
  2413. */
  2414. static unsigned int
  2415. hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
  2416. {
  2417. if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
  2418. return hdmi_mode->clock;
  2419. return cea_mode_alternate_clock(hdmi_mode);
  2420. }
  2421. static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
  2422. unsigned int clock_tolerance)
  2423. {
  2424. u8 vic;
  2425. if (!to_match->clock)
  2426. return 0;
  2427. for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
  2428. const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
  2429. unsigned int clock1, clock2;
  2430. /* Make sure to also match alternate clocks */
  2431. clock1 = hdmi_mode->clock;
  2432. clock2 = hdmi_mode_alternate_clock(hdmi_mode);
  2433. if (abs(to_match->clock - clock1) > clock_tolerance &&
  2434. abs(to_match->clock - clock2) > clock_tolerance)
  2435. continue;
  2436. if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
  2437. return vic;
  2438. }
  2439. return 0;
  2440. }
  2441. /*
  2442. * drm_match_hdmi_mode - look for a HDMI mode matching given mode
  2443. * @to_match: display mode
  2444. *
  2445. * An HDMI mode is one defined in the HDMI vendor specific block.
  2446. *
  2447. * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
  2448. */
  2449. static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
  2450. {
  2451. u8 vic;
  2452. if (!to_match->clock)
  2453. return 0;
  2454. for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
  2455. const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
  2456. unsigned int clock1, clock2;
  2457. /* Make sure to also match alternate clocks */
  2458. clock1 = hdmi_mode->clock;
  2459. clock2 = hdmi_mode_alternate_clock(hdmi_mode);
  2460. if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
  2461. KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
  2462. drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
  2463. return vic;
  2464. }
  2465. return 0;
  2466. }
  2467. static bool drm_valid_hdmi_vic(u8 vic)
  2468. {
  2469. return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
  2470. }
  2471. static int
  2472. add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
  2473. {
  2474. struct drm_device *dev = connector->dev;
  2475. struct drm_display_mode *mode, *tmp;
  2476. LIST_HEAD(list);
  2477. int modes = 0;
  2478. /* Don't add CEA modes if the CEA extension block is missing */
  2479. if (!drm_find_cea_extension(edid))
  2480. return 0;
  2481. /*
  2482. * Go through all probed modes and create a new mode
  2483. * with the alternate clock for certain CEA modes.
  2484. */
  2485. list_for_each_entry(mode, &connector->probed_modes, head) {
  2486. const struct drm_display_mode *cea_mode = NULL;
  2487. struct drm_display_mode *newmode;
  2488. u8 vic = drm_match_cea_mode(mode);
  2489. unsigned int clock1, clock2;
  2490. if (drm_valid_cea_vic(vic)) {
  2491. cea_mode = &edid_cea_modes[vic];
  2492. clock2 = cea_mode_alternate_clock(cea_mode);
  2493. } else {
  2494. vic = drm_match_hdmi_mode(mode);
  2495. if (drm_valid_hdmi_vic(vic)) {
  2496. cea_mode = &edid_4k_modes[vic];
  2497. clock2 = hdmi_mode_alternate_clock(cea_mode);
  2498. }
  2499. }
  2500. if (!cea_mode)
  2501. continue;
  2502. clock1 = cea_mode->clock;
  2503. if (clock1 == clock2)
  2504. continue;
  2505. if (mode->clock != clock1 && mode->clock != clock2)
  2506. continue;
  2507. newmode = drm_mode_duplicate(dev, cea_mode);
  2508. if (!newmode)
  2509. continue;
  2510. /* Carry over the stereo flags */
  2511. newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
  2512. /*
  2513. * The current mode could be either variant. Make
  2514. * sure to pick the "other" clock for the new mode.
  2515. */
  2516. if (mode->clock != clock1)
  2517. newmode->clock = clock1;
  2518. else
  2519. newmode->clock = clock2;
  2520. list_add_tail(&newmode->head, &list);
  2521. }
  2522. list_for_each_entry_safe(mode, tmp, &list, head) {
  2523. list_del(&mode->head);
  2524. drm_mode_probed_add(connector, mode);
  2525. modes++;
  2526. }
  2527. return modes;
  2528. }
  2529. static struct drm_display_mode *
  2530. drm_display_mode_from_vic_index(struct drm_connector *connector,
  2531. const u8 *video_db, u8 video_len,
  2532. u8 video_index)
  2533. {
  2534. struct drm_device *dev = connector->dev;
  2535. struct drm_display_mode *newmode;
  2536. u8 vic;
  2537. if (video_db == NULL || video_index >= video_len)
  2538. return NULL;
  2539. /* CEA modes are numbered 1..127 */
  2540. vic = (video_db[video_index] & 127);
  2541. if (!drm_valid_cea_vic(vic))
  2542. return NULL;
  2543. newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
  2544. if (!newmode)
  2545. return NULL;
  2546. newmode->vrefresh = 0;
  2547. return newmode;
  2548. }
  2549. static int
  2550. do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
  2551. {
  2552. int i, modes = 0;
  2553. for (i = 0; i < len; i++) {
  2554. struct drm_display_mode *mode;
  2555. mode = drm_display_mode_from_vic_index(connector, db, len, i);
  2556. if (mode) {
  2557. drm_mode_probed_add(connector, mode);
  2558. modes++;
  2559. }
  2560. }
  2561. return modes;
  2562. }
  2563. struct stereo_mandatory_mode {
  2564. int width, height, vrefresh;
  2565. unsigned int flags;
  2566. };
  2567. static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
  2568. { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
  2569. { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
  2570. { 1920, 1080, 50,
  2571. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
  2572. { 1920, 1080, 60,
  2573. DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
  2574. { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
  2575. { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
  2576. { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
  2577. { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
  2578. };
  2579. static bool
  2580. stereo_match_mandatory(const struct drm_display_mode *mode,
  2581. const struct stereo_mandatory_mode *stereo_mode)
  2582. {
  2583. unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
  2584. return mode->hdisplay == stereo_mode->width &&
  2585. mode->vdisplay == stereo_mode->height &&
  2586. interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
  2587. drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
  2588. }
  2589. static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
  2590. {
  2591. struct drm_device *dev = connector->dev;
  2592. const struct drm_display_mode *mode;
  2593. struct list_head stereo_modes;
  2594. int modes = 0, i;
  2595. INIT_LIST_HEAD(&stereo_modes);
  2596. list_for_each_entry(mode, &connector->probed_modes, head) {
  2597. for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
  2598. const struct stereo_mandatory_mode *mandatory;
  2599. struct drm_display_mode *new_mode;
  2600. if (!stereo_match_mandatory(mode,
  2601. &stereo_mandatory_modes[i]))
  2602. continue;
  2603. mandatory = &stereo_mandatory_modes[i];
  2604. new_mode = drm_mode_duplicate(dev, mode);
  2605. if (!new_mode)
  2606. continue;
  2607. new_mode->flags |= mandatory->flags;
  2608. list_add_tail(&new_mode->head, &stereo_modes);
  2609. modes++;
  2610. }
  2611. }
  2612. list_splice_tail(&stereo_modes, &connector->probed_modes);
  2613. return modes;
  2614. }
  2615. static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
  2616. {
  2617. struct drm_device *dev = connector->dev;
  2618. struct drm_display_mode *newmode;
  2619. if (!drm_valid_hdmi_vic(vic)) {
  2620. DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
  2621. return 0;
  2622. }
  2623. newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
  2624. if (!newmode)
  2625. return 0;
  2626. drm_mode_probed_add(connector, newmode);
  2627. return 1;
  2628. }
  2629. static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
  2630. const u8 *video_db, u8 video_len, u8 video_index)
  2631. {
  2632. struct drm_display_mode *newmode;
  2633. int modes = 0;
  2634. if (structure & (1 << 0)) {
  2635. newmode = drm_display_mode_from_vic_index(connector, video_db,
  2636. video_len,
  2637. video_index);
  2638. if (newmode) {
  2639. newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
  2640. drm_mode_probed_add(connector, newmode);
  2641. modes++;
  2642. }
  2643. }
  2644. if (structure & (1 << 6)) {
  2645. newmode = drm_display_mode_from_vic_index(connector, video_db,
  2646. video_len,
  2647. video_index);
  2648. if (newmode) {
  2649. newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
  2650. drm_mode_probed_add(connector, newmode);
  2651. modes++;
  2652. }
  2653. }
  2654. if (structure & (1 << 8)) {
  2655. newmode = drm_display_mode_from_vic_index(connector, video_db,
  2656. video_len,
  2657. video_index);
  2658. if (newmode) {
  2659. newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
  2660. drm_mode_probed_add(connector, newmode);
  2661. modes++;
  2662. }
  2663. }
  2664. return modes;
  2665. }
  2666. /*
  2667. * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
  2668. * @connector: connector corresponding to the HDMI sink
  2669. * @db: start of the CEA vendor specific block
  2670. * @len: length of the CEA block payload, ie. one can access up to db[len]
  2671. *
  2672. * Parses the HDMI VSDB looking for modes to add to @connector. This function
  2673. * also adds the stereo 3d modes when applicable.
  2674. */
  2675. static int
  2676. do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
  2677. const u8 *video_db, u8 video_len)
  2678. {
  2679. int modes = 0, offset = 0, i, multi_present = 0, multi_len;
  2680. u8 vic_len, hdmi_3d_len = 0;
  2681. u16 mask;
  2682. u16 structure_all;
  2683. if (len < 8)
  2684. goto out;
  2685. /* no HDMI_Video_Present */
  2686. if (!(db[8] & (1 << 5)))
  2687. goto out;
  2688. /* Latency_Fields_Present */
  2689. if (db[8] & (1 << 7))
  2690. offset += 2;
  2691. /* I_Latency_Fields_Present */
  2692. if (db[8] & (1 << 6))
  2693. offset += 2;
  2694. /* the declared length is not long enough for the 2 first bytes
  2695. * of additional video format capabilities */
  2696. if (len < (8 + offset + 2))
  2697. goto out;
  2698. /* 3D_Present */
  2699. offset++;
  2700. if (db[8 + offset] & (1 << 7)) {
  2701. modes += add_hdmi_mandatory_stereo_modes(connector);
  2702. /* 3D_Multi_present */
  2703. multi_present = (db[8 + offset] & 0x60) >> 5;
  2704. }
  2705. offset++;
  2706. vic_len = db[8 + offset] >> 5;
  2707. hdmi_3d_len = db[8 + offset] & 0x1f;
  2708. for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
  2709. u8 vic;
  2710. vic = db[9 + offset + i];
  2711. modes += add_hdmi_mode(connector, vic);
  2712. }
  2713. offset += 1 + vic_len;
  2714. if (multi_present == 1)
  2715. multi_len = 2;
  2716. else if (multi_present == 2)
  2717. multi_len = 4;
  2718. else
  2719. multi_len = 0;
  2720. if (len < (8 + offset + hdmi_3d_len - 1))
  2721. goto out;
  2722. if (hdmi_3d_len < multi_len)
  2723. goto out;
  2724. if (multi_present == 1 || multi_present == 2) {
  2725. /* 3D_Structure_ALL */
  2726. structure_all = (db[8 + offset] << 8) | db[9 + offset];
  2727. /* check if 3D_MASK is present */
  2728. if (multi_present == 2)
  2729. mask = (db[10 + offset] << 8) | db[11 + offset];
  2730. else
  2731. mask = 0xffff;
  2732. for (i = 0; i < 16; i++) {
  2733. if (mask & (1 << i))
  2734. modes += add_3d_struct_modes(connector,
  2735. structure_all,
  2736. video_db,
  2737. video_len, i);
  2738. }
  2739. }
  2740. offset += multi_len;
  2741. for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
  2742. int vic_index;
  2743. struct drm_display_mode *newmode = NULL;
  2744. unsigned int newflag = 0;
  2745. bool detail_present;
  2746. detail_present = ((db[8 + offset + i] & 0x0f) > 7);
  2747. if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
  2748. break;
  2749. /* 2D_VIC_order_X */
  2750. vic_index = db[8 + offset + i] >> 4;
  2751. /* 3D_Structure_X */
  2752. switch (db[8 + offset + i] & 0x0f) {
  2753. case 0:
  2754. newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
  2755. break;
  2756. case 6:
  2757. newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
  2758. break;
  2759. case 8:
  2760. /* 3D_Detail_X */
  2761. if ((db[9 + offset + i] >> 4) == 1)
  2762. newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
  2763. break;
  2764. }
  2765. if (newflag != 0) {
  2766. newmode = drm_display_mode_from_vic_index(connector,
  2767. video_db,
  2768. video_len,
  2769. vic_index);
  2770. if (newmode) {
  2771. newmode->flags |= newflag;
  2772. drm_mode_probed_add(connector, newmode);
  2773. modes++;
  2774. }
  2775. }
  2776. if (detail_present)
  2777. i++;
  2778. }
  2779. out:
  2780. return modes;
  2781. }
  2782. static int
  2783. cea_db_payload_len(const u8 *db)
  2784. {
  2785. return db[0] & 0x1f;
  2786. }
  2787. static int
  2788. cea_db_tag(const u8 *db)
  2789. {
  2790. return db[0] >> 5;
  2791. }
  2792. static int
  2793. cea_revision(const u8 *cea)
  2794. {
  2795. return cea[1];
  2796. }
  2797. static int
  2798. cea_db_offsets(const u8 *cea, int *start, int *end)
  2799. {
  2800. /* Data block offset in CEA extension block */
  2801. *start = 4;
  2802. *end = cea[2];
  2803. if (*end == 0)
  2804. *end = 127;
  2805. if (*end < 4 || *end > 127)
  2806. return -ERANGE;
  2807. return 0;
  2808. }
  2809. static bool cea_db_is_hdmi_vsdb(const u8 *db)
  2810. {
  2811. int hdmi_id;
  2812. if (cea_db_tag(db) != VENDOR_BLOCK)
  2813. return false;
  2814. if (cea_db_payload_len(db) < 5)
  2815. return false;
  2816. hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
  2817. return hdmi_id == HDMI_IEEE_OUI;
  2818. }
  2819. #define for_each_cea_db(cea, i, start, end) \
  2820. for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
  2821. static int
  2822. add_cea_modes(struct drm_connector *connector, struct edid *edid)
  2823. {
  2824. const u8 *cea = drm_find_cea_extension(edid);
  2825. const u8 *db, *hdmi = NULL, *video = NULL;
  2826. u8 dbl, hdmi_len, video_len = 0;
  2827. int modes = 0;
  2828. if (cea && cea_revision(cea) >= 3) {
  2829. int i, start, end;
  2830. if (cea_db_offsets(cea, &start, &end))
  2831. return 0;
  2832. for_each_cea_db(cea, i, start, end) {
  2833. db = &cea[i];
  2834. dbl = cea_db_payload_len(db);
  2835. if (cea_db_tag(db) == VIDEO_BLOCK) {
  2836. video = db + 1;
  2837. video_len = dbl;
  2838. modes += do_cea_modes(connector, video, dbl);
  2839. }
  2840. else if (cea_db_is_hdmi_vsdb(db)) {
  2841. hdmi = db;
  2842. hdmi_len = dbl;
  2843. }
  2844. }
  2845. }
  2846. /*
  2847. * We parse the HDMI VSDB after having added the cea modes as we will
  2848. * be patching their flags when the sink supports stereo 3D.
  2849. */
  2850. if (hdmi)
  2851. modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
  2852. video_len);
  2853. return modes;
  2854. }
  2855. static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
  2856. {
  2857. const struct drm_display_mode *cea_mode;
  2858. int clock1, clock2, clock;
  2859. u8 vic;
  2860. const char *type;
  2861. /*
  2862. * allow 5kHz clock difference either way to account for
  2863. * the 10kHz clock resolution limit of detailed timings.
  2864. */
  2865. vic = drm_match_cea_mode_clock_tolerance(mode, 5);
  2866. if (drm_valid_cea_vic(vic)) {
  2867. type = "CEA";
  2868. cea_mode = &edid_cea_modes[vic];
  2869. clock1 = cea_mode->clock;
  2870. clock2 = cea_mode_alternate_clock(cea_mode);
  2871. } else {
  2872. vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
  2873. if (drm_valid_hdmi_vic(vic)) {
  2874. type = "HDMI";
  2875. cea_mode = &edid_4k_modes[vic];
  2876. clock1 = cea_mode->clock;
  2877. clock2 = hdmi_mode_alternate_clock(cea_mode);
  2878. } else {
  2879. return;
  2880. }
  2881. }
  2882. /* pick whichever is closest */
  2883. if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
  2884. clock = clock1;
  2885. else
  2886. clock = clock2;
  2887. if (mode->clock == clock)
  2888. return;
  2889. DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
  2890. type, vic, mode->clock, clock);
  2891. mode->clock = clock;
  2892. }
  2893. static void
  2894. drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
  2895. {
  2896. u8 len = cea_db_payload_len(db);
  2897. if (len >= 6)
  2898. connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
  2899. if (len >= 8) {
  2900. connector->latency_present[0] = db[8] >> 7;
  2901. connector->latency_present[1] = (db[8] >> 6) & 1;
  2902. }
  2903. if (len >= 9)
  2904. connector->video_latency[0] = db[9];
  2905. if (len >= 10)
  2906. connector->audio_latency[0] = db[10];
  2907. if (len >= 11)
  2908. connector->video_latency[1] = db[11];
  2909. if (len >= 12)
  2910. connector->audio_latency[1] = db[12];
  2911. DRM_DEBUG_KMS("HDMI: latency present %d %d, "
  2912. "video latency %d %d, "
  2913. "audio latency %d %d\n",
  2914. connector->latency_present[0],
  2915. connector->latency_present[1],
  2916. connector->video_latency[0],
  2917. connector->video_latency[1],
  2918. connector->audio_latency[0],
  2919. connector->audio_latency[1]);
  2920. }
  2921. static void
  2922. monitor_name(struct detailed_timing *t, void *data)
  2923. {
  2924. if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
  2925. *(u8 **)data = t->data.other_data.data.str.str;
  2926. }
  2927. static int get_monitor_name(struct edid *edid, char name[13])
  2928. {
  2929. char *edid_name = NULL;
  2930. int mnl;
  2931. if (!edid || !name)
  2932. return 0;
  2933. drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
  2934. for (mnl = 0; edid_name && mnl < 13; mnl++) {
  2935. if (edid_name[mnl] == 0x0a)
  2936. break;
  2937. name[mnl] = edid_name[mnl];
  2938. }
  2939. return mnl;
  2940. }
  2941. /**
  2942. * drm_edid_get_monitor_name - fetch the monitor name from the edid
  2943. * @edid: monitor EDID information
  2944. * @name: pointer to a character array to hold the name of the monitor
  2945. * @bufsize: The size of the name buffer (should be at least 14 chars.)
  2946. *
  2947. */
  2948. void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
  2949. {
  2950. int name_length;
  2951. char buf[13];
  2952. if (bufsize <= 0)
  2953. return;
  2954. name_length = min(get_monitor_name(edid, buf), bufsize - 1);
  2955. memcpy(name, buf, name_length);
  2956. name[name_length] = '\0';
  2957. }
  2958. EXPORT_SYMBOL(drm_edid_get_monitor_name);
  2959. /**
  2960. * drm_edid_to_eld - build ELD from EDID
  2961. * @connector: connector corresponding to the HDMI/DP sink
  2962. * @edid: EDID to parse
  2963. *
  2964. * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
  2965. * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
  2966. */
  2967. void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
  2968. {
  2969. uint8_t *eld = connector->eld;
  2970. u8 *cea;
  2971. u8 *db;
  2972. int total_sad_count = 0;
  2973. int mnl;
  2974. int dbl;
  2975. memset(eld, 0, sizeof(connector->eld));
  2976. connector->latency_present[0] = false;
  2977. connector->latency_present[1] = false;
  2978. connector->video_latency[0] = 0;
  2979. connector->audio_latency[0] = 0;
  2980. connector->video_latency[1] = 0;
  2981. connector->audio_latency[1] = 0;
  2982. cea = drm_find_cea_extension(edid);
  2983. if (!cea) {
  2984. DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
  2985. return;
  2986. }
  2987. mnl = get_monitor_name(edid, eld + 20);
  2988. eld[4] = (cea[1] << 5) | mnl;
  2989. DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
  2990. eld[0] = 2 << 3; /* ELD version: 2 */
  2991. eld[16] = edid->mfg_id[0];
  2992. eld[17] = edid->mfg_id[1];
  2993. eld[18] = edid->prod_code[0];
  2994. eld[19] = edid->prod_code[1];
  2995. if (cea_revision(cea) >= 3) {
  2996. int i, start, end;
  2997. if (cea_db_offsets(cea, &start, &end)) {
  2998. start = 0;
  2999. end = 0;
  3000. }
  3001. for_each_cea_db(cea, i, start, end) {
  3002. db = &cea[i];
  3003. dbl = cea_db_payload_len(db);
  3004. switch (cea_db_tag(db)) {
  3005. int sad_count;
  3006. case AUDIO_BLOCK:
  3007. /* Audio Data Block, contains SADs */
  3008. sad_count = min(dbl / 3, 15 - total_sad_count);
  3009. if (sad_count >= 1)
  3010. memcpy(eld + 20 + mnl + total_sad_count * 3,
  3011. &db[1], sad_count * 3);
  3012. total_sad_count += sad_count;
  3013. break;
  3014. case SPEAKER_BLOCK:
  3015. /* Speaker Allocation Data Block */
  3016. if (dbl >= 1)
  3017. eld[7] = db[1];
  3018. break;
  3019. case VENDOR_BLOCK:
  3020. /* HDMI Vendor-Specific Data Block */
  3021. if (cea_db_is_hdmi_vsdb(db))
  3022. drm_parse_hdmi_vsdb_audio(connector, db);
  3023. break;
  3024. default:
  3025. break;
  3026. }
  3027. }
  3028. }
  3029. eld[5] |= total_sad_count << 4;
  3030. if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
  3031. connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  3032. eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
  3033. else
  3034. eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
  3035. eld[DRM_ELD_BASELINE_ELD_LEN] =
  3036. DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
  3037. DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
  3038. drm_eld_size(eld), total_sad_count);
  3039. }
  3040. EXPORT_SYMBOL(drm_edid_to_eld);
  3041. /**
  3042. * drm_edid_to_sad - extracts SADs from EDID
  3043. * @edid: EDID to parse
  3044. * @sads: pointer that will be set to the extracted SADs
  3045. *
  3046. * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
  3047. *
  3048. * Note: The returned pointer needs to be freed using kfree().
  3049. *
  3050. * Return: The number of found SADs or negative number on error.
  3051. */
  3052. int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
  3053. {
  3054. int count = 0;
  3055. int i, start, end, dbl;
  3056. u8 *cea;
  3057. cea = drm_find_cea_extension(edid);
  3058. if (!cea) {
  3059. DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
  3060. return -ENOENT;
  3061. }
  3062. if (cea_revision(cea) < 3) {
  3063. DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
  3064. return -ENOTSUPP;
  3065. }
  3066. if (cea_db_offsets(cea, &start, &end)) {
  3067. DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
  3068. return -EPROTO;
  3069. }
  3070. for_each_cea_db(cea, i, start, end) {
  3071. u8 *db = &cea[i];
  3072. if (cea_db_tag(db) == AUDIO_BLOCK) {
  3073. int j;
  3074. dbl = cea_db_payload_len(db);
  3075. count = dbl / 3; /* SAD is 3B */
  3076. *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
  3077. if (!*sads)
  3078. return -ENOMEM;
  3079. for (j = 0; j < count; j++) {
  3080. u8 *sad = &db[1 + j * 3];
  3081. (*sads)[j].format = (sad[0] & 0x78) >> 3;
  3082. (*sads)[j].channels = sad[0] & 0x7;
  3083. (*sads)[j].freq = sad[1] & 0x7F;
  3084. (*sads)[j].byte2 = sad[2];
  3085. }
  3086. break;
  3087. }
  3088. }
  3089. return count;
  3090. }
  3091. EXPORT_SYMBOL(drm_edid_to_sad);
  3092. /**
  3093. * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
  3094. * @edid: EDID to parse
  3095. * @sadb: pointer to the speaker block
  3096. *
  3097. * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
  3098. *
  3099. * Note: The returned pointer needs to be freed using kfree().
  3100. *
  3101. * Return: The number of found Speaker Allocation Blocks or negative number on
  3102. * error.
  3103. */
  3104. int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
  3105. {
  3106. int count = 0;
  3107. int i, start, end, dbl;
  3108. const u8 *cea;
  3109. cea = drm_find_cea_extension(edid);
  3110. if (!cea) {
  3111. DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
  3112. return -ENOENT;
  3113. }
  3114. if (cea_revision(cea) < 3) {
  3115. DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
  3116. return -ENOTSUPP;
  3117. }
  3118. if (cea_db_offsets(cea, &start, &end)) {
  3119. DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
  3120. return -EPROTO;
  3121. }
  3122. for_each_cea_db(cea, i, start, end) {
  3123. const u8 *db = &cea[i];
  3124. if (cea_db_tag(db) == SPEAKER_BLOCK) {
  3125. dbl = cea_db_payload_len(db);
  3126. /* Speaker Allocation Data Block */
  3127. if (dbl == 3) {
  3128. *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
  3129. if (!*sadb)
  3130. return -ENOMEM;
  3131. count = dbl;
  3132. break;
  3133. }
  3134. }
  3135. }
  3136. return count;
  3137. }
  3138. EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
  3139. /**
  3140. * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
  3141. * @connector: connector associated with the HDMI/DP sink
  3142. * @mode: the display mode
  3143. *
  3144. * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
  3145. * the sink doesn't support audio or video.
  3146. */
  3147. int drm_av_sync_delay(struct drm_connector *connector,
  3148. const struct drm_display_mode *mode)
  3149. {
  3150. int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
  3151. int a, v;
  3152. if (!connector->latency_present[0])
  3153. return 0;
  3154. if (!connector->latency_present[1])
  3155. i = 0;
  3156. a = connector->audio_latency[i];
  3157. v = connector->video_latency[i];
  3158. /*
  3159. * HDMI/DP sink doesn't support audio or video?
  3160. */
  3161. if (a == 255 || v == 255)
  3162. return 0;
  3163. /*
  3164. * Convert raw EDID values to millisecond.
  3165. * Treat unknown latency as 0ms.
  3166. */
  3167. if (a)
  3168. a = min(2 * (a - 1), 500);
  3169. if (v)
  3170. v = min(2 * (v - 1), 500);
  3171. return max(v - a, 0);
  3172. }
  3173. EXPORT_SYMBOL(drm_av_sync_delay);
  3174. /**
  3175. * drm_select_eld - select one ELD from multiple HDMI/DP sinks
  3176. * @encoder: the encoder just changed display mode
  3177. *
  3178. * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
  3179. * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
  3180. *
  3181. * Return: The connector associated with the first HDMI/DP sink that has ELD
  3182. * attached to it.
  3183. */
  3184. struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
  3185. {
  3186. struct drm_connector *connector;
  3187. struct drm_device *dev = encoder->dev;
  3188. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  3189. WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
  3190. drm_for_each_connector(connector, dev)
  3191. if (connector->encoder == encoder && connector->eld[0])
  3192. return connector;
  3193. return NULL;
  3194. }
  3195. EXPORT_SYMBOL(drm_select_eld);
  3196. /**
  3197. * drm_detect_hdmi_monitor - detect whether monitor is HDMI
  3198. * @edid: monitor EDID information
  3199. *
  3200. * Parse the CEA extension according to CEA-861-B.
  3201. *
  3202. * Return: True if the monitor is HDMI, false if not or unknown.
  3203. */
  3204. bool drm_detect_hdmi_monitor(struct edid *edid)
  3205. {
  3206. u8 *edid_ext;
  3207. int i;
  3208. int start_offset, end_offset;
  3209. edid_ext = drm_find_cea_extension(edid);
  3210. if (!edid_ext)
  3211. return false;
  3212. if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
  3213. return false;
  3214. /*
  3215. * Because HDMI identifier is in Vendor Specific Block,
  3216. * search it from all data blocks of CEA extension.
  3217. */
  3218. for_each_cea_db(edid_ext, i, start_offset, end_offset) {
  3219. if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
  3220. return true;
  3221. }
  3222. return false;
  3223. }
  3224. EXPORT_SYMBOL(drm_detect_hdmi_monitor);
  3225. /**
  3226. * drm_detect_monitor_audio - check monitor audio capability
  3227. * @edid: EDID block to scan
  3228. *
  3229. * Monitor should have CEA extension block.
  3230. * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
  3231. * audio' only. If there is any audio extension block and supported
  3232. * audio format, assume at least 'basic audio' support, even if 'basic
  3233. * audio' is not defined in EDID.
  3234. *
  3235. * Return: True if the monitor supports audio, false otherwise.
  3236. */
  3237. bool drm_detect_monitor_audio(struct edid *edid)
  3238. {
  3239. u8 *edid_ext;
  3240. int i, j;
  3241. bool has_audio = false;
  3242. int start_offset, end_offset;
  3243. edid_ext = drm_find_cea_extension(edid);
  3244. if (!edid_ext)
  3245. goto end;
  3246. has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
  3247. if (has_audio) {
  3248. DRM_DEBUG_KMS("Monitor has basic audio support\n");
  3249. goto end;
  3250. }
  3251. if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
  3252. goto end;
  3253. for_each_cea_db(edid_ext, i, start_offset, end_offset) {
  3254. if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
  3255. has_audio = true;
  3256. for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
  3257. DRM_DEBUG_KMS("CEA audio format %d\n",
  3258. (edid_ext[i + j] >> 3) & 0xf);
  3259. goto end;
  3260. }
  3261. }
  3262. end:
  3263. return has_audio;
  3264. }
  3265. EXPORT_SYMBOL(drm_detect_monitor_audio);
  3266. /**
  3267. * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
  3268. * @edid: EDID block to scan
  3269. *
  3270. * Check whether the monitor reports the RGB quantization range selection
  3271. * as supported. The AVI infoframe can then be used to inform the monitor
  3272. * which quantization range (full or limited) is used.
  3273. *
  3274. * Return: True if the RGB quantization range is selectable, false otherwise.
  3275. */
  3276. bool drm_rgb_quant_range_selectable(struct edid *edid)
  3277. {
  3278. u8 *edid_ext;
  3279. int i, start, end;
  3280. edid_ext = drm_find_cea_extension(edid);
  3281. if (!edid_ext)
  3282. return false;
  3283. if (cea_db_offsets(edid_ext, &start, &end))
  3284. return false;
  3285. for_each_cea_db(edid_ext, i, start, end) {
  3286. if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
  3287. cea_db_payload_len(&edid_ext[i]) == 2) {
  3288. DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
  3289. return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
  3290. }
  3291. }
  3292. return false;
  3293. }
  3294. EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
  3295. static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
  3296. const u8 *hdmi)
  3297. {
  3298. struct drm_display_info *info = &connector->display_info;
  3299. unsigned int dc_bpc = 0;
  3300. /* HDMI supports at least 8 bpc */
  3301. info->bpc = 8;
  3302. if (cea_db_payload_len(hdmi) < 6)
  3303. return;
  3304. if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
  3305. dc_bpc = 10;
  3306. info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
  3307. DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
  3308. connector->name);
  3309. }
  3310. if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
  3311. dc_bpc = 12;
  3312. info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
  3313. DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
  3314. connector->name);
  3315. }
  3316. if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
  3317. dc_bpc = 16;
  3318. info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
  3319. DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
  3320. connector->name);
  3321. }
  3322. if (dc_bpc == 0) {
  3323. DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
  3324. connector->name);
  3325. return;
  3326. }
  3327. DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
  3328. connector->name, dc_bpc);
  3329. info->bpc = dc_bpc;
  3330. /*
  3331. * Deep color support mandates RGB444 support for all video
  3332. * modes and forbids YCRCB422 support for all video modes per
  3333. * HDMI 1.3 spec.
  3334. */
  3335. info->color_formats = DRM_COLOR_FORMAT_RGB444;
  3336. /* YCRCB444 is optional according to spec. */
  3337. if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
  3338. info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
  3339. DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
  3340. connector->name);
  3341. }
  3342. /*
  3343. * Spec says that if any deep color mode is supported at all,
  3344. * then deep color 36 bit must be supported.
  3345. */
  3346. if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
  3347. DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
  3348. connector->name);
  3349. }
  3350. }
  3351. static void
  3352. drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
  3353. {
  3354. struct drm_display_info *info = &connector->display_info;
  3355. u8 len = cea_db_payload_len(db);
  3356. if (len >= 6)
  3357. info->dvi_dual = db[6] & 1;
  3358. if (len >= 7)
  3359. info->max_tmds_clock = db[7] * 5000;
  3360. DRM_DEBUG_KMS("HDMI: DVI dual %d, "
  3361. "max TMDS clock %d kHz\n",
  3362. info->dvi_dual,
  3363. info->max_tmds_clock);
  3364. drm_parse_hdmi_deep_color_info(connector, db);
  3365. }
  3366. static void drm_parse_cea_ext(struct drm_connector *connector,
  3367. struct edid *edid)
  3368. {
  3369. struct drm_display_info *info = &connector->display_info;
  3370. const u8 *edid_ext;
  3371. int i, start, end;
  3372. edid_ext = drm_find_cea_extension(edid);
  3373. if (!edid_ext)
  3374. return;
  3375. info->cea_rev = edid_ext[1];
  3376. /* The existence of a CEA block should imply RGB support */
  3377. info->color_formats = DRM_COLOR_FORMAT_RGB444;
  3378. if (edid_ext[3] & EDID_CEA_YCRCB444)
  3379. info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
  3380. if (edid_ext[3] & EDID_CEA_YCRCB422)
  3381. info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
  3382. if (cea_db_offsets(edid_ext, &start, &end))
  3383. return;
  3384. for_each_cea_db(edid_ext, i, start, end) {
  3385. const u8 *db = &edid_ext[i];
  3386. if (cea_db_is_hdmi_vsdb(db))
  3387. drm_parse_hdmi_vsdb_video(connector, db);
  3388. }
  3389. }
  3390. static void drm_add_display_info(struct drm_connector *connector,
  3391. struct edid *edid)
  3392. {
  3393. struct drm_display_info *info = &connector->display_info;
  3394. info->width_mm = edid->width_cm * 10;
  3395. info->height_mm = edid->height_cm * 10;
  3396. /* driver figures it out in this case */
  3397. info->bpc = 0;
  3398. info->color_formats = 0;
  3399. info->cea_rev = 0;
  3400. info->max_tmds_clock = 0;
  3401. info->dvi_dual = false;
  3402. if (edid->revision < 3)
  3403. return;
  3404. if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
  3405. return;
  3406. drm_parse_cea_ext(connector, edid);
  3407. /*
  3408. * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
  3409. *
  3410. * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
  3411. * tells us to assume 8 bpc color depth if the EDID doesn't have
  3412. * extensions which tell otherwise.
  3413. */
  3414. if ((info->bpc == 0) && (edid->revision < 4) &&
  3415. (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
  3416. info->bpc = 8;
  3417. DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
  3418. connector->name, info->bpc);
  3419. }
  3420. /* Only defined for 1.4 with digital displays */
  3421. if (edid->revision < 4)
  3422. return;
  3423. switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
  3424. case DRM_EDID_DIGITAL_DEPTH_6:
  3425. info->bpc = 6;
  3426. break;
  3427. case DRM_EDID_DIGITAL_DEPTH_8:
  3428. info->bpc = 8;
  3429. break;
  3430. case DRM_EDID_DIGITAL_DEPTH_10:
  3431. info->bpc = 10;
  3432. break;
  3433. case DRM_EDID_DIGITAL_DEPTH_12:
  3434. info->bpc = 12;
  3435. break;
  3436. case DRM_EDID_DIGITAL_DEPTH_14:
  3437. info->bpc = 14;
  3438. break;
  3439. case DRM_EDID_DIGITAL_DEPTH_16:
  3440. info->bpc = 16;
  3441. break;
  3442. case DRM_EDID_DIGITAL_DEPTH_UNDEF:
  3443. default:
  3444. info->bpc = 0;
  3445. break;
  3446. }
  3447. DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
  3448. connector->name, info->bpc);
  3449. info->color_formats |= DRM_COLOR_FORMAT_RGB444;
  3450. if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
  3451. info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
  3452. if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
  3453. info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
  3454. }
  3455. static int validate_displayid(u8 *displayid, int length, int idx)
  3456. {
  3457. int i;
  3458. u8 csum = 0;
  3459. struct displayid_hdr *base;
  3460. base = (struct displayid_hdr *)&displayid[idx];
  3461. DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
  3462. base->rev, base->bytes, base->prod_id, base->ext_count);
  3463. if (base->bytes + 5 > length - idx)
  3464. return -EINVAL;
  3465. for (i = idx; i <= base->bytes + 5; i++) {
  3466. csum += displayid[i];
  3467. }
  3468. if (csum) {
  3469. DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
  3470. return -EINVAL;
  3471. }
  3472. return 0;
  3473. }
  3474. static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
  3475. struct displayid_detailed_timings_1 *timings)
  3476. {
  3477. struct drm_display_mode *mode;
  3478. unsigned pixel_clock = (timings->pixel_clock[0] |
  3479. (timings->pixel_clock[1] << 8) |
  3480. (timings->pixel_clock[2] << 16));
  3481. unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
  3482. unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
  3483. unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
  3484. unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
  3485. unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
  3486. unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
  3487. unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
  3488. unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
  3489. bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
  3490. bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
  3491. mode = drm_mode_create(dev);
  3492. if (!mode)
  3493. return NULL;
  3494. mode->clock = pixel_clock * 10;
  3495. mode->hdisplay = hactive;
  3496. mode->hsync_start = mode->hdisplay + hsync;
  3497. mode->hsync_end = mode->hsync_start + hsync_width;
  3498. mode->htotal = mode->hdisplay + hblank;
  3499. mode->vdisplay = vactive;
  3500. mode->vsync_start = mode->vdisplay + vsync;
  3501. mode->vsync_end = mode->vsync_start + vsync_width;
  3502. mode->vtotal = mode->vdisplay + vblank;
  3503. mode->flags = 0;
  3504. mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
  3505. mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
  3506. mode->type = DRM_MODE_TYPE_DRIVER;
  3507. if (timings->flags & 0x80)
  3508. mode->type |= DRM_MODE_TYPE_PREFERRED;
  3509. mode->vrefresh = drm_mode_vrefresh(mode);
  3510. drm_mode_set_name(mode);
  3511. return mode;
  3512. }
  3513. static int add_displayid_detailed_1_modes(struct drm_connector *connector,
  3514. struct displayid_block *block)
  3515. {
  3516. struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
  3517. int i;
  3518. int num_timings;
  3519. struct drm_display_mode *newmode;
  3520. int num_modes = 0;
  3521. /* blocks must be multiple of 20 bytes length */
  3522. if (block->num_bytes % 20)
  3523. return 0;
  3524. num_timings = block->num_bytes / 20;
  3525. for (i = 0; i < num_timings; i++) {
  3526. struct displayid_detailed_timings_1 *timings = &det->timings[i];
  3527. newmode = drm_mode_displayid_detailed(connector->dev, timings);
  3528. if (!newmode)
  3529. continue;
  3530. drm_mode_probed_add(connector, newmode);
  3531. num_modes++;
  3532. }
  3533. return num_modes;
  3534. }
  3535. static int add_displayid_detailed_modes(struct drm_connector *connector,
  3536. struct edid *edid)
  3537. {
  3538. u8 *displayid;
  3539. int ret;
  3540. int idx = 1;
  3541. int length = EDID_LENGTH;
  3542. struct displayid_block *block;
  3543. int num_modes = 0;
  3544. displayid = drm_find_displayid_extension(edid);
  3545. if (!displayid)
  3546. return 0;
  3547. ret = validate_displayid(displayid, length, idx);
  3548. if (ret)
  3549. return 0;
  3550. idx += sizeof(struct displayid_hdr);
  3551. while (block = (struct displayid_block *)&displayid[idx],
  3552. idx + sizeof(struct displayid_block) <= length &&
  3553. idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
  3554. block->num_bytes > 0) {
  3555. idx += block->num_bytes + sizeof(struct displayid_block);
  3556. switch (block->tag) {
  3557. case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
  3558. num_modes += add_displayid_detailed_1_modes(connector, block);
  3559. break;
  3560. }
  3561. }
  3562. return num_modes;
  3563. }
  3564. /**
  3565. * drm_add_edid_modes - add modes from EDID data, if available
  3566. * @connector: connector we're probing
  3567. * @edid: EDID data
  3568. *
  3569. * Add the specified modes to the connector's mode list. Also fills out the
  3570. * &drm_display_info structure in @connector with any information which can be
  3571. * derived from the edid.
  3572. *
  3573. * Return: The number of modes added or 0 if we couldn't find any.
  3574. */
  3575. int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
  3576. {
  3577. int num_modes = 0;
  3578. u32 quirks;
  3579. if (edid == NULL) {
  3580. return 0;
  3581. }
  3582. if (!drm_edid_is_valid(edid)) {
  3583. dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
  3584. connector->name);
  3585. return 0;
  3586. }
  3587. quirks = edid_get_quirks(edid);
  3588. /*
  3589. * EDID spec says modes should be preferred in this order:
  3590. * - preferred detailed mode
  3591. * - other detailed modes from base block
  3592. * - detailed modes from extension blocks
  3593. * - CVT 3-byte code modes
  3594. * - standard timing codes
  3595. * - established timing codes
  3596. * - modes inferred from GTF or CVT range information
  3597. *
  3598. * We get this pretty much right.
  3599. *
  3600. * XXX order for additional mode types in extension blocks?
  3601. */
  3602. num_modes += add_detailed_modes(connector, edid, quirks);
  3603. num_modes += add_cvt_modes(connector, edid);
  3604. num_modes += add_standard_modes(connector, edid);
  3605. num_modes += add_established_modes(connector, edid);
  3606. num_modes += add_cea_modes(connector, edid);
  3607. num_modes += add_alternate_cea_modes(connector, edid);
  3608. num_modes += add_displayid_detailed_modes(connector, edid);
  3609. if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
  3610. num_modes += add_inferred_modes(connector, edid);
  3611. if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
  3612. edid_fixup_preferred(connector, quirks);
  3613. drm_add_display_info(connector, edid);
  3614. if (quirks & EDID_QUIRK_FORCE_6BPC)
  3615. connector->display_info.bpc = 6;
  3616. if (quirks & EDID_QUIRK_FORCE_8BPC)
  3617. connector->display_info.bpc = 8;
  3618. if (quirks & EDID_QUIRK_FORCE_10BPC)
  3619. connector->display_info.bpc = 10;
  3620. if (quirks & EDID_QUIRK_FORCE_12BPC)
  3621. connector->display_info.bpc = 12;
  3622. return num_modes;
  3623. }
  3624. EXPORT_SYMBOL(drm_add_edid_modes);
  3625. /**
  3626. * drm_add_modes_noedid - add modes for the connectors without EDID
  3627. * @connector: connector we're probing
  3628. * @hdisplay: the horizontal display limit
  3629. * @vdisplay: the vertical display limit
  3630. *
  3631. * Add the specified modes to the connector's mode list. Only when the
  3632. * hdisplay/vdisplay is not beyond the given limit, it will be added.
  3633. *
  3634. * Return: The number of modes added or 0 if we couldn't find any.
  3635. */
  3636. int drm_add_modes_noedid(struct drm_connector *connector,
  3637. int hdisplay, int vdisplay)
  3638. {
  3639. int i, count, num_modes = 0;
  3640. struct drm_display_mode *mode;
  3641. struct drm_device *dev = connector->dev;
  3642. count = ARRAY_SIZE(drm_dmt_modes);
  3643. if (hdisplay < 0)
  3644. hdisplay = 0;
  3645. if (vdisplay < 0)
  3646. vdisplay = 0;
  3647. for (i = 0; i < count; i++) {
  3648. const struct drm_display_mode *ptr = &drm_dmt_modes[i];
  3649. if (hdisplay && vdisplay) {
  3650. /*
  3651. * Only when two are valid, they will be used to check
  3652. * whether the mode should be added to the mode list of
  3653. * the connector.
  3654. */
  3655. if (ptr->hdisplay > hdisplay ||
  3656. ptr->vdisplay > vdisplay)
  3657. continue;
  3658. }
  3659. if (drm_mode_vrefresh(ptr) > 61)
  3660. continue;
  3661. mode = drm_mode_duplicate(dev, ptr);
  3662. if (mode) {
  3663. drm_mode_probed_add(connector, mode);
  3664. num_modes++;
  3665. }
  3666. }
  3667. return num_modes;
  3668. }
  3669. EXPORT_SYMBOL(drm_add_modes_noedid);
  3670. /**
  3671. * drm_set_preferred_mode - Sets the preferred mode of a connector
  3672. * @connector: connector whose mode list should be processed
  3673. * @hpref: horizontal resolution of preferred mode
  3674. * @vpref: vertical resolution of preferred mode
  3675. *
  3676. * Marks a mode as preferred if it matches the resolution specified by @hpref
  3677. * and @vpref.
  3678. */
  3679. void drm_set_preferred_mode(struct drm_connector *connector,
  3680. int hpref, int vpref)
  3681. {
  3682. struct drm_display_mode *mode;
  3683. list_for_each_entry(mode, &connector->probed_modes, head) {
  3684. if (mode->hdisplay == hpref &&
  3685. mode->vdisplay == vpref)
  3686. mode->type |= DRM_MODE_TYPE_PREFERRED;
  3687. }
  3688. }
  3689. EXPORT_SYMBOL(drm_set_preferred_mode);
  3690. /**
  3691. * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
  3692. * data from a DRM display mode
  3693. * @frame: HDMI AVI infoframe
  3694. * @mode: DRM display mode
  3695. *
  3696. * Return: 0 on success or a negative error code on failure.
  3697. */
  3698. int
  3699. drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
  3700. const struct drm_display_mode *mode)
  3701. {
  3702. int err;
  3703. if (!frame || !mode)
  3704. return -EINVAL;
  3705. err = hdmi_avi_infoframe_init(frame);
  3706. if (err < 0)
  3707. return err;
  3708. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  3709. frame->pixel_repeat = 1;
  3710. frame->video_code = drm_match_cea_mode(mode);
  3711. frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
  3712. /*
  3713. * Populate picture aspect ratio from either
  3714. * user input (if specified) or from the CEA mode list.
  3715. */
  3716. if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
  3717. mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
  3718. frame->picture_aspect = mode->picture_aspect_ratio;
  3719. else if (frame->video_code > 0)
  3720. frame->picture_aspect = drm_get_cea_aspect_ratio(
  3721. frame->video_code);
  3722. frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
  3723. frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
  3724. return 0;
  3725. }
  3726. EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
  3727. static enum hdmi_3d_structure
  3728. s3d_structure_from_display_mode(const struct drm_display_mode *mode)
  3729. {
  3730. u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
  3731. switch (layout) {
  3732. case DRM_MODE_FLAG_3D_FRAME_PACKING:
  3733. return HDMI_3D_STRUCTURE_FRAME_PACKING;
  3734. case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
  3735. return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
  3736. case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
  3737. return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
  3738. case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
  3739. return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
  3740. case DRM_MODE_FLAG_3D_L_DEPTH:
  3741. return HDMI_3D_STRUCTURE_L_DEPTH;
  3742. case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
  3743. return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
  3744. case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
  3745. return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
  3746. case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
  3747. return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
  3748. default:
  3749. return HDMI_3D_STRUCTURE_INVALID;
  3750. }
  3751. }
  3752. /**
  3753. * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
  3754. * data from a DRM display mode
  3755. * @frame: HDMI vendor infoframe
  3756. * @mode: DRM display mode
  3757. *
  3758. * Note that there's is a need to send HDMI vendor infoframes only when using a
  3759. * 4k or stereoscopic 3D mode. So when giving any other mode as input this
  3760. * function will return -EINVAL, error that can be safely ignored.
  3761. *
  3762. * Return: 0 on success or a negative error code on failure.
  3763. */
  3764. int
  3765. drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
  3766. const struct drm_display_mode *mode)
  3767. {
  3768. int err;
  3769. u32 s3d_flags;
  3770. u8 vic;
  3771. if (!frame || !mode)
  3772. return -EINVAL;
  3773. vic = drm_match_hdmi_mode(mode);
  3774. s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
  3775. if (!vic && !s3d_flags)
  3776. return -EINVAL;
  3777. if (vic && s3d_flags)
  3778. return -EINVAL;
  3779. err = hdmi_vendor_infoframe_init(frame);
  3780. if (err < 0)
  3781. return err;
  3782. if (vic)
  3783. frame->vic = vic;
  3784. else
  3785. frame->s3d_struct = s3d_structure_from_display_mode(mode);
  3786. return 0;
  3787. }
  3788. EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
  3789. static int drm_parse_tiled_block(struct drm_connector *connector,
  3790. struct displayid_block *block)
  3791. {
  3792. struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
  3793. u16 w, h;
  3794. u8 tile_v_loc, tile_h_loc;
  3795. u8 num_v_tile, num_h_tile;
  3796. struct drm_tile_group *tg;
  3797. w = tile->tile_size[0] | tile->tile_size[1] << 8;
  3798. h = tile->tile_size[2] | tile->tile_size[3] << 8;
  3799. num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
  3800. num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
  3801. tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
  3802. tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
  3803. connector->has_tile = true;
  3804. if (tile->tile_cap & 0x80)
  3805. connector->tile_is_single_monitor = true;
  3806. connector->num_h_tile = num_h_tile + 1;
  3807. connector->num_v_tile = num_v_tile + 1;
  3808. connector->tile_h_loc = tile_h_loc;
  3809. connector->tile_v_loc = tile_v_loc;
  3810. connector->tile_h_size = w + 1;
  3811. connector->tile_v_size = h + 1;
  3812. DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
  3813. DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
  3814. DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
  3815. num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
  3816. DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
  3817. tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
  3818. if (!tg) {
  3819. tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
  3820. }
  3821. if (!tg)
  3822. return -ENOMEM;
  3823. if (connector->tile_group != tg) {
  3824. /* if we haven't got a pointer,
  3825. take the reference, drop ref to old tile group */
  3826. if (connector->tile_group) {
  3827. drm_mode_put_tile_group(connector->dev, connector->tile_group);
  3828. }
  3829. connector->tile_group = tg;
  3830. } else
  3831. /* if same tile group, then release the ref we just took. */
  3832. drm_mode_put_tile_group(connector->dev, tg);
  3833. return 0;
  3834. }
  3835. static int drm_parse_display_id(struct drm_connector *connector,
  3836. u8 *displayid, int length,
  3837. bool is_edid_extension)
  3838. {
  3839. /* if this is an EDID extension the first byte will be 0x70 */
  3840. int idx = 0;
  3841. struct displayid_block *block;
  3842. int ret;
  3843. if (is_edid_extension)
  3844. idx = 1;
  3845. ret = validate_displayid(displayid, length, idx);
  3846. if (ret)
  3847. return ret;
  3848. idx += sizeof(struct displayid_hdr);
  3849. while (block = (struct displayid_block *)&displayid[idx],
  3850. idx + sizeof(struct displayid_block) <= length &&
  3851. idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
  3852. block->num_bytes > 0) {
  3853. idx += block->num_bytes + sizeof(struct displayid_block);
  3854. DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
  3855. block->tag, block->rev, block->num_bytes);
  3856. switch (block->tag) {
  3857. case DATA_BLOCK_TILED_DISPLAY:
  3858. ret = drm_parse_tiled_block(connector, block);
  3859. if (ret)
  3860. return ret;
  3861. break;
  3862. case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
  3863. /* handled in mode gathering code. */
  3864. break;
  3865. default:
  3866. DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
  3867. break;
  3868. }
  3869. }
  3870. return 0;
  3871. }
  3872. static void drm_get_displayid(struct drm_connector *connector,
  3873. struct edid *edid)
  3874. {
  3875. void *displayid = NULL;
  3876. int ret;
  3877. connector->has_tile = false;
  3878. displayid = drm_find_displayid_extension(edid);
  3879. if (!displayid) {
  3880. /* drop reference to any tile group we had */
  3881. goto out_drop_ref;
  3882. }
  3883. ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
  3884. if (ret < 0)
  3885. goto out_drop_ref;
  3886. if (!connector->has_tile)
  3887. goto out_drop_ref;
  3888. return;
  3889. out_drop_ref:
  3890. if (connector->tile_group) {
  3891. drm_mode_put_tile_group(connector->dev, connector->tile_group);
  3892. connector->tile_group = NULL;
  3893. }
  3894. return;
  3895. }