tegra-devfreq.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790
  1. /*
  2. * A devfreq driver for NVIDIA Tegra SoCs
  3. *
  4. * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
  5. * Copyright (C) 2014 Google, Inc
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. *
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/cpufreq.h>
  22. #include <linux/devfreq.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/io.h>
  25. #include <linux/module.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/pm_opp.h>
  28. #include <linux/reset.h>
  29. #include "governor.h"
  30. #define ACTMON_GLB_STATUS 0x0
  31. #define ACTMON_GLB_PERIOD_CTRL 0x4
  32. #define ACTMON_DEV_CTRL 0x0
  33. #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10
  34. #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
  35. #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20)
  36. #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21)
  37. #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23
  38. #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26
  39. #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29)
  40. #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30)
  41. #define ACTMON_DEV_CTRL_ENB BIT(31)
  42. #define ACTMON_DEV_UPPER_WMARK 0x4
  43. #define ACTMON_DEV_LOWER_WMARK 0x8
  44. #define ACTMON_DEV_INIT_AVG 0xc
  45. #define ACTMON_DEV_AVG_UPPER_WMARK 0x10
  46. #define ACTMON_DEV_AVG_LOWER_WMARK 0x14
  47. #define ACTMON_DEV_COUNT_WEIGHT 0x18
  48. #define ACTMON_DEV_AVG_COUNT 0x20
  49. #define ACTMON_DEV_INTR_STATUS 0x24
  50. #define ACTMON_INTR_STATUS_CLEAR 0xffffffff
  51. #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31)
  52. #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30)
  53. #define ACTMON_ABOVE_WMARK_WINDOW 1
  54. #define ACTMON_BELOW_WMARK_WINDOW 3
  55. #define ACTMON_BOOST_FREQ_STEP 16000
  56. /*
  57. * Activity counter is incremented every 256 memory transactions, and each
  58. * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
  59. * 4 * 256 = 1024.
  60. */
  61. #define ACTMON_COUNT_WEIGHT 0x400
  62. /*
  63. * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which
  64. * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
  65. */
  66. #define ACTMON_AVERAGE_WINDOW_LOG2 6
  67. #define ACTMON_SAMPLING_PERIOD 12 /* ms */
  68. #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */
  69. #define KHZ 1000
  70. /* Assume that the bus is saturated if the utilization is 25% */
  71. #define BUS_SATURATION_RATIO 25
  72. /**
  73. * struct tegra_devfreq_device_config - configuration specific to an ACTMON
  74. * device
  75. *
  76. * Coefficients and thresholds are percentages unless otherwise noted
  77. */
  78. struct tegra_devfreq_device_config {
  79. u32 offset;
  80. u32 irq_mask;
  81. /* Factors applied to boost_freq every consecutive watermark breach */
  82. unsigned int boost_up_coeff;
  83. unsigned int boost_down_coeff;
  84. /* Define the watermark bounds when applied to the current avg */
  85. unsigned int boost_up_threshold;
  86. unsigned int boost_down_threshold;
  87. /*
  88. * Threshold of activity (cycles) below which the CPU frequency isn't
  89. * to be taken into account. This is to avoid increasing the EMC
  90. * frequency when the CPU is very busy but not accessing the bus often.
  91. */
  92. u32 avg_dependency_threshold;
  93. };
  94. enum tegra_actmon_device {
  95. MCALL = 0,
  96. MCCPU,
  97. };
  98. static struct tegra_devfreq_device_config actmon_device_configs[] = {
  99. {
  100. /* MCALL: All memory accesses (including from the CPUs) */
  101. .offset = 0x1c0,
  102. .irq_mask = 1 << 26,
  103. .boost_up_coeff = 200,
  104. .boost_down_coeff = 50,
  105. .boost_up_threshold = 60,
  106. .boost_down_threshold = 40,
  107. },
  108. {
  109. /* MCCPU: memory accesses from the CPUs */
  110. .offset = 0x200,
  111. .irq_mask = 1 << 25,
  112. .boost_up_coeff = 800,
  113. .boost_down_coeff = 90,
  114. .boost_up_threshold = 27,
  115. .boost_down_threshold = 10,
  116. .avg_dependency_threshold = 50000,
  117. },
  118. };
  119. /**
  120. * struct tegra_devfreq_device - state specific to an ACTMON device
  121. *
  122. * Frequencies are in kHz.
  123. */
  124. struct tegra_devfreq_device {
  125. const struct tegra_devfreq_device_config *config;
  126. void __iomem *regs;
  127. spinlock_t lock;
  128. /* Average event count sampled in the last interrupt */
  129. u32 avg_count;
  130. /*
  131. * Extra frequency to increase the target by due to consecutive
  132. * watermark breaches.
  133. */
  134. unsigned long boost_freq;
  135. /* Optimal frequency calculated from the stats for this device */
  136. unsigned long target_freq;
  137. };
  138. struct tegra_devfreq {
  139. struct devfreq *devfreq;
  140. struct reset_control *reset;
  141. struct clk *clock;
  142. void __iomem *regs;
  143. struct clk *emc_clock;
  144. unsigned long max_freq;
  145. unsigned long cur_freq;
  146. struct notifier_block rate_change_nb;
  147. struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)];
  148. };
  149. struct tegra_actmon_emc_ratio {
  150. unsigned long cpu_freq;
  151. unsigned long emc_freq;
  152. };
  153. static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = {
  154. { 1400000, ULONG_MAX },
  155. { 1200000, 750000 },
  156. { 1100000, 600000 },
  157. { 1000000, 500000 },
  158. { 800000, 375000 },
  159. { 500000, 200000 },
  160. { 250000, 100000 },
  161. };
  162. static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset)
  163. {
  164. return readl(tegra->regs + offset);
  165. }
  166. static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
  167. {
  168. writel(val, tegra->regs + offset);
  169. }
  170. static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset)
  171. {
  172. return readl(dev->regs + offset);
  173. }
  174. static void device_writel(struct tegra_devfreq_device *dev, u32 val,
  175. u32 offset)
  176. {
  177. writel(val, dev->regs + offset);
  178. }
  179. static unsigned long do_percent(unsigned long val, unsigned int pct)
  180. {
  181. return val * pct / 100;
  182. }
  183. static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra,
  184. struct tegra_devfreq_device *dev)
  185. {
  186. u32 avg = dev->avg_count;
  187. u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ;
  188. u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD;
  189. device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK);
  190. avg = max(dev->avg_count, band);
  191. device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK);
  192. }
  193. static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra,
  194. struct tegra_devfreq_device *dev)
  195. {
  196. u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
  197. device_writel(dev, do_percent(val, dev->config->boost_up_threshold),
  198. ACTMON_DEV_UPPER_WMARK);
  199. device_writel(dev, do_percent(val, dev->config->boost_down_threshold),
  200. ACTMON_DEV_LOWER_WMARK);
  201. }
  202. static void actmon_write_barrier(struct tegra_devfreq *tegra)
  203. {
  204. /* ensure the update has reached the ACTMON */
  205. wmb();
  206. actmon_readl(tegra, ACTMON_GLB_STATUS);
  207. }
  208. static void actmon_isr_device(struct tegra_devfreq *tegra,
  209. struct tegra_devfreq_device *dev)
  210. {
  211. unsigned long flags;
  212. u32 intr_status, dev_ctrl;
  213. spin_lock_irqsave(&dev->lock, flags);
  214. dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT);
  215. tegra_devfreq_update_avg_wmark(tegra, dev);
  216. intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS);
  217. dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL);
  218. if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) {
  219. /*
  220. * new_boost = min(old_boost * up_coef + step, max_freq)
  221. */
  222. dev->boost_freq = do_percent(dev->boost_freq,
  223. dev->config->boost_up_coeff);
  224. dev->boost_freq += ACTMON_BOOST_FREQ_STEP;
  225. dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
  226. if (dev->boost_freq >= tegra->max_freq)
  227. dev->boost_freq = tegra->max_freq;
  228. else
  229. dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
  230. } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) {
  231. /*
  232. * new_boost = old_boost * down_coef
  233. * or 0 if (old_boost * down_coef < step / 2)
  234. */
  235. dev->boost_freq = do_percent(dev->boost_freq,
  236. dev->config->boost_down_coeff);
  237. dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
  238. if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1))
  239. dev->boost_freq = 0;
  240. else
  241. dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
  242. }
  243. if (dev->config->avg_dependency_threshold) {
  244. if (dev->avg_count >= dev->config->avg_dependency_threshold)
  245. dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
  246. else if (dev->boost_freq == 0)
  247. dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
  248. }
  249. device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL);
  250. device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
  251. actmon_write_barrier(tegra);
  252. spin_unlock_irqrestore(&dev->lock, flags);
  253. }
  254. static irqreturn_t actmon_isr(int irq, void *data)
  255. {
  256. struct tegra_devfreq *tegra = data;
  257. bool handled = false;
  258. unsigned int i;
  259. u32 val;
  260. val = actmon_readl(tegra, ACTMON_GLB_STATUS);
  261. for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
  262. if (val & tegra->devices[i].config->irq_mask) {
  263. actmon_isr_device(tegra, tegra->devices + i);
  264. handled = true;
  265. }
  266. }
  267. return handled ? IRQ_WAKE_THREAD : IRQ_NONE;
  268. }
  269. static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra,
  270. unsigned long cpu_freq)
  271. {
  272. unsigned int i;
  273. struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios;
  274. for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) {
  275. if (cpu_freq >= ratio->cpu_freq) {
  276. if (ratio->emc_freq >= tegra->max_freq)
  277. return tegra->max_freq;
  278. else
  279. return ratio->emc_freq;
  280. }
  281. }
  282. return 0;
  283. }
  284. static void actmon_update_target(struct tegra_devfreq *tegra,
  285. struct tegra_devfreq_device *dev)
  286. {
  287. unsigned long cpu_freq = 0;
  288. unsigned long static_cpu_emc_freq = 0;
  289. unsigned int avg_sustain_coef;
  290. unsigned long flags;
  291. if (dev->config->avg_dependency_threshold) {
  292. cpu_freq = cpufreq_get(0);
  293. static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
  294. }
  295. spin_lock_irqsave(&dev->lock, flags);
  296. dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD;
  297. avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold;
  298. dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef);
  299. dev->target_freq += dev->boost_freq;
  300. if (dev->avg_count >= dev->config->avg_dependency_threshold)
  301. dev->target_freq = max(dev->target_freq, static_cpu_emc_freq);
  302. spin_unlock_irqrestore(&dev->lock, flags);
  303. }
  304. static irqreturn_t actmon_thread_isr(int irq, void *data)
  305. {
  306. struct tegra_devfreq *tegra = data;
  307. mutex_lock(&tegra->devfreq->lock);
  308. update_devfreq(tegra->devfreq);
  309. mutex_unlock(&tegra->devfreq->lock);
  310. return IRQ_HANDLED;
  311. }
  312. static int tegra_actmon_rate_notify_cb(struct notifier_block *nb,
  313. unsigned long action, void *ptr)
  314. {
  315. struct clk_notifier_data *data = ptr;
  316. struct tegra_devfreq *tegra;
  317. struct tegra_devfreq_device *dev;
  318. unsigned int i;
  319. unsigned long flags;
  320. if (action != POST_RATE_CHANGE)
  321. return NOTIFY_OK;
  322. tegra = container_of(nb, struct tegra_devfreq, rate_change_nb);
  323. tegra->cur_freq = data->new_rate / KHZ;
  324. for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
  325. dev = &tegra->devices[i];
  326. spin_lock_irqsave(&dev->lock, flags);
  327. tegra_devfreq_update_wmark(tegra, dev);
  328. spin_unlock_irqrestore(&dev->lock, flags);
  329. }
  330. actmon_write_barrier(tegra);
  331. return NOTIFY_OK;
  332. }
  333. static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra)
  334. {
  335. struct tegra_devfreq_device *dev;
  336. u32 val;
  337. unsigned int i;
  338. for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
  339. dev = &tegra->devices[i];
  340. val = device_readl(dev, ACTMON_DEV_CTRL);
  341. val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
  342. val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
  343. val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
  344. val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
  345. device_writel(dev, val, ACTMON_DEV_CTRL);
  346. }
  347. actmon_write_barrier(tegra);
  348. }
  349. static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra)
  350. {
  351. struct tegra_devfreq_device *dev;
  352. u32 val;
  353. unsigned int i;
  354. for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
  355. dev = &tegra->devices[i];
  356. val = device_readl(dev, ACTMON_DEV_CTRL);
  357. val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
  358. val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
  359. val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
  360. val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
  361. device_writel(dev, val, ACTMON_DEV_CTRL);
  362. }
  363. actmon_write_barrier(tegra);
  364. }
  365. static void tegra_actmon_configure_device(struct tegra_devfreq *tegra,
  366. struct tegra_devfreq_device *dev)
  367. {
  368. u32 val = 0;
  369. dev->target_freq = tegra->cur_freq;
  370. dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
  371. device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG);
  372. tegra_devfreq_update_avg_wmark(tegra, dev);
  373. tegra_devfreq_update_wmark(tegra, dev);
  374. device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT);
  375. device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
  376. val |= ACTMON_DEV_CTRL_ENB_PERIODIC;
  377. val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1)
  378. << ACTMON_DEV_CTRL_K_VAL_SHIFT;
  379. val |= (ACTMON_BELOW_WMARK_WINDOW - 1)
  380. << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT;
  381. val |= (ACTMON_ABOVE_WMARK_WINDOW - 1)
  382. << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT;
  383. val |= ACTMON_DEV_CTRL_ENB;
  384. device_writel(dev, val, ACTMON_DEV_CTRL);
  385. actmon_write_barrier(tegra);
  386. }
  387. static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
  388. u32 flags)
  389. {
  390. struct tegra_devfreq *tegra = dev_get_drvdata(dev);
  391. struct dev_pm_opp *opp;
  392. unsigned long rate = *freq * KHZ;
  393. rcu_read_lock();
  394. opp = devfreq_recommended_opp(dev, &rate, flags);
  395. if (IS_ERR(opp)) {
  396. rcu_read_unlock();
  397. dev_err(dev, "Failed to find opp for %lu KHz\n", *freq);
  398. return PTR_ERR(opp);
  399. }
  400. rate = dev_pm_opp_get_freq(opp);
  401. rcu_read_unlock();
  402. clk_set_min_rate(tegra->emc_clock, rate);
  403. clk_set_rate(tegra->emc_clock, 0);
  404. *freq = rate;
  405. return 0;
  406. }
  407. static int tegra_devfreq_get_dev_status(struct device *dev,
  408. struct devfreq_dev_status *stat)
  409. {
  410. struct tegra_devfreq *tegra = dev_get_drvdata(dev);
  411. struct tegra_devfreq_device *actmon_dev;
  412. stat->current_frequency = tegra->cur_freq;
  413. /* To be used by the tegra governor */
  414. stat->private_data = tegra;
  415. /* The below are to be used by the other governors */
  416. actmon_dev = &tegra->devices[MCALL];
  417. /* Number of cycles spent on memory access */
  418. stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT);
  419. /* The bus can be considered to be saturated way before 100% */
  420. stat->busy_time *= 100 / BUS_SATURATION_RATIO;
  421. /* Number of cycles in a sampling period */
  422. stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq;
  423. stat->busy_time = min(stat->busy_time, stat->total_time);
  424. return 0;
  425. }
  426. static struct devfreq_dev_profile tegra_devfreq_profile = {
  427. .polling_ms = 0,
  428. .target = tegra_devfreq_target,
  429. .get_dev_status = tegra_devfreq_get_dev_status,
  430. };
  431. static int tegra_governor_get_target(struct devfreq *devfreq,
  432. unsigned long *freq)
  433. {
  434. struct devfreq_dev_status *stat;
  435. struct tegra_devfreq *tegra;
  436. struct tegra_devfreq_device *dev;
  437. unsigned long target_freq = 0;
  438. unsigned int i;
  439. int err;
  440. err = devfreq_update_stats(devfreq);
  441. if (err)
  442. return err;
  443. stat = &devfreq->last_status;
  444. tegra = stat->private_data;
  445. for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
  446. dev = &tegra->devices[i];
  447. actmon_update_target(tegra, dev);
  448. target_freq = max(target_freq, dev->target_freq);
  449. }
  450. *freq = target_freq;
  451. return 0;
  452. }
  453. static int tegra_governor_event_handler(struct devfreq *devfreq,
  454. unsigned int event, void *data)
  455. {
  456. struct tegra_devfreq *tegra;
  457. int ret = 0;
  458. tegra = dev_get_drvdata(devfreq->dev.parent);
  459. switch (event) {
  460. case DEVFREQ_GOV_START:
  461. devfreq_monitor_start(devfreq);
  462. tegra_actmon_enable_interrupts(tegra);
  463. break;
  464. case DEVFREQ_GOV_STOP:
  465. tegra_actmon_disable_interrupts(tegra);
  466. devfreq_monitor_stop(devfreq);
  467. break;
  468. case DEVFREQ_GOV_SUSPEND:
  469. tegra_actmon_disable_interrupts(tegra);
  470. devfreq_monitor_suspend(devfreq);
  471. break;
  472. case DEVFREQ_GOV_RESUME:
  473. devfreq_monitor_resume(devfreq);
  474. tegra_actmon_enable_interrupts(tegra);
  475. break;
  476. }
  477. return ret;
  478. }
  479. static struct devfreq_governor tegra_devfreq_governor = {
  480. .name = "tegra_actmon",
  481. .get_target_freq = tegra_governor_get_target,
  482. .event_handler = tegra_governor_event_handler,
  483. };
  484. static int tegra_devfreq_probe(struct platform_device *pdev)
  485. {
  486. struct tegra_devfreq *tegra;
  487. struct tegra_devfreq_device *dev;
  488. struct resource *res;
  489. unsigned int i;
  490. unsigned long rate;
  491. int irq;
  492. int err;
  493. tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
  494. if (!tegra)
  495. return -ENOMEM;
  496. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  497. tegra->regs = devm_ioremap_resource(&pdev->dev, res);
  498. if (IS_ERR(tegra->regs))
  499. return PTR_ERR(tegra->regs);
  500. tegra->reset = devm_reset_control_get(&pdev->dev, "actmon");
  501. if (IS_ERR(tegra->reset)) {
  502. dev_err(&pdev->dev, "Failed to get reset\n");
  503. return PTR_ERR(tegra->reset);
  504. }
  505. tegra->clock = devm_clk_get(&pdev->dev, "actmon");
  506. if (IS_ERR(tegra->clock)) {
  507. dev_err(&pdev->dev, "Failed to get actmon clock\n");
  508. return PTR_ERR(tegra->clock);
  509. }
  510. tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
  511. if (IS_ERR(tegra->emc_clock)) {
  512. dev_err(&pdev->dev, "Failed to get emc clock\n");
  513. return PTR_ERR(tegra->emc_clock);
  514. }
  515. clk_set_rate(tegra->emc_clock, ULONG_MAX);
  516. tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb;
  517. err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb);
  518. if (err) {
  519. dev_err(&pdev->dev,
  520. "Failed to register rate change notifier\n");
  521. return err;
  522. }
  523. reset_control_assert(tegra->reset);
  524. err = clk_prepare_enable(tegra->clock);
  525. if (err) {
  526. dev_err(&pdev->dev,
  527. "Failed to prepare and enable ACTMON clock\n");
  528. return err;
  529. }
  530. reset_control_deassert(tegra->reset);
  531. tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ;
  532. tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ;
  533. actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1,
  534. ACTMON_GLB_PERIOD_CTRL);
  535. for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
  536. dev = tegra->devices + i;
  537. dev->config = actmon_device_configs + i;
  538. dev->regs = tegra->regs + dev->config->offset;
  539. spin_lock_init(&dev->lock);
  540. tegra_actmon_configure_device(tegra, dev);
  541. }
  542. for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
  543. rate = clk_round_rate(tegra->emc_clock, rate);
  544. dev_pm_opp_add(&pdev->dev, rate, 0);
  545. }
  546. irq = platform_get_irq(pdev, 0);
  547. if (irq <= 0) {
  548. dev_err(&pdev->dev, "Failed to get IRQ\n");
  549. return -ENODEV;
  550. }
  551. platform_set_drvdata(pdev, tegra);
  552. err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr,
  553. actmon_thread_isr, IRQF_SHARED,
  554. "tegra-devfreq", tegra);
  555. if (err) {
  556. dev_err(&pdev->dev, "Interrupt request failed\n");
  557. return err;
  558. }
  559. tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock);
  560. tegra->devfreq = devm_devfreq_add_device(&pdev->dev,
  561. &tegra_devfreq_profile,
  562. "tegra_actmon",
  563. NULL);
  564. return 0;
  565. }
  566. static int tegra_devfreq_remove(struct platform_device *pdev)
  567. {
  568. struct tegra_devfreq *tegra = platform_get_drvdata(pdev);
  569. int irq = platform_get_irq(pdev, 0);
  570. u32 val;
  571. unsigned int i;
  572. for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
  573. val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL);
  574. val &= ~ACTMON_DEV_CTRL_ENB;
  575. device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL);
  576. }
  577. actmon_write_barrier(tegra);
  578. devm_free_irq(&pdev->dev, irq, tegra);
  579. clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb);
  580. clk_disable_unprepare(tegra->clock);
  581. return 0;
  582. }
  583. static const struct of_device_id tegra_devfreq_of_match[] = {
  584. { .compatible = "nvidia,tegra124-actmon" },
  585. { },
  586. };
  587. MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match);
  588. static struct platform_driver tegra_devfreq_driver = {
  589. .probe = tegra_devfreq_probe,
  590. .remove = tegra_devfreq_remove,
  591. .driver = {
  592. .name = "tegra-devfreq",
  593. .of_match_table = tegra_devfreq_of_match,
  594. },
  595. };
  596. static int __init tegra_devfreq_init(void)
  597. {
  598. int ret = 0;
  599. ret = devfreq_add_governor(&tegra_devfreq_governor);
  600. if (ret) {
  601. pr_err("%s: failed to add governor: %d\n", __func__, ret);
  602. return ret;
  603. }
  604. ret = platform_driver_register(&tegra_devfreq_driver);
  605. if (ret)
  606. devfreq_remove_governor(&tegra_devfreq_governor);
  607. return ret;
  608. }
  609. module_init(tegra_devfreq_init)
  610. static void __exit tegra_devfreq_exit(void)
  611. {
  612. int ret = 0;
  613. platform_driver_unregister(&tegra_devfreq_driver);
  614. ret = devfreq_remove_governor(&tegra_devfreq_governor);
  615. if (ret)
  616. pr_err("%s: failed to remove governor: %d\n", __func__, ret);
  617. }
  618. module_exit(tegra_devfreq_exit)
  619. MODULE_LICENSE("GPL v2");
  620. MODULE_DESCRIPTION("Tegra devfreq driver");
  621. MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>");