cpu.c 10.0 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/init.h>
  9. #include <linux/device.h>
  10. #include <linux/seq_file.h>
  11. #include <linux/cpu.h>
  12. #include <linux/module.h>
  13. #include <linux/percpu.h>
  14. #include <linux/param.h>
  15. #include <linux/errno.h>
  16. #include <linux/clk.h>
  17. #include <asm/setup.h>
  18. #include <asm/sysreg.h>
  19. static DEFINE_PER_CPU(struct cpu, cpu_devices);
  20. #ifdef CONFIG_PERFORMANCE_COUNTERS
  21. /*
  22. * XXX: If/when a SMP-capable implementation of AVR32 will ever be
  23. * made, we must make sure that the code executes on the correct CPU.
  24. */
  25. static ssize_t show_pc0event(struct device *dev,
  26. struct device_attribute *attr, char *buf)
  27. {
  28. unsigned long pccr;
  29. pccr = sysreg_read(PCCR);
  30. return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
  31. }
  32. static ssize_t store_pc0event(struct device *dev,
  33. struct device_attribute *attr, const char *buf,
  34. size_t count)
  35. {
  36. unsigned long val;
  37. int ret;
  38. ret = kstrtoul(buf, 0, &val);
  39. if (ret)
  40. return ret;
  41. if (val > 0x3f)
  42. return -EINVAL;
  43. val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff);
  44. sysreg_write(PCCR, val);
  45. return count;
  46. }
  47. static ssize_t show_pc0count(struct device *dev,
  48. struct device_attribute *attr, char *buf)
  49. {
  50. unsigned long pcnt0;
  51. pcnt0 = sysreg_read(PCNT0);
  52. return sprintf(buf, "%lu\n", pcnt0);
  53. }
  54. static ssize_t store_pc0count(struct device *dev,
  55. struct device_attribute *attr,
  56. const char *buf, size_t count)
  57. {
  58. unsigned long val;
  59. int ret;
  60. ret = kstrtoul(buf, 0, &val);
  61. if (ret)
  62. return ret;
  63. sysreg_write(PCNT0, val);
  64. return count;
  65. }
  66. static ssize_t show_pc1event(struct device *dev,
  67. struct device_attribute *attr, char *buf)
  68. {
  69. unsigned long pccr;
  70. pccr = sysreg_read(PCCR);
  71. return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
  72. }
  73. static ssize_t store_pc1event(struct device *dev,
  74. struct device_attribute *attr, const char *buf,
  75. size_t count)
  76. {
  77. unsigned long val;
  78. int ret;
  79. ret = kstrtoul(buf, 0, &val);
  80. if (ret)
  81. return ret;
  82. if (val > 0x3f)
  83. return -EINVAL;
  84. val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff);
  85. sysreg_write(PCCR, val);
  86. return count;
  87. }
  88. static ssize_t show_pc1count(struct device *dev,
  89. struct device_attribute *attr, char *buf)
  90. {
  91. unsigned long pcnt1;
  92. pcnt1 = sysreg_read(PCNT1);
  93. return sprintf(buf, "%lu\n", pcnt1);
  94. }
  95. static ssize_t store_pc1count(struct device *dev,
  96. struct device_attribute *attr, const char *buf,
  97. size_t count)
  98. {
  99. unsigned long val;
  100. int ret;
  101. ret = kstrtoul(buf, 0, &val);
  102. if (ret)
  103. return ret;
  104. sysreg_write(PCNT1, val);
  105. return count;
  106. }
  107. static ssize_t show_pccycles(struct device *dev,
  108. struct device_attribute *attr, char *buf)
  109. {
  110. unsigned long pccnt;
  111. pccnt = sysreg_read(PCCNT);
  112. return sprintf(buf, "%lu\n", pccnt);
  113. }
  114. static ssize_t store_pccycles(struct device *dev,
  115. struct device_attribute *attr, const char *buf,
  116. size_t count)
  117. {
  118. unsigned long val;
  119. int ret;
  120. ret = kstrtoul(buf, 0, &val);
  121. if (ret)
  122. return ret;
  123. sysreg_write(PCCNT, val);
  124. return count;
  125. }
  126. static ssize_t show_pcenable(struct device *dev,
  127. struct device_attribute *attr, char *buf)
  128. {
  129. unsigned long pccr;
  130. pccr = sysreg_read(PCCR);
  131. return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
  132. }
  133. static ssize_t store_pcenable(struct device *dev,
  134. struct device_attribute *attr, const char *buf,
  135. size_t count)
  136. {
  137. unsigned long pccr, val;
  138. int ret;
  139. ret = kstrtoul(buf, 0, &val);
  140. if (ret)
  141. return ret;
  142. if (val)
  143. val = 1;
  144. pccr = sysreg_read(PCCR);
  145. pccr = (pccr & ~1UL) | val;
  146. sysreg_write(PCCR, pccr);
  147. return count;
  148. }
  149. static DEVICE_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
  150. static DEVICE_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
  151. static DEVICE_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
  152. static DEVICE_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
  153. static DEVICE_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
  154. static DEVICE_ATTR(pcenable, 0600, show_pcenable, store_pcenable);
  155. #endif /* CONFIG_PERFORMANCE_COUNTERS */
  156. static int __init topology_init(void)
  157. {
  158. int cpu;
  159. for_each_possible_cpu(cpu) {
  160. struct cpu *c = &per_cpu(cpu_devices, cpu);
  161. register_cpu(c, cpu);
  162. #ifdef CONFIG_PERFORMANCE_COUNTERS
  163. device_create_file(&c->dev, &dev_attr_pc0event);
  164. device_create_file(&c->dev, &dev_attr_pc0count);
  165. device_create_file(&c->dev, &dev_attr_pc1event);
  166. device_create_file(&c->dev, &dev_attr_pc1count);
  167. device_create_file(&c->dev, &dev_attr_pccycles);
  168. device_create_file(&c->dev, &dev_attr_pcenable);
  169. #endif
  170. }
  171. return 0;
  172. }
  173. subsys_initcall(topology_init);
  174. struct chip_id_map {
  175. u16 mid;
  176. u16 pn;
  177. const char *name;
  178. };
  179. static const struct chip_id_map chip_names[] = {
  180. { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
  181. };
  182. #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
  183. static const char *cpu_names[] = {
  184. "Morgan",
  185. "AP7",
  186. };
  187. #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
  188. static const char *arch_names[] = {
  189. "AVR32A",
  190. "AVR32B",
  191. };
  192. #define NR_ARCH_NAMES ARRAY_SIZE(arch_names)
  193. static const char *mmu_types[] = {
  194. "No MMU",
  195. "ITLB and DTLB",
  196. "Shared TLB",
  197. "MPU"
  198. };
  199. static const char *cpu_feature_flags[] = {
  200. "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
  201. };
  202. static const char *get_chip_name(struct avr32_cpuinfo *cpu)
  203. {
  204. unsigned int i;
  205. unsigned int mid = avr32_get_manufacturer_id(cpu);
  206. unsigned int pn = avr32_get_product_number(cpu);
  207. for (i = 0; i < NR_CHIP_NAMES; i++) {
  208. if (chip_names[i].mid == mid && chip_names[i].pn == pn)
  209. return chip_names[i].name;
  210. }
  211. return "(unknown)";
  212. }
  213. void __init setup_processor(void)
  214. {
  215. unsigned long config0, config1;
  216. unsigned long features;
  217. unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
  218. unsigned device_id;
  219. unsigned tmp;
  220. unsigned i;
  221. config0 = sysreg_read(CONFIG0);
  222. config1 = sysreg_read(CONFIG1);
  223. cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
  224. cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
  225. arch_id = SYSREG_BFEXT(AT, config0);
  226. arch_rev = SYSREG_BFEXT(AR, config0);
  227. mmu_type = SYSREG_BFEXT(MMUT, config0);
  228. device_id = ocd_read(DID);
  229. boot_cpu_data.arch_type = arch_id;
  230. boot_cpu_data.cpu_type = cpu_id;
  231. boot_cpu_data.arch_revision = arch_rev;
  232. boot_cpu_data.cpu_revision = cpu_rev;
  233. boot_cpu_data.tlb_config = mmu_type;
  234. boot_cpu_data.device_id = device_id;
  235. tmp = SYSREG_BFEXT(ILSZ, config1);
  236. if (tmp) {
  237. boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
  238. boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
  239. boot_cpu_data.icache.linesz = 1 << (tmp + 1);
  240. }
  241. tmp = SYSREG_BFEXT(DLSZ, config1);
  242. if (tmp) {
  243. boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
  244. boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
  245. boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
  246. }
  247. if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) {
  248. printk ("Unknown CPU configuration (ID %02x, arch %02x), "
  249. "continuing anyway...\n",
  250. cpu_id, arch_id);
  251. return;
  252. }
  253. printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
  254. avr32_get_chip_revision(&boot_cpu_data) + 'A');
  255. printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
  256. cpu_names[cpu_id], cpu_id, cpu_rev,
  257. arch_names[arch_id], arch_rev);
  258. printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
  259. printk ("CPU: features:");
  260. features = 0;
  261. if (config0 & SYSREG_BIT(CONFIG0_R))
  262. features |= AVR32_FEATURE_RMW;
  263. if (config0 & SYSREG_BIT(CONFIG0_D))
  264. features |= AVR32_FEATURE_DSP;
  265. if (config0 & SYSREG_BIT(CONFIG0_S))
  266. features |= AVR32_FEATURE_SIMD;
  267. if (config0 & SYSREG_BIT(CONFIG0_O))
  268. features |= AVR32_FEATURE_OCD;
  269. if (config0 & SYSREG_BIT(CONFIG0_P))
  270. features |= AVR32_FEATURE_PCTR;
  271. if (config0 & SYSREG_BIT(CONFIG0_J))
  272. features |= AVR32_FEATURE_JAVA;
  273. if (config0 & SYSREG_BIT(CONFIG0_F))
  274. features |= AVR32_FEATURE_FPU;
  275. for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
  276. if (features & (1 << i))
  277. printk(" %s", cpu_feature_flags[i]);
  278. printk("\n");
  279. boot_cpu_data.features = features;
  280. }
  281. #ifdef CONFIG_PROC_FS
  282. static int c_show(struct seq_file *m, void *v)
  283. {
  284. unsigned int icache_size, dcache_size;
  285. unsigned int cpu = smp_processor_id();
  286. unsigned int freq;
  287. unsigned int i;
  288. icache_size = boot_cpu_data.icache.ways *
  289. boot_cpu_data.icache.sets *
  290. boot_cpu_data.icache.linesz;
  291. dcache_size = boot_cpu_data.dcache.ways *
  292. boot_cpu_data.dcache.sets *
  293. boot_cpu_data.dcache.linesz;
  294. seq_printf(m, "processor\t: %d\n", cpu);
  295. seq_printf(m, "chip type\t: %s revision %c\n",
  296. get_chip_name(&boot_cpu_data),
  297. avr32_get_chip_revision(&boot_cpu_data) + 'A');
  298. if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
  299. seq_printf(m, "cpu arch\t: %s revision %d\n",
  300. arch_names[boot_cpu_data.arch_type],
  301. boot_cpu_data.arch_revision);
  302. if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
  303. seq_printf(m, "cpu core\t: %s revision %d\n",
  304. cpu_names[boot_cpu_data.cpu_type],
  305. boot_cpu_data.cpu_revision);
  306. freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
  307. seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
  308. seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
  309. icache_size >> 10,
  310. boot_cpu_data.icache.ways,
  311. boot_cpu_data.icache.sets,
  312. boot_cpu_data.icache.linesz);
  313. seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
  314. dcache_size >> 10,
  315. boot_cpu_data.dcache.ways,
  316. boot_cpu_data.dcache.sets,
  317. boot_cpu_data.dcache.linesz);
  318. seq_printf(m, "features\t:");
  319. for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
  320. if (boot_cpu_data.features & (1 << i))
  321. seq_printf(m, " %s", cpu_feature_flags[i]);
  322. seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
  323. boot_cpu_data.loops_per_jiffy / (500000/HZ),
  324. (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
  325. return 0;
  326. }
  327. static void *c_start(struct seq_file *m, loff_t *pos)
  328. {
  329. return *pos < 1 ? (void *)1 : NULL;
  330. }
  331. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  332. {
  333. ++*pos;
  334. return NULL;
  335. }
  336. static void c_stop(struct seq_file *m, void *v)
  337. {
  338. }
  339. const struct seq_operations cpuinfo_op = {
  340. .start = c_start,
  341. .next = c_next,
  342. .stop = c_stop,
  343. .show = c_show
  344. };
  345. #endif /* CONFIG_PROC_FS */