sleep-s3c2412.S 1.8 KB

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  1. /* linux/arch/arm/mach-s3c2412/sleep.S
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2412 Power Manager low-level sleep support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/linkage.h>
  23. #include <asm/assembler.h>
  24. #include <mach/hardware.h>
  25. #include <mach/map.h>
  26. #include <mach/regs-irq.h>
  27. .text
  28. .global s3c2412_sleep_enter
  29. s3c2412_sleep_enter:
  30. mov r0, #0 /* argument for coprocessors */
  31. ldr r1, =S3C2410_INTPND
  32. ldr r2, =S3C2410_SRCPND
  33. ldr r3, =S3C2410_EINTPEND
  34. teq r0, r0
  35. bl s3c2412_sleep_enter1
  36. teq pc, r0
  37. bl s3c2412_sleep_enter1
  38. .align 5
  39. /* this is called twice, first with the Z flag to ensure that the
  40. * instructions have been loaded into the cache, and the second
  41. * time to try and suspend the system.
  42. */
  43. s3c2412_sleep_enter1:
  44. mcr p15, 0, r0, c7, c10, 4
  45. mcrne p15, 0, r0, c7, c0, 4
  46. /* if we return from here, it is because an interrupt was
  47. * active when we tried to shutdown. Try and ack the IRQ and
  48. * retry, as simply returning causes the system to lock.
  49. */
  50. ldrne r9, [r1]
  51. strne r9, [r1]
  52. ldrne r9, [r2]
  53. strne r9, [r2]
  54. ldrne r9, [r3]
  55. strne r9, [r3]
  56. bne s3c2412_sleep_enter1
  57. ret lr