sys_sable.c 17 KB

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  1. /*
  2. * linux/arch/alpha/kernel/sys_sable.c
  3. *
  4. * Copyright (C) 1995 David A Rusling
  5. * Copyright (C) 1996 Jay A Estabrook
  6. * Copyright (C) 1998, 1999 Richard Henderson
  7. *
  8. * Code supporting the Sable, Sable-Gamma, and Lynx systems.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/types.h>
  12. #include <linux/mm.h>
  13. #include <linux/sched.h>
  14. #include <linux/pci.h>
  15. #include <linux/init.h>
  16. #include <asm/ptrace.h>
  17. #include <asm/dma.h>
  18. #include <asm/irq.h>
  19. #include <asm/mmu_context.h>
  20. #include <asm/io.h>
  21. #include <asm/pgtable.h>
  22. #include <asm/core_t2.h>
  23. #include <asm/tlbflush.h>
  24. #include "proto.h"
  25. #include "irq_impl.h"
  26. #include "pci_impl.h"
  27. #include "machvec_impl.h"
  28. DEFINE_SPINLOCK(sable_lynx_irq_lock);
  29. typedef struct irq_swizzle_struct
  30. {
  31. char irq_to_mask[64];
  32. char mask_to_irq[64];
  33. /* Note mask bit is true for DISABLED irqs. */
  34. unsigned long shadow_mask;
  35. void (*update_irq_hw)(unsigned long bit, unsigned long mask);
  36. void (*ack_irq_hw)(unsigned long bit);
  37. } irq_swizzle_t;
  38. static irq_swizzle_t *sable_lynx_irq_swizzle;
  39. static void sable_lynx_init_irq(int nr_of_irqs);
  40. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
  41. /***********************************************************************/
  42. /*
  43. * For SABLE, which is really baroque, we manage 40 IRQ's, but the
  44. * hardware really only supports 24, not via normal ISA PIC,
  45. * but cascaded custom 8259's, etc.
  46. * 0-7 (char at 536)
  47. * 8-15 (char at 53a)
  48. * 16-23 (char at 53c)
  49. *
  50. * Summary Registers (536/53a/53c):
  51. *
  52. * Bit Meaning Kernel IRQ
  53. *------------------------------------------
  54. * 0 PCI slot 0 34
  55. * 1 NCR810 (builtin) 33
  56. * 2 TULIP (builtin) 32
  57. * 3 mouse 12
  58. * 4 PCI slot 1 35
  59. * 5 PCI slot 2 36
  60. * 6 keyboard 1
  61. * 7 floppy 6
  62. * 8 COM2 3
  63. * 9 parallel port 7
  64. *10 EISA irq 3 -
  65. *11 EISA irq 4 -
  66. *12 EISA irq 5 5
  67. *13 EISA irq 6 -
  68. *14 EISA irq 7 -
  69. *15 COM1 4
  70. *16 EISA irq 9 9
  71. *17 EISA irq 10 10
  72. *18 EISA irq 11 11
  73. *19 EISA irq 12 -
  74. *20 EISA irq 13 -
  75. *21 EISA irq 14 14
  76. *22 NC 15
  77. *23 IIC -
  78. */
  79. static void
  80. sable_update_irq_hw(unsigned long bit, unsigned long mask)
  81. {
  82. int port = 0x537;
  83. if (bit >= 16) {
  84. port = 0x53d;
  85. mask >>= 16;
  86. } else if (bit >= 8) {
  87. port = 0x53b;
  88. mask >>= 8;
  89. }
  90. outb(mask, port);
  91. }
  92. static void
  93. sable_ack_irq_hw(unsigned long bit)
  94. {
  95. int port, val1, val2;
  96. if (bit >= 16) {
  97. port = 0x53c;
  98. val1 = 0xE0 | (bit - 16);
  99. val2 = 0xE0 | 4;
  100. } else if (bit >= 8) {
  101. port = 0x53a;
  102. val1 = 0xE0 | (bit - 8);
  103. val2 = 0xE0 | 3;
  104. } else {
  105. port = 0x536;
  106. val1 = 0xE0 | (bit - 0);
  107. val2 = 0xE0 | 1;
  108. }
  109. outb(val1, port); /* ack the slave */
  110. outb(val2, 0x534); /* ack the master */
  111. }
  112. static irq_swizzle_t sable_irq_swizzle = {
  113. {
  114. -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
  115. -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
  116. -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 0-7 */
  117. -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 8-15 */
  118. 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
  119. -1, -1, -1, -1, -1, -1, -1, -1, /* */
  120. -1, -1, -1, -1, -1, -1, -1, -1, /* */
  121. -1, -1, -1, -1, -1, -1, -1, -1 /* */
  122. },
  123. {
  124. 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
  125. 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
  126. 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
  127. -1, -1, -1, -1, -1, -1, -1, -1, /* */
  128. -1, -1, -1, -1, -1, -1, -1, -1, /* */
  129. -1, -1, -1, -1, -1, -1, -1, -1, /* */
  130. -1, -1, -1, -1, -1, -1, -1, -1, /* */
  131. -1, -1, -1, -1, -1, -1, -1, -1 /* */
  132. },
  133. -1,
  134. sable_update_irq_hw,
  135. sable_ack_irq_hw
  136. };
  137. static void __init
  138. sable_init_irq(void)
  139. {
  140. outb(-1, 0x537); /* slave 0 */
  141. outb(-1, 0x53b); /* slave 1 */
  142. outb(-1, 0x53d); /* slave 2 */
  143. outb(0x44, 0x535); /* enable cascades in master */
  144. sable_lynx_irq_swizzle = &sable_irq_swizzle;
  145. sable_lynx_init_irq(40);
  146. }
  147. /*
  148. * PCI Fixup configuration for ALPHA SABLE (2100).
  149. *
  150. * The device to slot mapping looks like:
  151. *
  152. * Slot Device
  153. * 0 TULIP
  154. * 1 SCSI
  155. * 2 PCI-EISA bridge
  156. * 3 none
  157. * 4 none
  158. * 5 none
  159. * 6 PCI on board slot 0
  160. * 7 PCI on board slot 1
  161. * 8 PCI on board slot 2
  162. *
  163. *
  164. * This two layered interrupt approach means that we allocate IRQ 16 and
  165. * above for PCI interrupts. The IRQ relates to which bit the interrupt
  166. * comes in on. This makes interrupt processing much easier.
  167. */
  168. /*
  169. * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
  170. * with the values in the irq swizzling tables above.
  171. */
  172. static int __init
  173. sable_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  174. {
  175. static char irq_tab[9][5] __initdata = {
  176. /*INT INTA INTB INTC INTD */
  177. { 32+0, 32+0, 32+0, 32+0, 32+0}, /* IdSel 0, TULIP */
  178. { 32+1, 32+1, 32+1, 32+1, 32+1}, /* IdSel 1, SCSI */
  179. { -1, -1, -1, -1, -1}, /* IdSel 2, SIO */
  180. { -1, -1, -1, -1, -1}, /* IdSel 3, none */
  181. { -1, -1, -1, -1, -1}, /* IdSel 4, none */
  182. { -1, -1, -1, -1, -1}, /* IdSel 5, none */
  183. { 32+2, 32+2, 32+2, 32+2, 32+2}, /* IdSel 6, slot 0 */
  184. { 32+3, 32+3, 32+3, 32+3, 32+3}, /* IdSel 7, slot 1 */
  185. { 32+4, 32+4, 32+4, 32+4, 32+4} /* IdSel 8, slot 2 */
  186. };
  187. long min_idsel = 0, max_idsel = 8, irqs_per_slot = 5;
  188. return COMMON_TABLE_LOOKUP;
  189. }
  190. #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */
  191. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
  192. /***********************************************************************/
  193. /* LYNX hardware specifics
  194. */
  195. /*
  196. * For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC.
  197. *
  198. * Bit Meaning Kernel IRQ
  199. *------------------------------------------
  200. * 0
  201. * 1
  202. * 2
  203. * 3 mouse 12
  204. * 4
  205. * 5
  206. * 6 keyboard 1
  207. * 7 floppy 6
  208. * 8 COM2 3
  209. * 9 parallel port 7
  210. *10 EISA irq 3 -
  211. *11 EISA irq 4 -
  212. *12 EISA irq 5 5
  213. *13 EISA irq 6 -
  214. *14 EISA irq 7 -
  215. *15 COM1 4
  216. *16 EISA irq 9 9
  217. *17 EISA irq 10 10
  218. *18 EISA irq 11 11
  219. *19 EISA irq 12 -
  220. *20
  221. *21 EISA irq 14 14
  222. *22 EISA irq 15 15
  223. *23 IIC -
  224. *24 VGA (builtin) -
  225. *25
  226. *26
  227. *27
  228. *28 NCR810 (builtin) 28
  229. *29
  230. *30
  231. *31
  232. *32 PCI 0 slot 4 A primary bus 32
  233. *33 PCI 0 slot 4 B primary bus 33
  234. *34 PCI 0 slot 4 C primary bus 34
  235. *35 PCI 0 slot 4 D primary bus
  236. *36 PCI 0 slot 5 A primary bus
  237. *37 PCI 0 slot 5 B primary bus
  238. *38 PCI 0 slot 5 C primary bus
  239. *39 PCI 0 slot 5 D primary bus
  240. *40 PCI 0 slot 6 A primary bus
  241. *41 PCI 0 slot 6 B primary bus
  242. *42 PCI 0 slot 6 C primary bus
  243. *43 PCI 0 slot 6 D primary bus
  244. *44 PCI 0 slot 7 A primary bus
  245. *45 PCI 0 slot 7 B primary bus
  246. *46 PCI 0 slot 7 C primary bus
  247. *47 PCI 0 slot 7 D primary bus
  248. *48 PCI 0 slot 0 A secondary bus
  249. *49 PCI 0 slot 0 B secondary bus
  250. *50 PCI 0 slot 0 C secondary bus
  251. *51 PCI 0 slot 0 D secondary bus
  252. *52 PCI 0 slot 1 A secondary bus
  253. *53 PCI 0 slot 1 B secondary bus
  254. *54 PCI 0 slot 1 C secondary bus
  255. *55 PCI 0 slot 1 D secondary bus
  256. *56 PCI 0 slot 2 A secondary bus
  257. *57 PCI 0 slot 2 B secondary bus
  258. *58 PCI 0 slot 2 C secondary bus
  259. *59 PCI 0 slot 2 D secondary bus
  260. *60 PCI 0 slot 3 A secondary bus
  261. *61 PCI 0 slot 3 B secondary bus
  262. *62 PCI 0 slot 3 C secondary bus
  263. *63 PCI 0 slot 3 D secondary bus
  264. */
  265. static void
  266. lynx_update_irq_hw(unsigned long bit, unsigned long mask)
  267. {
  268. /*
  269. * Write the AIR register on the T3/T4 with the
  270. * address of the IC mask register (offset 0x40)
  271. */
  272. *(vulp)T2_AIR = 0x40;
  273. mb();
  274. *(vulp)T2_AIR; /* re-read to force write */
  275. mb();
  276. *(vulp)T2_DIR = mask;
  277. mb();
  278. mb();
  279. }
  280. static void
  281. lynx_ack_irq_hw(unsigned long bit)
  282. {
  283. *(vulp)T2_VAR = (u_long) bit;
  284. mb();
  285. mb();
  286. }
  287. static irq_swizzle_t lynx_irq_swizzle = {
  288. { /* irq_to_mask */
  289. -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
  290. -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
  291. -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo */
  292. -1, -1, -1, -1, 28, -1, -1, -1, /* pseudo */
  293. 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
  294. 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
  295. 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
  296. 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
  297. },
  298. { /* mask_to_irq */
  299. -1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */
  300. 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
  301. 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
  302. -1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */
  303. 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
  304. 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
  305. 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
  306. 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
  307. },
  308. -1,
  309. lynx_update_irq_hw,
  310. lynx_ack_irq_hw
  311. };
  312. static void __init
  313. lynx_init_irq(void)
  314. {
  315. sable_lynx_irq_swizzle = &lynx_irq_swizzle;
  316. sable_lynx_init_irq(64);
  317. }
  318. /*
  319. * PCI Fixup configuration for ALPHA LYNX (2100A)
  320. *
  321. * The device to slot mapping looks like:
  322. *
  323. * Slot Device
  324. * 0 none
  325. * 1 none
  326. * 2 PCI-EISA bridge
  327. * 3 PCI-PCI bridge
  328. * 4 NCR 810 (Demi-Lynx only)
  329. * 5 none
  330. * 6 PCI on board slot 4
  331. * 7 PCI on board slot 5
  332. * 8 PCI on board slot 6
  333. * 9 PCI on board slot 7
  334. *
  335. * And behind the PPB we have:
  336. *
  337. * 11 PCI on board slot 0
  338. * 12 PCI on board slot 1
  339. * 13 PCI on board slot 2
  340. * 14 PCI on board slot 3
  341. */
  342. /*
  343. * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
  344. * with the values in the irq swizzling tables above.
  345. */
  346. static int __init
  347. lynx_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  348. {
  349. static char irq_tab[19][5] __initdata = {
  350. /*INT INTA INTB INTC INTD */
  351. { -1, -1, -1, -1, -1}, /* IdSel 13, PCEB */
  352. { -1, -1, -1, -1, -1}, /* IdSel 14, PPB */
  353. { 28, 28, 28, 28, 28}, /* IdSel 15, NCR demi */
  354. { -1, -1, -1, -1, -1}, /* IdSel 16, none */
  355. { 32, 32, 33, 34, 35}, /* IdSel 17, slot 4 */
  356. { 36, 36, 37, 38, 39}, /* IdSel 18, slot 5 */
  357. { 40, 40, 41, 42, 43}, /* IdSel 19, slot 6 */
  358. { 44, 44, 45, 46, 47}, /* IdSel 20, slot 7 */
  359. { -1, -1, -1, -1, -1}, /* IdSel 22, none */
  360. /* The following are actually behind the PPB. */
  361. { -1, -1, -1, -1, -1}, /* IdSel 16 none */
  362. { 28, 28, 28, 28, 28}, /* IdSel 17 NCR lynx */
  363. { -1, -1, -1, -1, -1}, /* IdSel 18 none */
  364. { -1, -1, -1, -1, -1}, /* IdSel 19 none */
  365. { -1, -1, -1, -1, -1}, /* IdSel 20 none */
  366. { -1, -1, -1, -1, -1}, /* IdSel 21 none */
  367. { 48, 48, 49, 50, 51}, /* IdSel 22 slot 0 */
  368. { 52, 52, 53, 54, 55}, /* IdSel 23 slot 1 */
  369. { 56, 56, 57, 58, 59}, /* IdSel 24 slot 2 */
  370. { 60, 60, 61, 62, 63} /* IdSel 25 slot 3 */
  371. };
  372. const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5;
  373. return COMMON_TABLE_LOOKUP;
  374. }
  375. static u8 __init
  376. lynx_swizzle(struct pci_dev *dev, u8 *pinp)
  377. {
  378. int slot, pin = *pinp;
  379. if (dev->bus->number == 0) {
  380. slot = PCI_SLOT(dev->devfn);
  381. }
  382. /* Check for the built-in bridge */
  383. else if (PCI_SLOT(dev->bus->self->devfn) == 3) {
  384. slot = PCI_SLOT(dev->devfn) + 11;
  385. }
  386. else
  387. {
  388. /* Must be a card-based bridge. */
  389. do {
  390. if (PCI_SLOT(dev->bus->self->devfn) == 3) {
  391. slot = PCI_SLOT(dev->devfn) + 11;
  392. break;
  393. }
  394. pin = pci_swizzle_interrupt_pin(dev, pin);
  395. /* Move up the chain of bridges. */
  396. dev = dev->bus->self;
  397. /* Slot of the next bridge. */
  398. slot = PCI_SLOT(dev->devfn);
  399. } while (dev->bus->self);
  400. }
  401. *pinp = pin;
  402. return slot;
  403. }
  404. #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */
  405. /***********************************************************************/
  406. /* GENERIC irq routines */
  407. static inline void
  408. sable_lynx_enable_irq(struct irq_data *d)
  409. {
  410. unsigned long bit, mask;
  411. bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
  412. spin_lock(&sable_lynx_irq_lock);
  413. mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
  414. sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
  415. spin_unlock(&sable_lynx_irq_lock);
  416. #if 0
  417. printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
  418. __func__, mask, bit, irq);
  419. #endif
  420. }
  421. static void
  422. sable_lynx_disable_irq(struct irq_data *d)
  423. {
  424. unsigned long bit, mask;
  425. bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
  426. spin_lock(&sable_lynx_irq_lock);
  427. mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
  428. sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
  429. spin_unlock(&sable_lynx_irq_lock);
  430. #if 0
  431. printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
  432. __func__, mask, bit, irq);
  433. #endif
  434. }
  435. static void
  436. sable_lynx_mask_and_ack_irq(struct irq_data *d)
  437. {
  438. unsigned long bit, mask;
  439. bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
  440. spin_lock(&sable_lynx_irq_lock);
  441. mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
  442. sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
  443. sable_lynx_irq_swizzle->ack_irq_hw(bit);
  444. spin_unlock(&sable_lynx_irq_lock);
  445. }
  446. static struct irq_chip sable_lynx_irq_type = {
  447. .name = "SABLE/LYNX",
  448. .irq_unmask = sable_lynx_enable_irq,
  449. .irq_mask = sable_lynx_disable_irq,
  450. .irq_mask_ack = sable_lynx_mask_and_ack_irq,
  451. };
  452. static void
  453. sable_lynx_srm_device_interrupt(unsigned long vector)
  454. {
  455. /* Note that the vector reported by the SRM PALcode corresponds
  456. to the interrupt mask bits, but we have to manage via the
  457. so-called legacy IRQs for many common devices. */
  458. int bit, irq;
  459. bit = (vector - 0x800) >> 4;
  460. irq = sable_lynx_irq_swizzle->mask_to_irq[bit];
  461. #if 0
  462. printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",
  463. __func__, vector, bit, irq);
  464. #endif
  465. handle_irq(irq);
  466. }
  467. static void __init
  468. sable_lynx_init_irq(int nr_of_irqs)
  469. {
  470. long i;
  471. for (i = 0; i < nr_of_irqs; ++i) {
  472. irq_set_chip_and_handler(i, &sable_lynx_irq_type,
  473. handle_level_irq);
  474. irq_set_status_flags(i, IRQ_LEVEL);
  475. }
  476. common_init_isa_dma();
  477. }
  478. static void __init
  479. sable_lynx_init_pci(void)
  480. {
  481. common_init_pci();
  482. }
  483. /*****************************************************************/
  484. /*
  485. * The System Vectors
  486. *
  487. * In order that T2_HAE_ADDRESS should be a constant, we play
  488. * these games with GAMMA_BIAS.
  489. */
  490. #if defined(CONFIG_ALPHA_GENERIC) || \
  491. (defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA))
  492. #undef GAMMA_BIAS
  493. #define GAMMA_BIAS 0
  494. struct alpha_machine_vector sable_mv __initmv = {
  495. .vector_name = "Sable",
  496. DO_EV4_MMU,
  497. DO_DEFAULT_RTC,
  498. DO_T2_IO,
  499. .machine_check = t2_machine_check,
  500. .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
  501. .min_io_address = EISA_DEFAULT_IO_BASE,
  502. .min_mem_address = T2_DEFAULT_MEM_BASE,
  503. .nr_irqs = 40,
  504. .device_interrupt = sable_lynx_srm_device_interrupt,
  505. .init_arch = t2_init_arch,
  506. .init_irq = sable_init_irq,
  507. .init_rtc = common_init_rtc,
  508. .init_pci = sable_lynx_init_pci,
  509. .kill_arch = t2_kill_arch,
  510. .pci_map_irq = sable_map_irq,
  511. .pci_swizzle = common_swizzle,
  512. .sys = { .t2 = {
  513. .gamma_bias = 0
  514. } }
  515. };
  516. ALIAS_MV(sable)
  517. #endif /* GENERIC || (SABLE && !GAMMA) */
  518. #if defined(CONFIG_ALPHA_GENERIC) || \
  519. (defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA))
  520. #undef GAMMA_BIAS
  521. #define GAMMA_BIAS _GAMMA_BIAS
  522. struct alpha_machine_vector sable_gamma_mv __initmv = {
  523. .vector_name = "Sable-Gamma",
  524. DO_EV5_MMU,
  525. DO_DEFAULT_RTC,
  526. DO_T2_IO,
  527. .machine_check = t2_machine_check,
  528. .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
  529. .min_io_address = EISA_DEFAULT_IO_BASE,
  530. .min_mem_address = T2_DEFAULT_MEM_BASE,
  531. .nr_irqs = 40,
  532. .device_interrupt = sable_lynx_srm_device_interrupt,
  533. .init_arch = t2_init_arch,
  534. .init_irq = sable_init_irq,
  535. .init_rtc = common_init_rtc,
  536. .init_pci = sable_lynx_init_pci,
  537. .kill_arch = t2_kill_arch,
  538. .pci_map_irq = sable_map_irq,
  539. .pci_swizzle = common_swizzle,
  540. .sys = { .t2 = {
  541. .gamma_bias = _GAMMA_BIAS
  542. } }
  543. };
  544. ALIAS_MV(sable_gamma)
  545. #endif /* GENERIC || (SABLE && GAMMA) */
  546. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
  547. #undef GAMMA_BIAS
  548. #define GAMMA_BIAS _GAMMA_BIAS
  549. struct alpha_machine_vector lynx_mv __initmv = {
  550. .vector_name = "Lynx",
  551. DO_EV4_MMU,
  552. DO_DEFAULT_RTC,
  553. DO_T2_IO,
  554. .machine_check = t2_machine_check,
  555. .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
  556. .min_io_address = EISA_DEFAULT_IO_BASE,
  557. .min_mem_address = T2_DEFAULT_MEM_BASE,
  558. .nr_irqs = 64,
  559. .device_interrupt = sable_lynx_srm_device_interrupt,
  560. .init_arch = t2_init_arch,
  561. .init_irq = lynx_init_irq,
  562. .init_rtc = common_init_rtc,
  563. .init_pci = sable_lynx_init_pci,
  564. .kill_arch = t2_kill_arch,
  565. .pci_map_irq = lynx_map_irq,
  566. .pci_swizzle = lynx_swizzle,
  567. .sys = { .t2 = {
  568. .gamma_bias = _GAMMA_BIAS
  569. } }
  570. };
  571. ALIAS_MV(lynx)
  572. #endif /* GENERIC || LYNX */