tw9910.c 24 KB

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  1. /*
  2. * tw9910 Video Driver
  3. *
  4. * Copyright (C) 2008 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ov772x driver,
  8. *
  9. * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  10. * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  11. * Copyright (C) 2008 Magnus Damm
  12. * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/i2c.h>
  21. #include <linux/slab.h>
  22. #include <linux/kernel.h>
  23. #include <linux/delay.h>
  24. #include <linux/v4l2-mediabus.h>
  25. #include <linux/videodev2.h>
  26. #include <media/soc_camera.h>
  27. #include <media/i2c/tw9910.h>
  28. #include <media/v4l2-clk.h>
  29. #include <media/v4l2-subdev.h>
  30. #define GET_ID(val) ((val & 0xF8) >> 3)
  31. #define GET_REV(val) (val & 0x07)
  32. /*
  33. * register offset
  34. */
  35. #define ID 0x00 /* Product ID Code Register */
  36. #define STATUS1 0x01 /* Chip Status Register I */
  37. #define INFORM 0x02 /* Input Format */
  38. #define OPFORM 0x03 /* Output Format Control Register */
  39. #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
  40. #define OUTCTR1 0x05 /* Output Control I */
  41. #define ACNTL1 0x06 /* Analog Control Register 1 */
  42. #define CROP_HI 0x07 /* Cropping Register, High */
  43. #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
  44. #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
  45. #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
  46. #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
  47. #define CNTRL1 0x0C /* Control Register I */
  48. #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
  49. #define SCALE_HI 0x0E /* Scaling Register, High */
  50. #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
  51. #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
  52. #define CONTRAST 0x11 /* CONTRAST Control Register */
  53. #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
  54. #define SAT_U 0x13 /* Chroma (U) Gain Register */
  55. #define SAT_V 0x14 /* Chroma (V) Gain Register */
  56. #define HUE 0x15 /* Hue Control Register */
  57. #define CORING1 0x17
  58. #define CORING2 0x18 /* Coring and IF compensation */
  59. #define VBICNTL 0x19 /* VBI Control Register */
  60. #define ACNTL2 0x1A /* Analog Control 2 */
  61. #define OUTCTR2 0x1B /* Output Control 2 */
  62. #define SDT 0x1C /* Standard Selection */
  63. #define SDTR 0x1D /* Standard Recognition */
  64. #define TEST 0x1F /* Test Control Register */
  65. #define CLMPG 0x20 /* Clamping Gain */
  66. #define IAGC 0x21 /* Individual AGC Gain */
  67. #define AGCGAIN 0x22 /* AGC Gain */
  68. #define PEAKWT 0x23 /* White Peak Threshold */
  69. #define CLMPL 0x24 /* Clamp level */
  70. #define SYNCT 0x25 /* Sync Amplitude */
  71. #define MISSCNT 0x26 /* Sync Miss Count Register */
  72. #define PCLAMP 0x27 /* Clamp Position Register */
  73. #define VCNTL1 0x28 /* Vertical Control I */
  74. #define VCNTL2 0x29 /* Vertical Control II */
  75. #define CKILL 0x2A /* Color Killer Level Control */
  76. #define COMB 0x2B /* Comb Filter Control */
  77. #define LDLY 0x2C /* Luma Delay and H Filter Control */
  78. #define MISC1 0x2D /* Miscellaneous Control I */
  79. #define LOOP 0x2E /* LOOP Control Register */
  80. #define MISC2 0x2F /* Miscellaneous Control II */
  81. #define MVSN 0x30 /* Macrovision Detection */
  82. #define STATUS2 0x31 /* Chip STATUS II */
  83. #define HFREF 0x32 /* H monitor */
  84. #define CLMD 0x33 /* CLAMP MODE */
  85. #define IDCNTL 0x34 /* ID Detection Control */
  86. #define CLCNTL1 0x35 /* Clamp Control I */
  87. #define ANAPLLCTL 0x4C
  88. #define VBIMIN 0x4D
  89. #define HSLOWCTL 0x4E
  90. #define WSS3 0x4F
  91. #define FILLDATA 0x50
  92. #define SDID 0x51
  93. #define DID 0x52
  94. #define WSS1 0x53
  95. #define WSS2 0x54
  96. #define VVBI 0x55
  97. #define LCTL6 0x56
  98. #define LCTL7 0x57
  99. #define LCTL8 0x58
  100. #define LCTL9 0x59
  101. #define LCTL10 0x5A
  102. #define LCTL11 0x5B
  103. #define LCTL12 0x5C
  104. #define LCTL13 0x5D
  105. #define LCTL14 0x5E
  106. #define LCTL15 0x5F
  107. #define LCTL16 0x60
  108. #define LCTL17 0x61
  109. #define LCTL18 0x62
  110. #define LCTL19 0x63
  111. #define LCTL20 0x64
  112. #define LCTL21 0x65
  113. #define LCTL22 0x66
  114. #define LCTL23 0x67
  115. #define LCTL24 0x68
  116. #define LCTL25 0x69
  117. #define LCTL26 0x6A
  118. #define HSBEGIN 0x6B
  119. #define HSEND 0x6C
  120. #define OVSDLY 0x6D
  121. #define OVSEND 0x6E
  122. #define VBIDELAY 0x6F
  123. /*
  124. * register detail
  125. */
  126. /* INFORM */
  127. #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
  128. #define FC27_FF 0x00 /* 0 : Square pixel mode. */
  129. /* Must use 24.54MHz for 60Hz field rate */
  130. /* source or 29.5MHz for 50Hz field rate */
  131. #define IFSEL_S 0x10 /* 01 : S-video decoding */
  132. #define IFSEL_C 0x00 /* 00 : Composite video decoding */
  133. /* Y input video selection */
  134. #define YSEL_M0 0x00 /* 00 : Mux0 selected */
  135. #define YSEL_M1 0x04 /* 01 : Mux1 selected */
  136. #define YSEL_M2 0x08 /* 10 : Mux2 selected */
  137. #define YSEL_M3 0x10 /* 11 : Mux3 selected */
  138. /* OPFORM */
  139. #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
  140. /* 1 : ITU-R-656 compatible data sequence format */
  141. #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
  142. /* 1 : 16-bit YCrCb 4:2:2 output format.*/
  143. #define LLCMODE 0x20 /* 1 : LLC output mode. */
  144. /* 0 : free-run output mode */
  145. #define AINC 0x10 /* Serial interface auto-indexing control */
  146. /* 0 : auto-increment */
  147. /* 1 : non-auto */
  148. #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
  149. /* 0 : Vertical out ctrl by HACTIVE and DVALID */
  150. #define OEN_TRI_SEL_MASK 0x07
  151. #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
  152. #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
  153. #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
  154. /* OUTCTR1 */
  155. #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
  156. #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
  157. /* VS pin output control */
  158. #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
  159. #define VSSL_VACT 0x10 /* 1 : VACT */
  160. #define VSSL_FIELD 0x20 /* 2 : FIELD */
  161. #define VSSL_VVALID 0x30 /* 3 : VVALID */
  162. #define VSSL_ZERO 0x70 /* 7 : 0 */
  163. #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
  164. #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
  165. /* HS pin output control */
  166. #define HSSL_HACT 0x00 /* 0 : HACT */
  167. #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
  168. #define HSSL_DVALID 0x02 /* 2 : DVALID */
  169. #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
  170. #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
  171. #define HSSL_ZERO 0x07 /* 7 : 0 */
  172. /* ACNTL1 */
  173. #define SRESET 0x80 /* resets the device to its default state
  174. * but all register content remain unchanged.
  175. * This bit is self-resetting.
  176. */
  177. #define ACNTL1_PDN_MASK 0x0e
  178. #define CLK_PDN 0x08 /* system clock power down */
  179. #define Y_PDN 0x04 /* Luma ADC power down */
  180. #define C_PDN 0x02 /* Chroma ADC power down */
  181. /* ACNTL2 */
  182. #define ACNTL2_PDN_MASK 0x40
  183. #define PLL_PDN 0x40 /* PLL power down */
  184. /* VBICNTL */
  185. /* RTSEL : control the real time signal output from the MPOUT pin */
  186. #define RTSEL_MASK 0x07
  187. #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
  188. #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
  189. #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
  190. #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
  191. #define RTSEL_MONO 0x04 /* 0100 = MONO */
  192. #define RTSEL_DET50 0x05 /* 0101 = DET50 */
  193. #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
  194. #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
  195. /* HSYNC start and end are constant for now */
  196. #define HSYNC_START 0x0260
  197. #define HSYNC_END 0x0300
  198. /*
  199. * structure
  200. */
  201. struct regval_list {
  202. unsigned char reg_num;
  203. unsigned char value;
  204. };
  205. struct tw9910_scale_ctrl {
  206. char *name;
  207. unsigned short width;
  208. unsigned short height;
  209. u16 hscale;
  210. u16 vscale;
  211. };
  212. struct tw9910_priv {
  213. struct v4l2_subdev subdev;
  214. struct v4l2_clk *clk;
  215. struct tw9910_video_info *info;
  216. const struct tw9910_scale_ctrl *scale;
  217. v4l2_std_id norm;
  218. u32 revision;
  219. };
  220. static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
  221. {
  222. .name = "NTSC SQ",
  223. .width = 640,
  224. .height = 480,
  225. .hscale = 0x0100,
  226. .vscale = 0x0100,
  227. },
  228. {
  229. .name = "NTSC CCIR601",
  230. .width = 720,
  231. .height = 480,
  232. .hscale = 0x0100,
  233. .vscale = 0x0100,
  234. },
  235. {
  236. .name = "NTSC SQ (CIF)",
  237. .width = 320,
  238. .height = 240,
  239. .hscale = 0x0200,
  240. .vscale = 0x0200,
  241. },
  242. {
  243. .name = "NTSC CCIR601 (CIF)",
  244. .width = 360,
  245. .height = 240,
  246. .hscale = 0x0200,
  247. .vscale = 0x0200,
  248. },
  249. {
  250. .name = "NTSC SQ (QCIF)",
  251. .width = 160,
  252. .height = 120,
  253. .hscale = 0x0400,
  254. .vscale = 0x0400,
  255. },
  256. {
  257. .name = "NTSC CCIR601 (QCIF)",
  258. .width = 180,
  259. .height = 120,
  260. .hscale = 0x0400,
  261. .vscale = 0x0400,
  262. },
  263. };
  264. static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
  265. {
  266. .name = "PAL SQ",
  267. .width = 768,
  268. .height = 576,
  269. .hscale = 0x0100,
  270. .vscale = 0x0100,
  271. },
  272. {
  273. .name = "PAL CCIR601",
  274. .width = 720,
  275. .height = 576,
  276. .hscale = 0x0100,
  277. .vscale = 0x0100,
  278. },
  279. {
  280. .name = "PAL SQ (CIF)",
  281. .width = 384,
  282. .height = 288,
  283. .hscale = 0x0200,
  284. .vscale = 0x0200,
  285. },
  286. {
  287. .name = "PAL CCIR601 (CIF)",
  288. .width = 360,
  289. .height = 288,
  290. .hscale = 0x0200,
  291. .vscale = 0x0200,
  292. },
  293. {
  294. .name = "PAL SQ (QCIF)",
  295. .width = 192,
  296. .height = 144,
  297. .hscale = 0x0400,
  298. .vscale = 0x0400,
  299. },
  300. {
  301. .name = "PAL CCIR601 (QCIF)",
  302. .width = 180,
  303. .height = 144,
  304. .hscale = 0x0400,
  305. .vscale = 0x0400,
  306. },
  307. };
  308. /*
  309. * general function
  310. */
  311. static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
  312. {
  313. return container_of(i2c_get_clientdata(client), struct tw9910_priv,
  314. subdev);
  315. }
  316. static int tw9910_mask_set(struct i2c_client *client, u8 command,
  317. u8 mask, u8 set)
  318. {
  319. s32 val = i2c_smbus_read_byte_data(client, command);
  320. if (val < 0)
  321. return val;
  322. val &= ~mask;
  323. val |= set & mask;
  324. return i2c_smbus_write_byte_data(client, command, val);
  325. }
  326. static int tw9910_set_scale(struct i2c_client *client,
  327. const struct tw9910_scale_ctrl *scale)
  328. {
  329. int ret;
  330. ret = i2c_smbus_write_byte_data(client, SCALE_HI,
  331. (scale->vscale & 0x0F00) >> 4 |
  332. (scale->hscale & 0x0F00) >> 8);
  333. if (ret < 0)
  334. return ret;
  335. ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
  336. scale->hscale & 0x00FF);
  337. if (ret < 0)
  338. return ret;
  339. ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
  340. scale->vscale & 0x00FF);
  341. return ret;
  342. }
  343. static int tw9910_set_hsync(struct i2c_client *client)
  344. {
  345. struct tw9910_priv *priv = to_tw9910(client);
  346. int ret;
  347. /* bit 10 - 3 */
  348. ret = i2c_smbus_write_byte_data(client, HSBEGIN,
  349. (HSYNC_START & 0x07F8) >> 3);
  350. if (ret < 0)
  351. return ret;
  352. /* bit 10 - 3 */
  353. ret = i2c_smbus_write_byte_data(client, HSEND,
  354. (HSYNC_END & 0x07F8) >> 3);
  355. if (ret < 0)
  356. return ret;
  357. /* So far only revisions 0 and 1 have been seen */
  358. /* bit 2 - 0 */
  359. if (1 == priv->revision)
  360. ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
  361. (HSYNC_START & 0x0007) << 4 |
  362. (HSYNC_END & 0x0007));
  363. return ret;
  364. }
  365. static void tw9910_reset(struct i2c_client *client)
  366. {
  367. tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
  368. msleep(1);
  369. }
  370. static int tw9910_power(struct i2c_client *client, int enable)
  371. {
  372. int ret;
  373. u8 acntl1;
  374. u8 acntl2;
  375. if (enable) {
  376. acntl1 = 0;
  377. acntl2 = 0;
  378. } else {
  379. acntl1 = CLK_PDN | Y_PDN | C_PDN;
  380. acntl2 = PLL_PDN;
  381. }
  382. ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
  383. if (ret < 0)
  384. return ret;
  385. return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
  386. }
  387. static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
  388. u32 width, u32 height)
  389. {
  390. const struct tw9910_scale_ctrl *scale;
  391. const struct tw9910_scale_ctrl *ret = NULL;
  392. __u32 diff = 0xffffffff, tmp;
  393. int size, i;
  394. if (norm & V4L2_STD_NTSC) {
  395. scale = tw9910_ntsc_scales;
  396. size = ARRAY_SIZE(tw9910_ntsc_scales);
  397. } else if (norm & V4L2_STD_PAL) {
  398. scale = tw9910_pal_scales;
  399. size = ARRAY_SIZE(tw9910_pal_scales);
  400. } else {
  401. return NULL;
  402. }
  403. for (i = 0; i < size; i++) {
  404. tmp = abs(width - scale[i].width) +
  405. abs(height - scale[i].height);
  406. if (tmp < diff) {
  407. diff = tmp;
  408. ret = scale + i;
  409. }
  410. }
  411. return ret;
  412. }
  413. /*
  414. * subdevice operations
  415. */
  416. static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
  417. {
  418. struct i2c_client *client = v4l2_get_subdevdata(sd);
  419. struct tw9910_priv *priv = to_tw9910(client);
  420. u8 val;
  421. int ret;
  422. if (!enable) {
  423. switch (priv->revision) {
  424. case 0:
  425. val = OEN_TRI_SEL_ALL_OFF_r0;
  426. break;
  427. case 1:
  428. val = OEN_TRI_SEL_ALL_OFF_r1;
  429. break;
  430. default:
  431. dev_err(&client->dev, "un-supported revision\n");
  432. return -EINVAL;
  433. }
  434. } else {
  435. val = OEN_TRI_SEL_ALL_ON;
  436. if (!priv->scale) {
  437. dev_err(&client->dev, "norm select error\n");
  438. return -EPERM;
  439. }
  440. dev_dbg(&client->dev, "%s %dx%d\n",
  441. priv->scale->name,
  442. priv->scale->width,
  443. priv->scale->height);
  444. }
  445. ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
  446. if (ret < 0)
  447. return ret;
  448. return tw9910_power(client, enable);
  449. }
  450. static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
  451. {
  452. struct i2c_client *client = v4l2_get_subdevdata(sd);
  453. struct tw9910_priv *priv = to_tw9910(client);
  454. *norm = priv->norm;
  455. return 0;
  456. }
  457. static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
  458. {
  459. struct i2c_client *client = v4l2_get_subdevdata(sd);
  460. struct tw9910_priv *priv = to_tw9910(client);
  461. const unsigned hact = 720;
  462. const unsigned hdelay = 15;
  463. unsigned vact;
  464. unsigned vdelay;
  465. int ret;
  466. if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
  467. return -EINVAL;
  468. priv->norm = norm;
  469. if (norm & V4L2_STD_525_60) {
  470. vact = 240;
  471. vdelay = 18;
  472. ret = tw9910_mask_set(client, VVBI, 0x10, 0x10);
  473. } else {
  474. vact = 288;
  475. vdelay = 24;
  476. ret = tw9910_mask_set(client, VVBI, 0x10, 0x00);
  477. }
  478. if (!ret)
  479. ret = i2c_smbus_write_byte_data(client, CROP_HI,
  480. ((vdelay >> 2) & 0xc0) |
  481. ((vact >> 4) & 0x30) |
  482. ((hdelay >> 6) & 0x0c) |
  483. ((hact >> 8) & 0x03));
  484. if (!ret)
  485. ret = i2c_smbus_write_byte_data(client, VDELAY_LO,
  486. vdelay & 0xff);
  487. if (!ret)
  488. ret = i2c_smbus_write_byte_data(client, VACTIVE_LO,
  489. vact & 0xff);
  490. return ret;
  491. }
  492. #ifdef CONFIG_VIDEO_ADV_DEBUG
  493. static int tw9910_g_register(struct v4l2_subdev *sd,
  494. struct v4l2_dbg_register *reg)
  495. {
  496. struct i2c_client *client = v4l2_get_subdevdata(sd);
  497. int ret;
  498. if (reg->reg > 0xff)
  499. return -EINVAL;
  500. reg->size = 1;
  501. ret = i2c_smbus_read_byte_data(client, reg->reg);
  502. if (ret < 0)
  503. return ret;
  504. /*
  505. * ret = int
  506. * reg->val = __u64
  507. */
  508. reg->val = (__u64)ret;
  509. return 0;
  510. }
  511. static int tw9910_s_register(struct v4l2_subdev *sd,
  512. const struct v4l2_dbg_register *reg)
  513. {
  514. struct i2c_client *client = v4l2_get_subdevdata(sd);
  515. if (reg->reg > 0xff ||
  516. reg->val > 0xff)
  517. return -EINVAL;
  518. return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
  519. }
  520. #endif
  521. static int tw9910_s_power(struct v4l2_subdev *sd, int on)
  522. {
  523. struct i2c_client *client = v4l2_get_subdevdata(sd);
  524. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  525. struct tw9910_priv *priv = to_tw9910(client);
  526. return soc_camera_set_power(&client->dev, ssdd, priv->clk, on);
  527. }
  528. static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
  529. {
  530. struct i2c_client *client = v4l2_get_subdevdata(sd);
  531. struct tw9910_priv *priv = to_tw9910(client);
  532. int ret = -EINVAL;
  533. u8 val;
  534. /*
  535. * select suitable norm
  536. */
  537. priv->scale = tw9910_select_norm(priv->norm, *width, *height);
  538. if (!priv->scale)
  539. goto tw9910_set_fmt_error;
  540. /*
  541. * reset hardware
  542. */
  543. tw9910_reset(client);
  544. /*
  545. * set bus width
  546. */
  547. val = 0x00;
  548. if (SOCAM_DATAWIDTH_16 == priv->info->buswidth)
  549. val = LEN;
  550. ret = tw9910_mask_set(client, OPFORM, LEN, val);
  551. if (ret < 0)
  552. goto tw9910_set_fmt_error;
  553. /*
  554. * select MPOUT behavior
  555. */
  556. switch (priv->info->mpout) {
  557. case TW9910_MPO_VLOSS:
  558. val = RTSEL_VLOSS; break;
  559. case TW9910_MPO_HLOCK:
  560. val = RTSEL_HLOCK; break;
  561. case TW9910_MPO_SLOCK:
  562. val = RTSEL_SLOCK; break;
  563. case TW9910_MPO_VLOCK:
  564. val = RTSEL_VLOCK; break;
  565. case TW9910_MPO_MONO:
  566. val = RTSEL_MONO; break;
  567. case TW9910_MPO_DET50:
  568. val = RTSEL_DET50; break;
  569. case TW9910_MPO_FIELD:
  570. val = RTSEL_FIELD; break;
  571. case TW9910_MPO_RTCO:
  572. val = RTSEL_RTCO; break;
  573. default:
  574. val = 0;
  575. }
  576. ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
  577. if (ret < 0)
  578. goto tw9910_set_fmt_error;
  579. /*
  580. * set scale
  581. */
  582. ret = tw9910_set_scale(client, priv->scale);
  583. if (ret < 0)
  584. goto tw9910_set_fmt_error;
  585. /*
  586. * set hsync
  587. */
  588. ret = tw9910_set_hsync(client);
  589. if (ret < 0)
  590. goto tw9910_set_fmt_error;
  591. *width = priv->scale->width;
  592. *height = priv->scale->height;
  593. return ret;
  594. tw9910_set_fmt_error:
  595. tw9910_reset(client);
  596. priv->scale = NULL;
  597. return ret;
  598. }
  599. static int tw9910_get_selection(struct v4l2_subdev *sd,
  600. struct v4l2_subdev_pad_config *cfg,
  601. struct v4l2_subdev_selection *sel)
  602. {
  603. struct i2c_client *client = v4l2_get_subdevdata(sd);
  604. struct tw9910_priv *priv = to_tw9910(client);
  605. if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
  606. return -EINVAL;
  607. /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
  608. if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
  609. return -EINVAL;
  610. sel->r.left = 0;
  611. sel->r.top = 0;
  612. if (priv->norm & V4L2_STD_NTSC) {
  613. sel->r.width = 640;
  614. sel->r.height = 480;
  615. } else {
  616. sel->r.width = 768;
  617. sel->r.height = 576;
  618. }
  619. return 0;
  620. }
  621. static int tw9910_get_fmt(struct v4l2_subdev *sd,
  622. struct v4l2_subdev_pad_config *cfg,
  623. struct v4l2_subdev_format *format)
  624. {
  625. struct v4l2_mbus_framefmt *mf = &format->format;
  626. struct i2c_client *client = v4l2_get_subdevdata(sd);
  627. struct tw9910_priv *priv = to_tw9910(client);
  628. if (format->pad)
  629. return -EINVAL;
  630. if (!priv->scale) {
  631. priv->scale = tw9910_select_norm(priv->norm, 640, 480);
  632. if (!priv->scale)
  633. return -EINVAL;
  634. }
  635. mf->width = priv->scale->width;
  636. mf->height = priv->scale->height;
  637. mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
  638. mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
  639. mf->field = V4L2_FIELD_INTERLACED_BT;
  640. return 0;
  641. }
  642. static int tw9910_s_fmt(struct v4l2_subdev *sd,
  643. struct v4l2_mbus_framefmt *mf)
  644. {
  645. u32 width = mf->width, height = mf->height;
  646. int ret;
  647. WARN_ON(mf->field != V4L2_FIELD_ANY &&
  648. mf->field != V4L2_FIELD_INTERLACED_BT);
  649. /*
  650. * check color format
  651. */
  652. if (mf->code != MEDIA_BUS_FMT_UYVY8_2X8)
  653. return -EINVAL;
  654. mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
  655. ret = tw9910_set_frame(sd, &width, &height);
  656. if (!ret) {
  657. mf->width = width;
  658. mf->height = height;
  659. }
  660. return ret;
  661. }
  662. static int tw9910_set_fmt(struct v4l2_subdev *sd,
  663. struct v4l2_subdev_pad_config *cfg,
  664. struct v4l2_subdev_format *format)
  665. {
  666. struct v4l2_mbus_framefmt *mf = &format->format;
  667. struct i2c_client *client = v4l2_get_subdevdata(sd);
  668. struct tw9910_priv *priv = to_tw9910(client);
  669. const struct tw9910_scale_ctrl *scale;
  670. if (format->pad)
  671. return -EINVAL;
  672. if (V4L2_FIELD_ANY == mf->field) {
  673. mf->field = V4L2_FIELD_INTERLACED_BT;
  674. } else if (V4L2_FIELD_INTERLACED_BT != mf->field) {
  675. dev_err(&client->dev, "Field type %d invalid.\n", mf->field);
  676. return -EINVAL;
  677. }
  678. mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
  679. mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
  680. /*
  681. * select suitable norm
  682. */
  683. scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
  684. if (!scale)
  685. return -EINVAL;
  686. mf->width = scale->width;
  687. mf->height = scale->height;
  688. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  689. return tw9910_s_fmt(sd, mf);
  690. cfg->try_fmt = *mf;
  691. return 0;
  692. }
  693. static int tw9910_video_probe(struct i2c_client *client)
  694. {
  695. struct tw9910_priv *priv = to_tw9910(client);
  696. s32 id;
  697. int ret;
  698. /*
  699. * tw9910 only use 8 or 16 bit bus width
  700. */
  701. if (SOCAM_DATAWIDTH_16 != priv->info->buswidth &&
  702. SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
  703. dev_err(&client->dev, "bus width error\n");
  704. return -ENODEV;
  705. }
  706. ret = tw9910_s_power(&priv->subdev, 1);
  707. if (ret < 0)
  708. return ret;
  709. /*
  710. * check and show Product ID
  711. * So far only revisions 0 and 1 have been seen
  712. */
  713. id = i2c_smbus_read_byte_data(client, ID);
  714. priv->revision = GET_REV(id);
  715. id = GET_ID(id);
  716. if (0x0B != id ||
  717. 0x01 < priv->revision) {
  718. dev_err(&client->dev,
  719. "Product ID error %x:%x\n",
  720. id, priv->revision);
  721. ret = -ENODEV;
  722. goto done;
  723. }
  724. dev_info(&client->dev,
  725. "tw9910 Product ID %0x:%0x\n", id, priv->revision);
  726. priv->norm = V4L2_STD_NTSC;
  727. priv->scale = &tw9910_ntsc_scales[0];
  728. done:
  729. tw9910_s_power(&priv->subdev, 0);
  730. return ret;
  731. }
  732. static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
  733. #ifdef CONFIG_VIDEO_ADV_DEBUG
  734. .g_register = tw9910_g_register,
  735. .s_register = tw9910_s_register,
  736. #endif
  737. .s_power = tw9910_s_power,
  738. };
  739. static int tw9910_enum_mbus_code(struct v4l2_subdev *sd,
  740. struct v4l2_subdev_pad_config *cfg,
  741. struct v4l2_subdev_mbus_code_enum *code)
  742. {
  743. if (code->pad || code->index)
  744. return -EINVAL;
  745. code->code = MEDIA_BUS_FMT_UYVY8_2X8;
  746. return 0;
  747. }
  748. static int tw9910_g_mbus_config(struct v4l2_subdev *sd,
  749. struct v4l2_mbus_config *cfg)
  750. {
  751. struct i2c_client *client = v4l2_get_subdevdata(sd);
  752. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  753. cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
  754. V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
  755. V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
  756. V4L2_MBUS_DATA_ACTIVE_HIGH;
  757. cfg->type = V4L2_MBUS_PARALLEL;
  758. cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
  759. return 0;
  760. }
  761. static int tw9910_s_mbus_config(struct v4l2_subdev *sd,
  762. const struct v4l2_mbus_config *cfg)
  763. {
  764. struct i2c_client *client = v4l2_get_subdevdata(sd);
  765. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  766. u8 val = VSSL_VVALID | HSSL_DVALID;
  767. unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg);
  768. /*
  769. * set OUTCTR1
  770. *
  771. * We use VVALID and DVALID signals to control VSYNC and HSYNC
  772. * outputs, in this mode their polarity is inverted.
  773. */
  774. if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  775. val |= HSP_HI;
  776. if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  777. val |= VSP_HI;
  778. return i2c_smbus_write_byte_data(client, OUTCTR1, val);
  779. }
  780. static int tw9910_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
  781. {
  782. *norm = V4L2_STD_NTSC | V4L2_STD_PAL;
  783. return 0;
  784. }
  785. static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
  786. .s_std = tw9910_s_std,
  787. .g_std = tw9910_g_std,
  788. .s_stream = tw9910_s_stream,
  789. .g_mbus_config = tw9910_g_mbus_config,
  790. .s_mbus_config = tw9910_s_mbus_config,
  791. .g_tvnorms = tw9910_g_tvnorms,
  792. };
  793. static const struct v4l2_subdev_pad_ops tw9910_subdev_pad_ops = {
  794. .enum_mbus_code = tw9910_enum_mbus_code,
  795. .get_selection = tw9910_get_selection,
  796. .get_fmt = tw9910_get_fmt,
  797. .set_fmt = tw9910_set_fmt,
  798. };
  799. static struct v4l2_subdev_ops tw9910_subdev_ops = {
  800. .core = &tw9910_subdev_core_ops,
  801. .video = &tw9910_subdev_video_ops,
  802. .pad = &tw9910_subdev_pad_ops,
  803. };
  804. /*
  805. * i2c_driver function
  806. */
  807. static int tw9910_probe(struct i2c_client *client,
  808. const struct i2c_device_id *did)
  809. {
  810. struct tw9910_priv *priv;
  811. struct tw9910_video_info *info;
  812. struct i2c_adapter *adapter =
  813. to_i2c_adapter(client->dev.parent);
  814. struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
  815. int ret;
  816. if (!ssdd || !ssdd->drv_priv) {
  817. dev_err(&client->dev, "TW9910: missing platform data!\n");
  818. return -EINVAL;
  819. }
  820. info = ssdd->drv_priv;
  821. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
  822. dev_err(&client->dev,
  823. "I2C-Adapter doesn't support "
  824. "I2C_FUNC_SMBUS_BYTE_DATA\n");
  825. return -EIO;
  826. }
  827. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  828. if (!priv)
  829. return -ENOMEM;
  830. priv->info = info;
  831. v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
  832. priv->clk = v4l2_clk_get(&client->dev, "mclk");
  833. if (IS_ERR(priv->clk))
  834. return PTR_ERR(priv->clk);
  835. ret = tw9910_video_probe(client);
  836. if (ret < 0)
  837. v4l2_clk_put(priv->clk);
  838. return ret;
  839. }
  840. static int tw9910_remove(struct i2c_client *client)
  841. {
  842. struct tw9910_priv *priv = to_tw9910(client);
  843. v4l2_clk_put(priv->clk);
  844. return 0;
  845. }
  846. static const struct i2c_device_id tw9910_id[] = {
  847. { "tw9910", 0 },
  848. { }
  849. };
  850. MODULE_DEVICE_TABLE(i2c, tw9910_id);
  851. static struct i2c_driver tw9910_i2c_driver = {
  852. .driver = {
  853. .name = "tw9910",
  854. },
  855. .probe = tw9910_probe,
  856. .remove = tw9910_remove,
  857. .id_table = tw9910_id,
  858. };
  859. module_i2c_driver(tw9910_i2c_driver);
  860. MODULE_DESCRIPTION("SoC Camera driver for tw9910");
  861. MODULE_AUTHOR("Kuninori Morimoto");
  862. MODULE_LICENSE("GPL v2");