ccp-dmaengine.c 17 KB

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  1. /*
  2. * AMD Cryptographic Coprocessor (CCP) driver
  3. *
  4. * Copyright (C) 2016 Advanced Micro Devices, Inc.
  5. *
  6. * Author: Gary R Hook <gary.hook@amd.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/mutex.h>
  16. #include <linux/ccp.h>
  17. #include "ccp-dev.h"
  18. #include "../../dma/dmaengine.h"
  19. #define CCP_DMA_WIDTH(_mask) \
  20. ({ \
  21. u64 mask = _mask + 1; \
  22. (mask == 0) ? 64 : fls64(mask); \
  23. })
  24. static void ccp_free_cmd_resources(struct ccp_device *ccp,
  25. struct list_head *list)
  26. {
  27. struct ccp_dma_cmd *cmd, *ctmp;
  28. list_for_each_entry_safe(cmd, ctmp, list, entry) {
  29. list_del(&cmd->entry);
  30. kmem_cache_free(ccp->dma_cmd_cache, cmd);
  31. }
  32. }
  33. static void ccp_free_desc_resources(struct ccp_device *ccp,
  34. struct list_head *list)
  35. {
  36. struct ccp_dma_desc *desc, *dtmp;
  37. list_for_each_entry_safe(desc, dtmp, list, entry) {
  38. ccp_free_cmd_resources(ccp, &desc->active);
  39. ccp_free_cmd_resources(ccp, &desc->pending);
  40. list_del(&desc->entry);
  41. kmem_cache_free(ccp->dma_desc_cache, desc);
  42. }
  43. }
  44. static void ccp_free_chan_resources(struct dma_chan *dma_chan)
  45. {
  46. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  47. dma_chan);
  48. unsigned long flags;
  49. dev_dbg(chan->ccp->dev, "%s - chan=%p\n", __func__, chan);
  50. spin_lock_irqsave(&chan->lock, flags);
  51. ccp_free_desc_resources(chan->ccp, &chan->complete);
  52. ccp_free_desc_resources(chan->ccp, &chan->active);
  53. ccp_free_desc_resources(chan->ccp, &chan->pending);
  54. ccp_free_desc_resources(chan->ccp, &chan->created);
  55. spin_unlock_irqrestore(&chan->lock, flags);
  56. }
  57. static void ccp_cleanup_desc_resources(struct ccp_device *ccp,
  58. struct list_head *list)
  59. {
  60. struct ccp_dma_desc *desc, *dtmp;
  61. list_for_each_entry_safe_reverse(desc, dtmp, list, entry) {
  62. if (!async_tx_test_ack(&desc->tx_desc))
  63. continue;
  64. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  65. ccp_free_cmd_resources(ccp, &desc->active);
  66. ccp_free_cmd_resources(ccp, &desc->pending);
  67. list_del(&desc->entry);
  68. kmem_cache_free(ccp->dma_desc_cache, desc);
  69. }
  70. }
  71. static void ccp_do_cleanup(unsigned long data)
  72. {
  73. struct ccp_dma_chan *chan = (struct ccp_dma_chan *)data;
  74. unsigned long flags;
  75. dev_dbg(chan->ccp->dev, "%s - chan=%s\n", __func__,
  76. dma_chan_name(&chan->dma_chan));
  77. spin_lock_irqsave(&chan->lock, flags);
  78. ccp_cleanup_desc_resources(chan->ccp, &chan->complete);
  79. spin_unlock_irqrestore(&chan->lock, flags);
  80. }
  81. static int ccp_issue_next_cmd(struct ccp_dma_desc *desc)
  82. {
  83. struct ccp_dma_cmd *cmd;
  84. int ret;
  85. cmd = list_first_entry(&desc->pending, struct ccp_dma_cmd, entry);
  86. list_move(&cmd->entry, &desc->active);
  87. dev_dbg(desc->ccp->dev, "%s - tx %d, cmd=%p\n", __func__,
  88. desc->tx_desc.cookie, cmd);
  89. ret = ccp_enqueue_cmd(&cmd->ccp_cmd);
  90. if (!ret || (ret == -EINPROGRESS) || (ret == -EBUSY))
  91. return 0;
  92. dev_dbg(desc->ccp->dev, "%s - error: ret=%d, tx %d, cmd=%p\n", __func__,
  93. ret, desc->tx_desc.cookie, cmd);
  94. return ret;
  95. }
  96. static void ccp_free_active_cmd(struct ccp_dma_desc *desc)
  97. {
  98. struct ccp_dma_cmd *cmd;
  99. cmd = list_first_entry_or_null(&desc->active, struct ccp_dma_cmd,
  100. entry);
  101. if (!cmd)
  102. return;
  103. dev_dbg(desc->ccp->dev, "%s - freeing tx %d cmd=%p\n",
  104. __func__, desc->tx_desc.cookie, cmd);
  105. list_del(&cmd->entry);
  106. kmem_cache_free(desc->ccp->dma_cmd_cache, cmd);
  107. }
  108. static struct ccp_dma_desc *__ccp_next_dma_desc(struct ccp_dma_chan *chan,
  109. struct ccp_dma_desc *desc)
  110. {
  111. /* Move current DMA descriptor to the complete list */
  112. if (desc)
  113. list_move(&desc->entry, &chan->complete);
  114. /* Get the next DMA descriptor on the active list */
  115. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  116. entry);
  117. return desc;
  118. }
  119. static struct ccp_dma_desc *ccp_handle_active_desc(struct ccp_dma_chan *chan,
  120. struct ccp_dma_desc *desc)
  121. {
  122. struct dma_async_tx_descriptor *tx_desc;
  123. unsigned long flags;
  124. /* Loop over descriptors until one is found with commands */
  125. do {
  126. if (desc) {
  127. /* Remove the DMA command from the list and free it */
  128. ccp_free_active_cmd(desc);
  129. if (!list_empty(&desc->pending)) {
  130. /* No errors, keep going */
  131. if (desc->status != DMA_ERROR)
  132. return desc;
  133. /* Error, free remaining commands and move on */
  134. ccp_free_cmd_resources(desc->ccp,
  135. &desc->pending);
  136. }
  137. tx_desc = &desc->tx_desc;
  138. } else {
  139. tx_desc = NULL;
  140. }
  141. spin_lock_irqsave(&chan->lock, flags);
  142. if (desc) {
  143. if (desc->status != DMA_ERROR)
  144. desc->status = DMA_COMPLETE;
  145. dev_dbg(desc->ccp->dev,
  146. "%s - tx %d complete, status=%u\n", __func__,
  147. desc->tx_desc.cookie, desc->status);
  148. dma_cookie_complete(tx_desc);
  149. }
  150. desc = __ccp_next_dma_desc(chan, desc);
  151. spin_unlock_irqrestore(&chan->lock, flags);
  152. if (tx_desc) {
  153. if (tx_desc->callback &&
  154. (tx_desc->flags & DMA_PREP_INTERRUPT))
  155. tx_desc->callback(tx_desc->callback_param);
  156. dma_run_dependencies(tx_desc);
  157. }
  158. } while (desc);
  159. return NULL;
  160. }
  161. static struct ccp_dma_desc *__ccp_pending_to_active(struct ccp_dma_chan *chan)
  162. {
  163. struct ccp_dma_desc *desc;
  164. if (list_empty(&chan->pending))
  165. return NULL;
  166. desc = list_empty(&chan->active)
  167. ? list_first_entry(&chan->pending, struct ccp_dma_desc, entry)
  168. : NULL;
  169. list_splice_tail_init(&chan->pending, &chan->active);
  170. return desc;
  171. }
  172. static void ccp_cmd_callback(void *data, int err)
  173. {
  174. struct ccp_dma_desc *desc = data;
  175. struct ccp_dma_chan *chan;
  176. int ret;
  177. if (err == -EINPROGRESS)
  178. return;
  179. chan = container_of(desc->tx_desc.chan, struct ccp_dma_chan,
  180. dma_chan);
  181. dev_dbg(chan->ccp->dev, "%s - tx %d callback, err=%d\n",
  182. __func__, desc->tx_desc.cookie, err);
  183. if (err)
  184. desc->status = DMA_ERROR;
  185. while (true) {
  186. /* Check for DMA descriptor completion */
  187. desc = ccp_handle_active_desc(chan, desc);
  188. /* Don't submit cmd if no descriptor or DMA is paused */
  189. if (!desc || (chan->status == DMA_PAUSED))
  190. break;
  191. ret = ccp_issue_next_cmd(desc);
  192. if (!ret)
  193. break;
  194. desc->status = DMA_ERROR;
  195. }
  196. tasklet_schedule(&chan->cleanup_tasklet);
  197. }
  198. static dma_cookie_t ccp_tx_submit(struct dma_async_tx_descriptor *tx_desc)
  199. {
  200. struct ccp_dma_desc *desc = container_of(tx_desc, struct ccp_dma_desc,
  201. tx_desc);
  202. struct ccp_dma_chan *chan;
  203. dma_cookie_t cookie;
  204. unsigned long flags;
  205. chan = container_of(tx_desc->chan, struct ccp_dma_chan, dma_chan);
  206. spin_lock_irqsave(&chan->lock, flags);
  207. cookie = dma_cookie_assign(tx_desc);
  208. list_del(&desc->entry);
  209. list_add_tail(&desc->entry, &chan->pending);
  210. spin_unlock_irqrestore(&chan->lock, flags);
  211. dev_dbg(chan->ccp->dev, "%s - added tx descriptor %d to pending list\n",
  212. __func__, cookie);
  213. return cookie;
  214. }
  215. static struct ccp_dma_cmd *ccp_alloc_dma_cmd(struct ccp_dma_chan *chan)
  216. {
  217. struct ccp_dma_cmd *cmd;
  218. cmd = kmem_cache_alloc(chan->ccp->dma_cmd_cache, GFP_NOWAIT);
  219. if (cmd)
  220. memset(cmd, 0, sizeof(*cmd));
  221. return cmd;
  222. }
  223. static struct ccp_dma_desc *ccp_alloc_dma_desc(struct ccp_dma_chan *chan,
  224. unsigned long flags)
  225. {
  226. struct ccp_dma_desc *desc;
  227. desc = kmem_cache_zalloc(chan->ccp->dma_desc_cache, GFP_NOWAIT);
  228. if (!desc)
  229. return NULL;
  230. dma_async_tx_descriptor_init(&desc->tx_desc, &chan->dma_chan);
  231. desc->tx_desc.flags = flags;
  232. desc->tx_desc.tx_submit = ccp_tx_submit;
  233. desc->ccp = chan->ccp;
  234. INIT_LIST_HEAD(&desc->pending);
  235. INIT_LIST_HEAD(&desc->active);
  236. desc->status = DMA_IN_PROGRESS;
  237. return desc;
  238. }
  239. static struct ccp_dma_desc *ccp_create_desc(struct dma_chan *dma_chan,
  240. struct scatterlist *dst_sg,
  241. unsigned int dst_nents,
  242. struct scatterlist *src_sg,
  243. unsigned int src_nents,
  244. unsigned long flags)
  245. {
  246. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  247. dma_chan);
  248. struct ccp_device *ccp = chan->ccp;
  249. struct ccp_dma_desc *desc;
  250. struct ccp_dma_cmd *cmd;
  251. struct ccp_cmd *ccp_cmd;
  252. struct ccp_passthru_nomap_engine *ccp_pt;
  253. unsigned int src_offset, src_len;
  254. unsigned int dst_offset, dst_len;
  255. unsigned int len;
  256. unsigned long sflags;
  257. size_t total_len;
  258. if (!dst_sg || !src_sg)
  259. return NULL;
  260. if (!dst_nents || !src_nents)
  261. return NULL;
  262. desc = ccp_alloc_dma_desc(chan, flags);
  263. if (!desc)
  264. return NULL;
  265. total_len = 0;
  266. src_len = sg_dma_len(src_sg);
  267. src_offset = 0;
  268. dst_len = sg_dma_len(dst_sg);
  269. dst_offset = 0;
  270. while (true) {
  271. if (!src_len) {
  272. src_nents--;
  273. if (!src_nents)
  274. break;
  275. src_sg = sg_next(src_sg);
  276. if (!src_sg)
  277. break;
  278. src_len = sg_dma_len(src_sg);
  279. src_offset = 0;
  280. continue;
  281. }
  282. if (!dst_len) {
  283. dst_nents--;
  284. if (!dst_nents)
  285. break;
  286. dst_sg = sg_next(dst_sg);
  287. if (!dst_sg)
  288. break;
  289. dst_len = sg_dma_len(dst_sg);
  290. dst_offset = 0;
  291. continue;
  292. }
  293. len = min(dst_len, src_len);
  294. cmd = ccp_alloc_dma_cmd(chan);
  295. if (!cmd)
  296. goto err;
  297. ccp_cmd = &cmd->ccp_cmd;
  298. ccp_cmd->ccp = chan->ccp;
  299. ccp_pt = &ccp_cmd->u.passthru_nomap;
  300. ccp_cmd->flags = CCP_CMD_MAY_BACKLOG;
  301. ccp_cmd->flags |= CCP_CMD_PASSTHRU_NO_DMA_MAP;
  302. ccp_cmd->engine = CCP_ENGINE_PASSTHRU;
  303. ccp_pt->bit_mod = CCP_PASSTHRU_BITWISE_NOOP;
  304. ccp_pt->byte_swap = CCP_PASSTHRU_BYTESWAP_NOOP;
  305. ccp_pt->src_dma = sg_dma_address(src_sg) + src_offset;
  306. ccp_pt->dst_dma = sg_dma_address(dst_sg) + dst_offset;
  307. ccp_pt->src_len = len;
  308. ccp_pt->final = 1;
  309. ccp_cmd->callback = ccp_cmd_callback;
  310. ccp_cmd->data = desc;
  311. list_add_tail(&cmd->entry, &desc->pending);
  312. dev_dbg(ccp->dev,
  313. "%s - cmd=%p, src=%pad, dst=%pad, len=%llu\n", __func__,
  314. cmd, &ccp_pt->src_dma,
  315. &ccp_pt->dst_dma, ccp_pt->src_len);
  316. total_len += len;
  317. src_len -= len;
  318. src_offset += len;
  319. dst_len -= len;
  320. dst_offset += len;
  321. }
  322. desc->len = total_len;
  323. if (list_empty(&desc->pending))
  324. goto err;
  325. dev_dbg(ccp->dev, "%s - desc=%p\n", __func__, desc);
  326. spin_lock_irqsave(&chan->lock, sflags);
  327. list_add_tail(&desc->entry, &chan->created);
  328. spin_unlock_irqrestore(&chan->lock, sflags);
  329. return desc;
  330. err:
  331. ccp_free_cmd_resources(ccp, &desc->pending);
  332. kmem_cache_free(ccp->dma_desc_cache, desc);
  333. return NULL;
  334. }
  335. static struct dma_async_tx_descriptor *ccp_prep_dma_memcpy(
  336. struct dma_chan *dma_chan, dma_addr_t dst, dma_addr_t src, size_t len,
  337. unsigned long flags)
  338. {
  339. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  340. dma_chan);
  341. struct ccp_dma_desc *desc;
  342. struct scatterlist dst_sg, src_sg;
  343. dev_dbg(chan->ccp->dev,
  344. "%s - src=%pad, dst=%pad, len=%zu, flags=%#lx\n",
  345. __func__, &src, &dst, len, flags);
  346. sg_init_table(&dst_sg, 1);
  347. sg_dma_address(&dst_sg) = dst;
  348. sg_dma_len(&dst_sg) = len;
  349. sg_init_table(&src_sg, 1);
  350. sg_dma_address(&src_sg) = src;
  351. sg_dma_len(&src_sg) = len;
  352. desc = ccp_create_desc(dma_chan, &dst_sg, 1, &src_sg, 1, flags);
  353. if (!desc)
  354. return NULL;
  355. return &desc->tx_desc;
  356. }
  357. static struct dma_async_tx_descriptor *ccp_prep_dma_sg(
  358. struct dma_chan *dma_chan, struct scatterlist *dst_sg,
  359. unsigned int dst_nents, struct scatterlist *src_sg,
  360. unsigned int src_nents, unsigned long flags)
  361. {
  362. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  363. dma_chan);
  364. struct ccp_dma_desc *desc;
  365. dev_dbg(chan->ccp->dev,
  366. "%s - src=%p, src_nents=%u dst=%p, dst_nents=%u, flags=%#lx\n",
  367. __func__, src_sg, src_nents, dst_sg, dst_nents, flags);
  368. desc = ccp_create_desc(dma_chan, dst_sg, dst_nents, src_sg, src_nents,
  369. flags);
  370. if (!desc)
  371. return NULL;
  372. return &desc->tx_desc;
  373. }
  374. static struct dma_async_tx_descriptor *ccp_prep_dma_interrupt(
  375. struct dma_chan *dma_chan, unsigned long flags)
  376. {
  377. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  378. dma_chan);
  379. struct ccp_dma_desc *desc;
  380. desc = ccp_alloc_dma_desc(chan, flags);
  381. if (!desc)
  382. return NULL;
  383. return &desc->tx_desc;
  384. }
  385. static void ccp_issue_pending(struct dma_chan *dma_chan)
  386. {
  387. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  388. dma_chan);
  389. struct ccp_dma_desc *desc;
  390. unsigned long flags;
  391. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  392. spin_lock_irqsave(&chan->lock, flags);
  393. desc = __ccp_pending_to_active(chan);
  394. spin_unlock_irqrestore(&chan->lock, flags);
  395. /* If there was nothing active, start processing */
  396. if (desc)
  397. ccp_cmd_callback(desc, 0);
  398. }
  399. static enum dma_status ccp_tx_status(struct dma_chan *dma_chan,
  400. dma_cookie_t cookie,
  401. struct dma_tx_state *state)
  402. {
  403. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  404. dma_chan);
  405. struct ccp_dma_desc *desc;
  406. enum dma_status ret;
  407. unsigned long flags;
  408. if (chan->status == DMA_PAUSED) {
  409. ret = DMA_PAUSED;
  410. goto out;
  411. }
  412. ret = dma_cookie_status(dma_chan, cookie, state);
  413. if (ret == DMA_COMPLETE) {
  414. spin_lock_irqsave(&chan->lock, flags);
  415. /* Get status from complete chain, if still there */
  416. list_for_each_entry(desc, &chan->complete, entry) {
  417. if (desc->tx_desc.cookie != cookie)
  418. continue;
  419. ret = desc->status;
  420. break;
  421. }
  422. spin_unlock_irqrestore(&chan->lock, flags);
  423. }
  424. out:
  425. dev_dbg(chan->ccp->dev, "%s - %u\n", __func__, ret);
  426. return ret;
  427. }
  428. static int ccp_pause(struct dma_chan *dma_chan)
  429. {
  430. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  431. dma_chan);
  432. chan->status = DMA_PAUSED;
  433. /*TODO: Wait for active DMA to complete before returning? */
  434. return 0;
  435. }
  436. static int ccp_resume(struct dma_chan *dma_chan)
  437. {
  438. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  439. dma_chan);
  440. struct ccp_dma_desc *desc;
  441. unsigned long flags;
  442. spin_lock_irqsave(&chan->lock, flags);
  443. desc = list_first_entry_or_null(&chan->active, struct ccp_dma_desc,
  444. entry);
  445. spin_unlock_irqrestore(&chan->lock, flags);
  446. /* Indicate the channel is running again */
  447. chan->status = DMA_IN_PROGRESS;
  448. /* If there was something active, re-start */
  449. if (desc)
  450. ccp_cmd_callback(desc, 0);
  451. return 0;
  452. }
  453. static int ccp_terminate_all(struct dma_chan *dma_chan)
  454. {
  455. struct ccp_dma_chan *chan = container_of(dma_chan, struct ccp_dma_chan,
  456. dma_chan);
  457. unsigned long flags;
  458. dev_dbg(chan->ccp->dev, "%s\n", __func__);
  459. /*TODO: Wait for active DMA to complete before continuing */
  460. spin_lock_irqsave(&chan->lock, flags);
  461. /*TODO: Purge the complete list? */
  462. ccp_free_desc_resources(chan->ccp, &chan->active);
  463. ccp_free_desc_resources(chan->ccp, &chan->pending);
  464. ccp_free_desc_resources(chan->ccp, &chan->created);
  465. spin_unlock_irqrestore(&chan->lock, flags);
  466. return 0;
  467. }
  468. int ccp_dmaengine_register(struct ccp_device *ccp)
  469. {
  470. struct ccp_dma_chan *chan;
  471. struct dma_device *dma_dev = &ccp->dma_dev;
  472. struct dma_chan *dma_chan;
  473. char *dma_cmd_cache_name;
  474. char *dma_desc_cache_name;
  475. unsigned int i;
  476. int ret;
  477. ccp->ccp_dma_chan = devm_kcalloc(ccp->dev, ccp->cmd_q_count,
  478. sizeof(*(ccp->ccp_dma_chan)),
  479. GFP_KERNEL);
  480. if (!ccp->ccp_dma_chan)
  481. return -ENOMEM;
  482. dma_cmd_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  483. "%s-dmaengine-cmd-cache",
  484. ccp->name);
  485. if (!dma_cmd_cache_name)
  486. return -ENOMEM;
  487. ccp->dma_cmd_cache = kmem_cache_create(dma_cmd_cache_name,
  488. sizeof(struct ccp_dma_cmd),
  489. sizeof(void *),
  490. SLAB_HWCACHE_ALIGN, NULL);
  491. if (!ccp->dma_cmd_cache)
  492. return -ENOMEM;
  493. dma_desc_cache_name = devm_kasprintf(ccp->dev, GFP_KERNEL,
  494. "%s-dmaengine-desc-cache",
  495. ccp->name);
  496. if (!dma_desc_cache_name) {
  497. ret = -ENOMEM;
  498. goto err_cache;
  499. }
  500. ccp->dma_desc_cache = kmem_cache_create(dma_desc_cache_name,
  501. sizeof(struct ccp_dma_desc),
  502. sizeof(void *),
  503. SLAB_HWCACHE_ALIGN, NULL);
  504. if (!ccp->dma_desc_cache) {
  505. ret = -ENOMEM;
  506. goto err_cache;
  507. }
  508. dma_dev->dev = ccp->dev;
  509. dma_dev->src_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  510. dma_dev->dst_addr_widths = CCP_DMA_WIDTH(dma_get_mask(ccp->dev));
  511. dma_dev->directions = DMA_MEM_TO_MEM;
  512. dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
  513. dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
  514. dma_cap_set(DMA_SG, dma_dev->cap_mask);
  515. dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
  516. INIT_LIST_HEAD(&dma_dev->channels);
  517. for (i = 0; i < ccp->cmd_q_count; i++) {
  518. chan = ccp->ccp_dma_chan + i;
  519. dma_chan = &chan->dma_chan;
  520. chan->ccp = ccp;
  521. spin_lock_init(&chan->lock);
  522. INIT_LIST_HEAD(&chan->created);
  523. INIT_LIST_HEAD(&chan->pending);
  524. INIT_LIST_HEAD(&chan->active);
  525. INIT_LIST_HEAD(&chan->complete);
  526. tasklet_init(&chan->cleanup_tasklet, ccp_do_cleanup,
  527. (unsigned long)chan);
  528. dma_chan->device = dma_dev;
  529. dma_cookie_init(dma_chan);
  530. list_add_tail(&dma_chan->device_node, &dma_dev->channels);
  531. }
  532. dma_dev->device_free_chan_resources = ccp_free_chan_resources;
  533. dma_dev->device_prep_dma_memcpy = ccp_prep_dma_memcpy;
  534. dma_dev->device_prep_dma_sg = ccp_prep_dma_sg;
  535. dma_dev->device_prep_dma_interrupt = ccp_prep_dma_interrupt;
  536. dma_dev->device_issue_pending = ccp_issue_pending;
  537. dma_dev->device_tx_status = ccp_tx_status;
  538. dma_dev->device_pause = ccp_pause;
  539. dma_dev->device_resume = ccp_resume;
  540. dma_dev->device_terminate_all = ccp_terminate_all;
  541. ret = dma_async_device_register(dma_dev);
  542. if (ret)
  543. goto err_reg;
  544. return 0;
  545. err_reg:
  546. kmem_cache_destroy(ccp->dma_desc_cache);
  547. err_cache:
  548. kmem_cache_destroy(ccp->dma_cmd_cache);
  549. return ret;
  550. }
  551. void ccp_dmaengine_unregister(struct ccp_device *ccp)
  552. {
  553. struct dma_device *dma_dev = &ccp->dma_dev;
  554. dma_async_device_unregister(dma_dev);
  555. kmem_cache_destroy(ccp->dma_desc_cache);
  556. kmem_cache_destroy(ccp->dma_cmd_cache);
  557. }