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linux-libre
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arch
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unicore32
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include
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mach
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regs-ost.h

regs-ost.h 1.7 KB
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  1. /*
    2. 

  2.  * PKUnity Operating System Timer (OST) Registers
    3. 

  3.  */
    4. 

  4. /*
    5. 

  5.  * Match Reg 0 OST_OSMR0
    6. 

  6.  */
    7. 

  7. #define OST_OSMR0	(PKUNITY_OST_BASE + 0x0000)
    8. 

  8. /*
    9. 

  9.  * Match Reg 1 OST_OSMR1
    10. 

  10.  */
    11. 

  11. #define OST_OSMR1	(PKUNITY_OST_BASE + 0x0004)
    12. 

  12. /*
    13. 

  13.  * Match Reg 2 OST_OSMR2
    14. 

  14.  */
    15. 

  15. #define OST_OSMR2	(PKUNITY_OST_BASE + 0x0008)
    16. 

  16. /*
    17. 

  17.  * Match Reg 3 OST_OSMR3
    18. 

  18.  */
    19. 

  19. #define OST_OSMR3	(PKUNITY_OST_BASE + 0x000C)
    20. 

  20. /*
    21. 

  21.  * Counter Reg OST_OSCR
    22. 

  22.  */
    23. 

  23. #define OST_OSCR	(PKUNITY_OST_BASE + 0x0010)
    24. 

  24. /*
    25. 

  25.  * Status Reg OST_OSSR
    26. 

  26.  */
    27. 

  27. #define OST_OSSR	(PKUNITY_OST_BASE + 0x0014)
    28. 

  28. /*
    29. 

  29.  * Watchdog Enable Reg OST_OWER
    30. 

  30.  */
    31. 

  31. #define OST_OWER	(PKUNITY_OST_BASE + 0x0018)
    32. 

  32. /*
    33. 

  33.  * Interrupt Enable Reg OST_OIER
    34. 

  34.  */
    35. 

  35. #define OST_OIER	(PKUNITY_OST_BASE + 0x001C)
    36. 

  36. 

  37. /*
    38. 

  38.  * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
    39. 

  39.  *      PWCR: Pulse Width Control Reg
    40. 

  40.  *      DCCR: Duty Cycle Control Reg
    41. 

  41.  *      PCR: Period Control Reg
    42. 

  42.  */
    43. 

  43. #define OST_PWM_PWCR	(0x00)
    44. 

  44. #define OST_PWM_DCCR	(0x04)
    45. 

  45. #define OST_PWM_PCR 	(0x08)
    46. 

  46. 

  47. /*
    48. 

  48.  * Match detected 0 OST_OSSR_M0
    49. 

  49.  */
    50. 

  50. #define OST_OSSR_M0		FIELD(1, 1, 0)
    51. 

  51. /*
    52. 

  52.  * Match detected 1 OST_OSSR_M1
    53. 

  53.  */
    54. 

  54. #define OST_OSSR_M1		FIELD(1, 1, 1)
    55. 

  55. /*
    56. 

  56.  * Match detected 2 OST_OSSR_M2
    57. 

  57.  */
    58. 

  58. #define OST_OSSR_M2		FIELD(1, 1, 2)
    59. 

  59. /*
    60. 

  60.  * Match detected 3 OST_OSSR_M3
    61. 

  61.  */
    62. 

  62. #define OST_OSSR_M3		FIELD(1, 1, 3)
    63. 

  63. 

  64. /*
    65. 

  65.  * Interrupt enable 0 OST_OIER_E0
    66. 

  66.  */
    67. 

  67. #define OST_OIER_E0		FIELD(1, 1, 0)
    68. 

  68. /*
    69. 

  69.  * Interrupt enable 1 OST_OIER_E1
    70. 

  70.  */
    71. 

  71. #define OST_OIER_E1		FIELD(1, 1, 1)
    72. 

  72. /*
    73. 

  73.  * Interrupt enable 2 OST_OIER_E2
    74. 

  74.  */
    75. 

  75. #define OST_OIER_E2		FIELD(1, 1, 2)
    76. 

  76. /*
    77. 

  77.  * Interrupt enable 3 OST_OIER_E3
    78. 

  78.  */
    79. 

  79. #define OST_OIER_E3		FIELD(1, 1, 3)
    80. 

  80. 

  81. /*
    82. 

  82.  * Watchdog Match Enable OST_OWER_WME
    83. 

  83.  */
    84. 

  84. #define OST_OWER_WME		FIELD(1, 1, 0)
    85. 

  85. 

  86. /*
    87. 

  87.  * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE
    88. 

  88.  */
    89. 

  89. #define OST_PWMDCCR_FDCYCLE	FIELD(1, 1, 10)
    90. 

  90. 

  91.