smp.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712
  1. /*
  2. * This program is free software; you can redistribute it and/or
  3. * modify it under the terms of the GNU General Public License
  4. * as published by the Free Software Foundation; either version 2
  5. * of the License, or (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  15. *
  16. * Copyright (C) 2000, 2001 Kanoj Sarcar
  17. * Copyright (C) 2000, 2001 Ralf Baechle
  18. * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
  19. * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
  20. */
  21. #include <linux/cache.h>
  22. #include <linux/delay.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/smp.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/threads.h>
  28. #include <linux/export.h>
  29. #include <linux/time.h>
  30. #include <linux/timex.h>
  31. #include <linux/sched.h>
  32. #include <linux/cpumask.h>
  33. #include <linux/cpu.h>
  34. #include <linux/err.h>
  35. #include <linux/ftrace.h>
  36. #include <linux/irqdomain.h>
  37. #include <linux/of.h>
  38. #include <linux/of_irq.h>
  39. #include <linux/atomic.h>
  40. #include <asm/cpu.h>
  41. #include <asm/processor.h>
  42. #include <asm/idle.h>
  43. #include <asm/r4k-timer.h>
  44. #include <asm/mips-cpc.h>
  45. #include <asm/mmu_context.h>
  46. #include <asm/time.h>
  47. #include <asm/setup.h>
  48. #include <asm/maar.h>
  49. cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
  50. int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
  51. EXPORT_SYMBOL(__cpu_number_map);
  52. int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
  53. EXPORT_SYMBOL(__cpu_logical_map);
  54. /* Number of TCs (or siblings in Intel speak) per CPU core */
  55. int smp_num_siblings = 1;
  56. EXPORT_SYMBOL(smp_num_siblings);
  57. /* representing the TCs (or siblings in Intel speak) of each logical CPU */
  58. cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
  59. EXPORT_SYMBOL(cpu_sibling_map);
  60. /* representing the core map of multi-core chips of each logical CPU */
  61. cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
  62. EXPORT_SYMBOL(cpu_core_map);
  63. static DECLARE_COMPLETION(cpu_starting);
  64. static DECLARE_COMPLETION(cpu_running);
  65. /*
  66. * A logcal cpu mask containing only one VPE per core to
  67. * reduce the number of IPIs on large MT systems.
  68. */
  69. cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
  70. EXPORT_SYMBOL(cpu_foreign_map);
  71. /* representing cpus for which sibling maps can be computed */
  72. static cpumask_t cpu_sibling_setup_map;
  73. /* representing cpus for which core maps can be computed */
  74. static cpumask_t cpu_core_setup_map;
  75. cpumask_t cpu_coherent_mask;
  76. #ifdef CONFIG_GENERIC_IRQ_IPI
  77. static struct irq_desc *call_desc;
  78. static struct irq_desc *sched_desc;
  79. #endif
  80. static inline void set_cpu_sibling_map(int cpu)
  81. {
  82. int i;
  83. cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
  84. if (smp_num_siblings > 1) {
  85. for_each_cpu(i, &cpu_sibling_setup_map) {
  86. if (cpu_data[cpu].package == cpu_data[i].package &&
  87. cpu_data[cpu].core == cpu_data[i].core) {
  88. cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
  89. cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
  90. }
  91. }
  92. } else
  93. cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
  94. }
  95. static inline void set_cpu_core_map(int cpu)
  96. {
  97. int i;
  98. cpumask_set_cpu(cpu, &cpu_core_setup_map);
  99. for_each_cpu(i, &cpu_core_setup_map) {
  100. if (cpu_data[cpu].package == cpu_data[i].package) {
  101. cpumask_set_cpu(i, &cpu_core_map[cpu]);
  102. cpumask_set_cpu(cpu, &cpu_core_map[i]);
  103. }
  104. }
  105. }
  106. /*
  107. * Calculate a new cpu_foreign_map mask whenever a
  108. * new cpu appears or disappears.
  109. */
  110. void calculate_cpu_foreign_map(void)
  111. {
  112. int i, k, core_present;
  113. cpumask_t temp_foreign_map;
  114. /* Re-calculate the mask */
  115. cpumask_clear(&temp_foreign_map);
  116. for_each_online_cpu(i) {
  117. core_present = 0;
  118. for_each_cpu(k, &temp_foreign_map)
  119. if (cpu_data[i].package == cpu_data[k].package &&
  120. cpu_data[i].core == cpu_data[k].core)
  121. core_present = 1;
  122. if (!core_present)
  123. cpumask_set_cpu(i, &temp_foreign_map);
  124. }
  125. for_each_online_cpu(i)
  126. cpumask_andnot(&cpu_foreign_map[i],
  127. &temp_foreign_map, &cpu_sibling_map[i]);
  128. }
  129. struct plat_smp_ops *mp_ops;
  130. EXPORT_SYMBOL(mp_ops);
  131. void register_smp_ops(struct plat_smp_ops *ops)
  132. {
  133. if (mp_ops)
  134. printk(KERN_WARNING "Overriding previously set SMP ops\n");
  135. mp_ops = ops;
  136. }
  137. #ifdef CONFIG_GENERIC_IRQ_IPI
  138. void mips_smp_send_ipi_single(int cpu, unsigned int action)
  139. {
  140. mips_smp_send_ipi_mask(cpumask_of(cpu), action);
  141. }
  142. void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
  143. {
  144. unsigned long flags;
  145. unsigned int core;
  146. int cpu;
  147. local_irq_save(flags);
  148. switch (action) {
  149. case SMP_CALL_FUNCTION:
  150. __ipi_send_mask(call_desc, mask);
  151. break;
  152. case SMP_RESCHEDULE_YOURSELF:
  153. __ipi_send_mask(sched_desc, mask);
  154. break;
  155. default:
  156. BUG();
  157. }
  158. if (mips_cpc_present()) {
  159. for_each_cpu(cpu, mask) {
  160. core = cpu_data[cpu].core;
  161. if (core == current_cpu_data.core)
  162. continue;
  163. while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
  164. mips_cm_lock_other(core, 0);
  165. mips_cpc_lock_other(core);
  166. write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
  167. mips_cpc_unlock_other();
  168. mips_cm_unlock_other();
  169. }
  170. }
  171. }
  172. local_irq_restore(flags);
  173. }
  174. static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
  175. {
  176. scheduler_ipi();
  177. return IRQ_HANDLED;
  178. }
  179. static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
  180. {
  181. generic_smp_call_function_interrupt();
  182. return IRQ_HANDLED;
  183. }
  184. static struct irqaction irq_resched = {
  185. .handler = ipi_resched_interrupt,
  186. .flags = IRQF_PERCPU,
  187. .name = "IPI resched"
  188. };
  189. static struct irqaction irq_call = {
  190. .handler = ipi_call_interrupt,
  191. .flags = IRQF_PERCPU,
  192. .name = "IPI call"
  193. };
  194. static void smp_ipi_init_one(unsigned int virq,
  195. struct irqaction *action)
  196. {
  197. int ret;
  198. irq_set_handler(virq, handle_percpu_irq);
  199. ret = setup_irq(virq, action);
  200. BUG_ON(ret);
  201. }
  202. static unsigned int call_virq, sched_virq;
  203. int mips_smp_ipi_allocate(const struct cpumask *mask)
  204. {
  205. int virq;
  206. struct irq_domain *ipidomain;
  207. struct device_node *node;
  208. node = of_irq_find_parent(of_root);
  209. ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
  210. /*
  211. * Some platforms have half DT setup. So if we found irq node but
  212. * didn't find an ipidomain, try to search for one that is not in the
  213. * DT.
  214. */
  215. if (node && !ipidomain)
  216. ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
  217. /*
  218. * There are systems which only use IPI domains some of the time,
  219. * depending upon configuration we don't know until runtime. An
  220. * example is Malta where we may compile in support for GIC & the
  221. * MT ASE, but run on a system which has multiple VPEs in a single
  222. * core and doesn't include a GIC. Until all IPI implementations
  223. * have been converted to use IPI domains the best we can do here
  224. * is to return & hope some other code sets up the IPIs.
  225. */
  226. if (!ipidomain)
  227. return 0;
  228. virq = irq_reserve_ipi(ipidomain, mask);
  229. BUG_ON(!virq);
  230. if (!call_virq)
  231. call_virq = virq;
  232. virq = irq_reserve_ipi(ipidomain, mask);
  233. BUG_ON(!virq);
  234. if (!sched_virq)
  235. sched_virq = virq;
  236. if (irq_domain_is_ipi_per_cpu(ipidomain)) {
  237. int cpu;
  238. for_each_cpu(cpu, mask) {
  239. smp_ipi_init_one(call_virq + cpu, &irq_call);
  240. smp_ipi_init_one(sched_virq + cpu, &irq_resched);
  241. }
  242. } else {
  243. smp_ipi_init_one(call_virq, &irq_call);
  244. smp_ipi_init_one(sched_virq, &irq_resched);
  245. }
  246. return 0;
  247. }
  248. int mips_smp_ipi_free(const struct cpumask *mask)
  249. {
  250. struct irq_domain *ipidomain;
  251. struct device_node *node;
  252. node = of_irq_find_parent(of_root);
  253. ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
  254. /*
  255. * Some platforms have half DT setup. So if we found irq node but
  256. * didn't find an ipidomain, try to search for one that is not in the
  257. * DT.
  258. */
  259. if (node && !ipidomain)
  260. ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
  261. BUG_ON(!ipidomain);
  262. if (irq_domain_is_ipi_per_cpu(ipidomain)) {
  263. int cpu;
  264. for_each_cpu(cpu, mask) {
  265. remove_irq(call_virq + cpu, &irq_call);
  266. remove_irq(sched_virq + cpu, &irq_resched);
  267. }
  268. }
  269. irq_destroy_ipi(call_virq, mask);
  270. irq_destroy_ipi(sched_virq, mask);
  271. return 0;
  272. }
  273. static int __init mips_smp_ipi_init(void)
  274. {
  275. mips_smp_ipi_allocate(cpu_possible_mask);
  276. call_desc = irq_to_desc(call_virq);
  277. sched_desc = irq_to_desc(sched_virq);
  278. return 0;
  279. }
  280. early_initcall(mips_smp_ipi_init);
  281. #endif
  282. /*
  283. * First C code run on the secondary CPUs after being started up by
  284. * the master.
  285. */
  286. asmlinkage void start_secondary(void)
  287. {
  288. unsigned int cpu;
  289. cpu_probe();
  290. per_cpu_trap_init(false);
  291. mips_clockevent_init();
  292. mp_ops->init_secondary();
  293. cpu_report();
  294. maar_init();
  295. /*
  296. * XXX parity protection should be folded in here when it's converted
  297. * to an option instead of something based on .cputype
  298. */
  299. calibrate_delay();
  300. preempt_disable();
  301. cpu = smp_processor_id();
  302. cpu_data[cpu].udelay_val = loops_per_jiffy;
  303. cpumask_set_cpu(cpu, &cpu_coherent_mask);
  304. notify_cpu_starting(cpu);
  305. /* Notify boot CPU that we're starting & ready to sync counters */
  306. complete(&cpu_starting);
  307. synchronise_count_slave(cpu);
  308. /* The CPU is running and counters synchronised, now mark it online */
  309. set_cpu_online(cpu, true);
  310. set_cpu_sibling_map(cpu);
  311. set_cpu_core_map(cpu);
  312. calculate_cpu_foreign_map();
  313. /*
  314. * Notify boot CPU that we're up & online and it can safely return
  315. * from __cpu_up
  316. */
  317. complete(&cpu_running);
  318. /*
  319. * irq will be enabled in ->smp_finish(), enabling it too early
  320. * is dangerous.
  321. */
  322. WARN_ON_ONCE(!irqs_disabled());
  323. mp_ops->smp_finish();
  324. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  325. }
  326. static void stop_this_cpu(void *dummy)
  327. {
  328. /*
  329. * Remove this CPU:
  330. */
  331. set_cpu_online(smp_processor_id(), false);
  332. calculate_cpu_foreign_map();
  333. local_irq_disable();
  334. while (1);
  335. }
  336. void smp_send_stop(void)
  337. {
  338. smp_call_function(stop_this_cpu, NULL, 0);
  339. }
  340. void __init smp_cpus_done(unsigned int max_cpus)
  341. {
  342. }
  343. /* called from main before smp_init() */
  344. void __init smp_prepare_cpus(unsigned int max_cpus)
  345. {
  346. init_new_context(current, &init_mm);
  347. current_thread_info()->cpu = 0;
  348. mp_ops->prepare_cpus(max_cpus);
  349. set_cpu_sibling_map(0);
  350. set_cpu_core_map(0);
  351. calculate_cpu_foreign_map();
  352. #ifndef CONFIG_HOTPLUG_CPU
  353. init_cpu_present(cpu_possible_mask);
  354. #endif
  355. cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
  356. }
  357. /* preload SMP state for boot cpu */
  358. void smp_prepare_boot_cpu(void)
  359. {
  360. set_cpu_possible(0, true);
  361. set_cpu_online(0, true);
  362. }
  363. int __cpu_up(unsigned int cpu, struct task_struct *tidle)
  364. {
  365. mp_ops->boot_secondary(cpu, tidle);
  366. /* Wait for CPU to start and be ready to sync counters */
  367. if (!wait_for_completion_timeout(&cpu_starting,
  368. msecs_to_jiffies(1000))) {
  369. pr_crit("CPU%u: failed to start\n", cpu);
  370. return -EIO;
  371. }
  372. synchronise_count_master(cpu);
  373. /* Wait for CPU to finish startup & mark itself online before return */
  374. wait_for_completion(&cpu_running);
  375. return 0;
  376. }
  377. /* Not really SMP stuff ... */
  378. int setup_profiling_timer(unsigned int multiplier)
  379. {
  380. return 0;
  381. }
  382. static void flush_tlb_all_ipi(void *info)
  383. {
  384. local_flush_tlb_all();
  385. }
  386. void flush_tlb_all(void)
  387. {
  388. on_each_cpu(flush_tlb_all_ipi, NULL, 1);
  389. }
  390. static void flush_tlb_mm_ipi(void *mm)
  391. {
  392. local_flush_tlb_mm((struct mm_struct *)mm);
  393. }
  394. /*
  395. * Special Variant of smp_call_function for use by TLB functions:
  396. *
  397. * o No return value
  398. * o collapses to normal function call on UP kernels
  399. * o collapses to normal function call on systems with a single shared
  400. * primary cache.
  401. */
  402. static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
  403. {
  404. smp_call_function(func, info, 1);
  405. }
  406. static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
  407. {
  408. preempt_disable();
  409. smp_on_other_tlbs(func, info);
  410. func(info);
  411. preempt_enable();
  412. }
  413. /*
  414. * The following tlb flush calls are invoked when old translations are
  415. * being torn down, or pte attributes are changing. For single threaded
  416. * address spaces, a new context is obtained on the current cpu, and tlb
  417. * context on other cpus are invalidated to force a new context allocation
  418. * at switch_mm time, should the mm ever be used on other cpus. For
  419. * multithreaded address spaces, intercpu interrupts have to be sent.
  420. * Another case where intercpu interrupts are required is when the target
  421. * mm might be active on another cpu (eg debuggers doing the flushes on
  422. * behalf of debugees, kswapd stealing pages from another process etc).
  423. * Kanoj 07/00.
  424. */
  425. void flush_tlb_mm(struct mm_struct *mm)
  426. {
  427. preempt_disable();
  428. if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
  429. smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
  430. } else {
  431. unsigned int cpu;
  432. for_each_online_cpu(cpu) {
  433. if (cpu != smp_processor_id() && cpu_context(cpu, mm))
  434. cpu_context(cpu, mm) = 0;
  435. }
  436. }
  437. local_flush_tlb_mm(mm);
  438. preempt_enable();
  439. }
  440. struct flush_tlb_data {
  441. struct vm_area_struct *vma;
  442. unsigned long addr1;
  443. unsigned long addr2;
  444. };
  445. static void flush_tlb_range_ipi(void *info)
  446. {
  447. struct flush_tlb_data *fd = info;
  448. local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
  449. }
  450. void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
  451. {
  452. struct mm_struct *mm = vma->vm_mm;
  453. preempt_disable();
  454. if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
  455. struct flush_tlb_data fd = {
  456. .vma = vma,
  457. .addr1 = start,
  458. .addr2 = end,
  459. };
  460. smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
  461. } else {
  462. unsigned int cpu;
  463. int exec = vma->vm_flags & VM_EXEC;
  464. for_each_online_cpu(cpu) {
  465. /*
  466. * flush_cache_range() will only fully flush icache if
  467. * the VMA is executable, otherwise we must invalidate
  468. * ASID without it appearing to has_valid_asid() as if
  469. * mm has been completely unused by that CPU.
  470. */
  471. if (cpu != smp_processor_id() && cpu_context(cpu, mm))
  472. cpu_context(cpu, mm) = !exec;
  473. }
  474. }
  475. local_flush_tlb_range(vma, start, end);
  476. preempt_enable();
  477. }
  478. static void flush_tlb_kernel_range_ipi(void *info)
  479. {
  480. struct flush_tlb_data *fd = info;
  481. local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
  482. }
  483. void flush_tlb_kernel_range(unsigned long start, unsigned long end)
  484. {
  485. struct flush_tlb_data fd = {
  486. .addr1 = start,
  487. .addr2 = end,
  488. };
  489. on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
  490. }
  491. static void flush_tlb_page_ipi(void *info)
  492. {
  493. struct flush_tlb_data *fd = info;
  494. local_flush_tlb_page(fd->vma, fd->addr1);
  495. }
  496. void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
  497. {
  498. preempt_disable();
  499. if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
  500. struct flush_tlb_data fd = {
  501. .vma = vma,
  502. .addr1 = page,
  503. };
  504. smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
  505. } else {
  506. unsigned int cpu;
  507. for_each_online_cpu(cpu) {
  508. /*
  509. * flush_cache_page() only does partial flushes, so
  510. * invalidate ASID without it appearing to
  511. * has_valid_asid() as if mm has been completely unused
  512. * by that CPU.
  513. */
  514. if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
  515. cpu_context(cpu, vma->vm_mm) = 1;
  516. }
  517. }
  518. local_flush_tlb_page(vma, page);
  519. preempt_enable();
  520. }
  521. static void flush_tlb_one_ipi(void *info)
  522. {
  523. unsigned long vaddr = (unsigned long) info;
  524. local_flush_tlb_one(vaddr);
  525. }
  526. void flush_tlb_one(unsigned long vaddr)
  527. {
  528. smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
  529. }
  530. EXPORT_SYMBOL(flush_tlb_page);
  531. EXPORT_SYMBOL(flush_tlb_one);
  532. #if defined(CONFIG_KEXEC)
  533. void (*dump_ipi_function_ptr)(void *) = NULL;
  534. void dump_send_ipi(void (*dump_ipi_callback)(void *))
  535. {
  536. int i;
  537. int cpu = smp_processor_id();
  538. dump_ipi_function_ptr = dump_ipi_callback;
  539. smp_mb();
  540. for_each_online_cpu(i)
  541. if (i != cpu)
  542. mp_ops->send_ipi_single(i, SMP_DUMP);
  543. }
  544. EXPORT_SYMBOL(dump_send_ipi);
  545. #endif
  546. #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
  547. static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
  548. static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd);
  549. void tick_broadcast(const struct cpumask *mask)
  550. {
  551. atomic_t *count;
  552. struct call_single_data *csd;
  553. int cpu;
  554. for_each_cpu(cpu, mask) {
  555. count = &per_cpu(tick_broadcast_count, cpu);
  556. csd = &per_cpu(tick_broadcast_csd, cpu);
  557. if (atomic_inc_return(count) == 1)
  558. smp_call_function_single_async(cpu, csd);
  559. }
  560. }
  561. static void tick_broadcast_callee(void *info)
  562. {
  563. int cpu = smp_processor_id();
  564. tick_receive_broadcast();
  565. atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
  566. }
  567. static int __init tick_broadcast_init(void)
  568. {
  569. struct call_single_data *csd;
  570. int cpu;
  571. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  572. csd = &per_cpu(tick_broadcast_csd, cpu);
  573. csd->func = tick_broadcast_callee;
  574. }
  575. return 0;
  576. }
  577. early_initcall(tick_broadcast_init);
  578. #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */