edosk2674.dts 2.1 KB

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  1. /dts-v1/;
  2. / {
  3. compatible = "renesas,edosk2674";
  4. #address-cells = <1>;
  5. #size-cells = <1>;
  6. interrupt-parent = <&h8intc>;
  7. chosen {
  8. bootargs = "console=ttySC2,38400";
  9. stdout-path = &sci2;
  10. };
  11. aliases {
  12. serial0 = &sci0;
  13. serial1 = &sci1;
  14. serial2 = &sci2;
  15. };
  16. xclk: oscillator {
  17. #clock-cells = <0>;
  18. compatible = "fixed-clock";
  19. clock-frequency = <33333333>;
  20. clock-output-names = "xtal";
  21. };
  22. pllclk: pllclk {
  23. compatible = "renesas,h8s2678-pll-clock";
  24. clocks = <&xclk>;
  25. #clock-cells = <0>;
  26. reg = <0xffff3b 1>, <0xffff45 1>;
  27. };
  28. core_clk: core_clk {
  29. compatible = "renesas,h8300-div-clock";
  30. clocks = <&pllclk>;
  31. #clock-cells = <0>;
  32. reg = <0xffff3b 1>;
  33. renesas,width = <3>;
  34. };
  35. fclk: fclk {
  36. compatible = "fixed-factor-clock";
  37. clocks = <&core_clk>;
  38. #clock-cells = <0>;
  39. clock-div = <1>;
  40. clock-mult = <1>;
  41. };
  42. memory@400000 {
  43. device_type = "memory";
  44. reg = <0x400000 0x800000>;
  45. };
  46. cpus {
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. cpu@0 {
  50. compatible = "renesas,h8300";
  51. clock-frequency = <33333333>;
  52. };
  53. };
  54. h8intc: interrupt-controller@fffe00 {
  55. compatible = "renesas,h8s-intc", "renesas,h8300-intc";
  56. #interrupt-cells = <2>;
  57. interrupt-controller;
  58. reg = <0xfffe00 24>;
  59. };
  60. bsc: memory-controller@fffec0 {
  61. compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
  62. reg = <0xfffec0 24>;
  63. };
  64. tpu: timer@ffffe0 {
  65. compatible = "renesas,tpu";
  66. reg = <0xffffe0 16>, <0xfffff0 12>;
  67. clocks = <&fclk>;
  68. clock-names = "fck";
  69. };
  70. timer8: timer@ffffb0 {
  71. compatible = "renesas,8bit-timer";
  72. reg = <0xffffb0 10>;
  73. interrupts = <72 0>;
  74. clocks = <&fclk>;
  75. clock-names = "fck";
  76. };
  77. sci0: serial@ffff78 {
  78. compatible = "renesas,sci";
  79. reg = <0xffff78 8>;
  80. interrupts = <88 0>, <89 0>, <90 0>, <91 0>;
  81. clocks = <&fclk>;
  82. clock-names = "fck";
  83. };
  84. sci1: serial@ffff80 {
  85. compatible = "renesas,sci";
  86. reg = <0xffff80 8>;
  87. interrupts = <92 0>, <93 0>, <94 0>, <95 0>;
  88. clocks = <&fclk>;
  89. clock-names = "fck";
  90. };
  91. sci2: serial@ffff88 {
  92. compatible = "renesas,sci";
  93. reg = <0xffff88 8>;
  94. interrupts = <96 0>, <97 0>, <98 0>, <99 0>;
  95. clocks = <&fclk>;
  96. clock-names = "fck";
  97. };
  98. };