ice1724.c 78 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883
  1. /*
  2. * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
  3. * VIA VT1720 (Envy24PT)
  4. *
  5. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  6. * 2002 James Stafford <jstafford@ampltd.com>
  7. * 2003 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/delay.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/init.h>
  27. #include <linux/pci.h>
  28. #include <linux/slab.h>
  29. #include <linux/module.h>
  30. #include <linux/mutex.h>
  31. #include <sound/core.h>
  32. #include <sound/info.h>
  33. #include <sound/rawmidi.h>
  34. #include <sound/initval.h>
  35. #include <sound/asoundef.h>
  36. #include "ice1712.h"
  37. #include "envy24ht.h"
  38. /* lowlevel routines */
  39. #include "amp.h"
  40. #include "revo.h"
  41. #include "aureon.h"
  42. #include "vt1720_mobo.h"
  43. #include "pontis.h"
  44. #include "prodigy192.h"
  45. #include "prodigy_hifi.h"
  46. #include "juli.h"
  47. #include "maya44.h"
  48. #include "phase.h"
  49. #include "wtm.h"
  50. #include "se.h"
  51. #include "quartet.h"
  52. #include "psc724.h"
  53. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  54. MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
  55. MODULE_LICENSE("GPL");
  56. MODULE_SUPPORTED_DEVICE("{"
  57. REVO_DEVICE_DESC
  58. AMP_AUDIO2000_DEVICE_DESC
  59. AUREON_DEVICE_DESC
  60. VT1720_MOBO_DEVICE_DESC
  61. PONTIS_DEVICE_DESC
  62. PRODIGY192_DEVICE_DESC
  63. PRODIGY_HIFI_DEVICE_DESC
  64. JULI_DEVICE_DESC
  65. MAYA44_DEVICE_DESC
  66. PHASE_DEVICE_DESC
  67. WTM_DEVICE_DESC
  68. SE_DEVICE_DESC
  69. QTET_DEVICE_DESC
  70. "{VIA,VT1720},"
  71. "{VIA,VT1724},"
  72. "{ICEnsemble,Generic ICE1724},"
  73. "{ICEnsemble,Generic Envy24HT}"
  74. "{ICEnsemble,Generic Envy24PT}}");
  75. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  76. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  77. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  78. static char *model[SNDRV_CARDS];
  79. module_param_array(index, int, NULL, 0444);
  80. MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
  81. module_param_array(id, charp, NULL, 0444);
  82. MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
  83. module_param_array(enable, bool, NULL, 0444);
  84. MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
  85. module_param_array(model, charp, NULL, 0444);
  86. MODULE_PARM_DESC(model, "Use the given board model.");
  87. /* Both VT1720 and VT1724 have the same PCI IDs */
  88. static const struct pci_device_id snd_vt1724_ids[] = {
  89. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
  90. { 0, }
  91. };
  92. MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
  93. static int PRO_RATE_LOCKED;
  94. static int PRO_RATE_RESET = 1;
  95. static unsigned int PRO_RATE_DEFAULT = 44100;
  96. static const char * const ext_clock_names[1] = { "IEC958 In" };
  97. /*
  98. * Basic I/O
  99. */
  100. /*
  101. * default rates, default clock routines
  102. */
  103. /* check whether the clock mode is spdif-in */
  104. static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
  105. {
  106. return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
  107. }
  108. /*
  109. * locking rate makes sense only for internal clock mode
  110. */
  111. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  112. {
  113. return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
  114. }
  115. /*
  116. * ac97 section
  117. */
  118. static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
  119. {
  120. unsigned char old_cmd;
  121. int tm;
  122. for (tm = 0; tm < 0x10000; tm++) {
  123. old_cmd = inb(ICEMT1724(ice, AC97_CMD));
  124. if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
  125. continue;
  126. if (!(old_cmd & VT1724_AC97_READY))
  127. continue;
  128. return old_cmd;
  129. }
  130. dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
  131. return old_cmd;
  132. }
  133. static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
  134. {
  135. int tm;
  136. for (tm = 0; tm < 0x10000; tm++)
  137. if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
  138. return 0;
  139. dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
  140. return -EIO;
  141. }
  142. static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
  143. unsigned short reg,
  144. unsigned short val)
  145. {
  146. struct snd_ice1712 *ice = ac97->private_data;
  147. unsigned char old_cmd;
  148. old_cmd = snd_vt1724_ac97_ready(ice);
  149. old_cmd &= ~VT1724_AC97_ID_MASK;
  150. old_cmd |= ac97->num;
  151. outb(reg, ICEMT1724(ice, AC97_INDEX));
  152. outw(val, ICEMT1724(ice, AC97_DATA));
  153. outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
  154. snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
  155. }
  156. static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  157. {
  158. struct snd_ice1712 *ice = ac97->private_data;
  159. unsigned char old_cmd;
  160. old_cmd = snd_vt1724_ac97_ready(ice);
  161. old_cmd &= ~VT1724_AC97_ID_MASK;
  162. old_cmd |= ac97->num;
  163. outb(reg, ICEMT1724(ice, AC97_INDEX));
  164. outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
  165. if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
  166. return ~0;
  167. return inw(ICEMT1724(ice, AC97_DATA));
  168. }
  169. /*
  170. * GPIO operations
  171. */
  172. /* set gpio direction 0 = read, 1 = write */
  173. static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  174. {
  175. outl(data, ICEREG1724(ice, GPIO_DIRECTION));
  176. inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
  177. }
  178. /* get gpio direction 0 = read, 1 = write */
  179. static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
  180. {
  181. return inl(ICEREG1724(ice, GPIO_DIRECTION));
  182. }
  183. /* set the gpio mask (0 = writable) */
  184. static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  185. {
  186. outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
  187. if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
  188. outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
  189. inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
  190. }
  191. static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
  192. {
  193. unsigned int mask;
  194. if (!ice->vt1720)
  195. mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
  196. else
  197. mask = 0;
  198. mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
  199. return mask;
  200. }
  201. static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
  202. {
  203. outw(data, ICEREG1724(ice, GPIO_DATA));
  204. if (!ice->vt1720)
  205. outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
  206. inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
  207. }
  208. static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
  209. {
  210. unsigned int data;
  211. if (!ice->vt1720)
  212. data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
  213. else
  214. data = 0;
  215. data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
  216. return data;
  217. }
  218. /*
  219. * MIDI
  220. */
  221. static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
  222. {
  223. unsigned int count;
  224. for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
  225. inb(ICEREG1724(ice, MPU_DATA));
  226. }
  227. static inline struct snd_rawmidi_substream *
  228. get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
  229. {
  230. return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
  231. struct snd_rawmidi_substream, list);
  232. }
  233. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
  234. static void vt1724_midi_write(struct snd_ice1712 *ice)
  235. {
  236. struct snd_rawmidi_substream *s;
  237. int count, i;
  238. u8 buffer[32];
  239. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
  240. count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
  241. if (count > 0) {
  242. count = snd_rawmidi_transmit(s, buffer, count);
  243. for (i = 0; i < count; ++i)
  244. outb(buffer[i], ICEREG1724(ice, MPU_DATA));
  245. }
  246. /* mask irq when all bytes have been transmitted.
  247. * enabled again in output_trigger when the new data comes in.
  248. */
  249. enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
  250. !snd_rawmidi_transmit_empty(s));
  251. }
  252. static void vt1724_midi_read(struct snd_ice1712 *ice)
  253. {
  254. struct snd_rawmidi_substream *s;
  255. int count, i;
  256. u8 buffer[32];
  257. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
  258. count = inb(ICEREG1724(ice, MPU_RXFIFO));
  259. if (count > 0) {
  260. count = min(count, 32);
  261. for (i = 0; i < count; ++i)
  262. buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
  263. snd_rawmidi_receive(s, buffer, count);
  264. }
  265. }
  266. /* call with ice->reg_lock */
  267. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
  268. {
  269. u8 mask = inb(ICEREG1724(ice, IRQMASK));
  270. if (enable)
  271. mask &= ~flag;
  272. else
  273. mask |= flag;
  274. outb(mask, ICEREG1724(ice, IRQMASK));
  275. }
  276. static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
  277. u8 flag, int enable)
  278. {
  279. struct snd_ice1712 *ice = substream->rmidi->private_data;
  280. spin_lock_irq(&ice->reg_lock);
  281. enable_midi_irq(ice, flag, enable);
  282. spin_unlock_irq(&ice->reg_lock);
  283. }
  284. static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
  285. {
  286. return 0;
  287. }
  288. static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
  289. {
  290. return 0;
  291. }
  292. static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
  293. {
  294. struct snd_ice1712 *ice = s->rmidi->private_data;
  295. unsigned long flags;
  296. spin_lock_irqsave(&ice->reg_lock, flags);
  297. if (up) {
  298. ice->midi_output = 1;
  299. vt1724_midi_write(ice);
  300. } else {
  301. ice->midi_output = 0;
  302. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  303. }
  304. spin_unlock_irqrestore(&ice->reg_lock, flags);
  305. }
  306. static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
  307. {
  308. struct snd_ice1712 *ice = s->rmidi->private_data;
  309. unsigned long timeout;
  310. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
  311. /* 32 bytes should be transmitted in less than about 12 ms */
  312. timeout = jiffies + msecs_to_jiffies(15);
  313. do {
  314. if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
  315. break;
  316. schedule_timeout_uninterruptible(1);
  317. } while (time_after(timeout, jiffies));
  318. }
  319. static struct snd_rawmidi_ops vt1724_midi_output_ops = {
  320. .open = vt1724_midi_output_open,
  321. .close = vt1724_midi_output_close,
  322. .trigger = vt1724_midi_output_trigger,
  323. .drain = vt1724_midi_output_drain,
  324. };
  325. static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
  326. {
  327. vt1724_midi_clear_rx(s->rmidi->private_data);
  328. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
  329. return 0;
  330. }
  331. static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
  332. {
  333. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
  334. return 0;
  335. }
  336. static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
  337. {
  338. struct snd_ice1712 *ice = s->rmidi->private_data;
  339. unsigned long flags;
  340. spin_lock_irqsave(&ice->reg_lock, flags);
  341. if (up) {
  342. ice->midi_input = 1;
  343. vt1724_midi_read(ice);
  344. } else {
  345. ice->midi_input = 0;
  346. }
  347. spin_unlock_irqrestore(&ice->reg_lock, flags);
  348. }
  349. static struct snd_rawmidi_ops vt1724_midi_input_ops = {
  350. .open = vt1724_midi_input_open,
  351. .close = vt1724_midi_input_close,
  352. .trigger = vt1724_midi_input_trigger,
  353. };
  354. /*
  355. * Interrupt handler
  356. */
  357. static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
  358. {
  359. struct snd_ice1712 *ice = dev_id;
  360. unsigned char status;
  361. unsigned char status_mask =
  362. VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
  363. int handled = 0;
  364. int timeout = 0;
  365. while (1) {
  366. status = inb(ICEREG1724(ice, IRQSTAT));
  367. status &= status_mask;
  368. if (status == 0)
  369. break;
  370. spin_lock(&ice->reg_lock);
  371. if (++timeout > 10) {
  372. status = inb(ICEREG1724(ice, IRQSTAT));
  373. dev_err(ice->card->dev,
  374. "Too long irq loop, status = 0x%x\n", status);
  375. if (status & VT1724_IRQ_MPU_TX) {
  376. dev_err(ice->card->dev, "Disabling MPU_TX\n");
  377. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  378. }
  379. spin_unlock(&ice->reg_lock);
  380. break;
  381. }
  382. handled = 1;
  383. if (status & VT1724_IRQ_MPU_TX) {
  384. if (ice->midi_output)
  385. vt1724_midi_write(ice);
  386. else
  387. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  388. /* Due to mysterical reasons, MPU_TX is always
  389. * generated (and can't be cleared) when a PCM
  390. * playback is going. So let's ignore at the
  391. * next loop.
  392. */
  393. status_mask &= ~VT1724_IRQ_MPU_TX;
  394. }
  395. if (status & VT1724_IRQ_MPU_RX) {
  396. if (ice->midi_input)
  397. vt1724_midi_read(ice);
  398. else
  399. vt1724_midi_clear_rx(ice);
  400. }
  401. /* ack MPU irq */
  402. outb(status, ICEREG1724(ice, IRQSTAT));
  403. spin_unlock(&ice->reg_lock);
  404. if (status & VT1724_IRQ_MTPCM) {
  405. /*
  406. * Multi-track PCM
  407. * PCM assignment are:
  408. * Playback DMA0 (M/C) = playback_pro_substream
  409. * Playback DMA1 = playback_con_substream_ds[0]
  410. * Playback DMA2 = playback_con_substream_ds[1]
  411. * Playback DMA3 = playback_con_substream_ds[2]
  412. * Playback DMA4 (SPDIF) = playback_con_substream
  413. * Record DMA0 = capture_pro_substream
  414. * Record DMA1 = capture_con_substream
  415. */
  416. unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
  417. if (mtstat & VT1724_MULTI_PDMA0) {
  418. if (ice->playback_pro_substream)
  419. snd_pcm_period_elapsed(ice->playback_pro_substream);
  420. }
  421. if (mtstat & VT1724_MULTI_RDMA0) {
  422. if (ice->capture_pro_substream)
  423. snd_pcm_period_elapsed(ice->capture_pro_substream);
  424. }
  425. if (mtstat & VT1724_MULTI_PDMA1) {
  426. if (ice->playback_con_substream_ds[0])
  427. snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
  428. }
  429. if (mtstat & VT1724_MULTI_PDMA2) {
  430. if (ice->playback_con_substream_ds[1])
  431. snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
  432. }
  433. if (mtstat & VT1724_MULTI_PDMA3) {
  434. if (ice->playback_con_substream_ds[2])
  435. snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
  436. }
  437. if (mtstat & VT1724_MULTI_PDMA4) {
  438. if (ice->playback_con_substream)
  439. snd_pcm_period_elapsed(ice->playback_con_substream);
  440. }
  441. if (mtstat & VT1724_MULTI_RDMA1) {
  442. if (ice->capture_con_substream)
  443. snd_pcm_period_elapsed(ice->capture_con_substream);
  444. }
  445. /* ack anyway to avoid freeze */
  446. outb(mtstat, ICEMT1724(ice, IRQ));
  447. /* ought to really handle this properly */
  448. if (mtstat & VT1724_MULTI_FIFO_ERR) {
  449. unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
  450. outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
  451. outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
  452. /* If I don't do this, I get machine lockup due to continual interrupts */
  453. }
  454. }
  455. }
  456. return IRQ_RETVAL(handled);
  457. }
  458. /*
  459. * PCM code - professional part (multitrack)
  460. */
  461. static unsigned int rates[] = {
  462. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  463. 32000, 44100, 48000, 64000, 88200, 96000,
  464. 176400, 192000,
  465. };
  466. static struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
  467. .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
  468. .list = rates,
  469. .mask = 0,
  470. };
  471. static struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
  472. .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
  473. .list = rates,
  474. .mask = 0,
  475. };
  476. static struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
  477. .count = ARRAY_SIZE(rates),
  478. .list = rates,
  479. .mask = 0,
  480. };
  481. struct vt1724_pcm_reg {
  482. unsigned int addr; /* ADDR register offset */
  483. unsigned int size; /* SIZE register offset */
  484. unsigned int count; /* COUNT register offset */
  485. unsigned int start; /* start & pause bit */
  486. };
  487. static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  488. {
  489. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  490. unsigned char what;
  491. unsigned char old;
  492. struct snd_pcm_substream *s;
  493. what = 0;
  494. snd_pcm_group_for_each_entry(s, substream) {
  495. if (snd_pcm_substream_chip(s) == ice) {
  496. const struct vt1724_pcm_reg *reg;
  497. reg = s->runtime->private_data;
  498. what |= reg->start;
  499. snd_pcm_trigger_done(s, substream);
  500. }
  501. }
  502. switch (cmd) {
  503. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  504. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  505. spin_lock(&ice->reg_lock);
  506. old = inb(ICEMT1724(ice, DMA_PAUSE));
  507. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  508. old |= what;
  509. else
  510. old &= ~what;
  511. outb(old, ICEMT1724(ice, DMA_PAUSE));
  512. spin_unlock(&ice->reg_lock);
  513. break;
  514. case SNDRV_PCM_TRIGGER_START:
  515. case SNDRV_PCM_TRIGGER_STOP:
  516. case SNDRV_PCM_TRIGGER_SUSPEND:
  517. spin_lock(&ice->reg_lock);
  518. old = inb(ICEMT1724(ice, DMA_CONTROL));
  519. if (cmd == SNDRV_PCM_TRIGGER_START)
  520. old |= what;
  521. else
  522. old &= ~what;
  523. outb(old, ICEMT1724(ice, DMA_CONTROL));
  524. spin_unlock(&ice->reg_lock);
  525. break;
  526. case SNDRV_PCM_TRIGGER_RESUME:
  527. /* apps will have to restart stream */
  528. break;
  529. default:
  530. return -EINVAL;
  531. }
  532. return 0;
  533. }
  534. /*
  535. */
  536. #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
  537. VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
  538. #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
  539. VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
  540. static const unsigned int stdclock_rate_list[16] = {
  541. 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
  542. 22050, 11025, 88200, 176400, 0, 192000, 64000
  543. };
  544. static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
  545. {
  546. return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
  547. }
  548. static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
  549. {
  550. int i;
  551. for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
  552. if (stdclock_rate_list[i] == rate) {
  553. outb(i, ICEMT1724(ice, RATE));
  554. return;
  555. }
  556. }
  557. }
  558. static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
  559. unsigned int rate)
  560. {
  561. unsigned char val, old;
  562. /* check MT02 */
  563. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  564. val = old = inb(ICEMT1724(ice, I2S_FORMAT));
  565. if (rate > 96000)
  566. val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
  567. else
  568. val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
  569. if (val != old) {
  570. outb(val, ICEMT1724(ice, I2S_FORMAT));
  571. /* master clock changed */
  572. return 1;
  573. }
  574. }
  575. /* no change in master clock */
  576. return 0;
  577. }
  578. static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
  579. int force)
  580. {
  581. unsigned long flags;
  582. unsigned char mclk_change;
  583. unsigned int i, old_rate;
  584. if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
  585. return -EINVAL;
  586. spin_lock_irqsave(&ice->reg_lock, flags);
  587. if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
  588. (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
  589. /* running? we cannot change the rate now... */
  590. spin_unlock_irqrestore(&ice->reg_lock, flags);
  591. return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
  592. }
  593. if (!force && is_pro_rate_locked(ice)) {
  594. /* comparing required and current rate - makes sense for
  595. * internal clock only */
  596. spin_unlock_irqrestore(&ice->reg_lock, flags);
  597. return (rate == ice->cur_rate) ? 0 : -EBUSY;
  598. }
  599. if (force || !ice->is_spdif_master(ice)) {
  600. /* force means the rate was switched by ucontrol, otherwise
  601. * setting clock rate for internal clock mode */
  602. old_rate = ice->get_rate(ice);
  603. if (force || (old_rate != rate))
  604. ice->set_rate(ice, rate);
  605. else if (rate == ice->cur_rate) {
  606. spin_unlock_irqrestore(&ice->reg_lock, flags);
  607. return 0;
  608. }
  609. }
  610. ice->cur_rate = rate;
  611. /* setting master clock */
  612. mclk_change = ice->set_mclk(ice, rate);
  613. spin_unlock_irqrestore(&ice->reg_lock, flags);
  614. if (mclk_change && ice->gpio.i2s_mclk_changed)
  615. ice->gpio.i2s_mclk_changed(ice);
  616. if (ice->gpio.set_pro_rate)
  617. ice->gpio.set_pro_rate(ice, rate);
  618. /* set up codecs */
  619. for (i = 0; i < ice->akm_codecs; i++) {
  620. if (ice->akm[i].ops.set_rate_val)
  621. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  622. }
  623. if (ice->spdif.ops.setup_rate)
  624. ice->spdif.ops.setup_rate(ice, rate);
  625. return 0;
  626. }
  627. static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
  628. struct snd_pcm_hw_params *hw_params)
  629. {
  630. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  631. int i, chs, err;
  632. chs = params_channels(hw_params);
  633. mutex_lock(&ice->open_mutex);
  634. /* mark surround channels */
  635. if (substream == ice->playback_pro_substream) {
  636. /* PDMA0 can be multi-channel up to 8 */
  637. chs = chs / 2 - 1;
  638. for (i = 0; i < chs; i++) {
  639. if (ice->pcm_reserved[i] &&
  640. ice->pcm_reserved[i] != substream) {
  641. mutex_unlock(&ice->open_mutex);
  642. return -EBUSY;
  643. }
  644. ice->pcm_reserved[i] = substream;
  645. }
  646. for (; i < 3; i++) {
  647. if (ice->pcm_reserved[i] == substream)
  648. ice->pcm_reserved[i] = NULL;
  649. }
  650. } else {
  651. for (i = 0; i < 3; i++) {
  652. /* check individual playback stream */
  653. if (ice->playback_con_substream_ds[i] == substream) {
  654. if (ice->pcm_reserved[i] &&
  655. ice->pcm_reserved[i] != substream) {
  656. mutex_unlock(&ice->open_mutex);
  657. return -EBUSY;
  658. }
  659. ice->pcm_reserved[i] = substream;
  660. break;
  661. }
  662. }
  663. }
  664. mutex_unlock(&ice->open_mutex);
  665. err = snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
  666. if (err < 0)
  667. return err;
  668. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  669. }
  670. static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
  671. {
  672. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  673. int i;
  674. mutex_lock(&ice->open_mutex);
  675. /* unmark surround channels */
  676. for (i = 0; i < 3; i++)
  677. if (ice->pcm_reserved[i] == substream)
  678. ice->pcm_reserved[i] = NULL;
  679. mutex_unlock(&ice->open_mutex);
  680. return snd_pcm_lib_free_pages(substream);
  681. }
  682. static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
  683. {
  684. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  685. unsigned char val;
  686. unsigned int size;
  687. spin_lock_irq(&ice->reg_lock);
  688. val = (8 - substream->runtime->channels) >> 1;
  689. outb(val, ICEMT1724(ice, BURST));
  690. outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
  691. size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
  692. /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
  693. outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
  694. outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
  695. size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  696. /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
  697. outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
  698. outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
  699. spin_unlock_irq(&ice->reg_lock);
  700. /*
  701. dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
  702. "buffer = 0x%x, period = 0x%x\n",
  703. substream->runtime->channels,
  704. (unsigned int)substream->runtime->dma_addr,
  705. snd_pcm_lib_buffer_bytes(substream),
  706. snd_pcm_lib_period_bytes(substream));
  707. */
  708. return 0;
  709. }
  710. static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
  711. {
  712. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  713. size_t ptr;
  714. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
  715. return 0;
  716. #if 0 /* read PLAYBACK_ADDR */
  717. ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
  718. if (ptr < substream->runtime->dma_addr) {
  719. dev_dbg(ice->card->dev, "invalid negative ptr\n");
  720. return 0;
  721. }
  722. ptr -= substream->runtime->dma_addr;
  723. ptr = bytes_to_frames(substream->runtime, ptr);
  724. if (ptr >= substream->runtime->buffer_size) {
  725. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  726. (int)ptr, (int)substream->runtime->period_size);
  727. return 0;
  728. }
  729. #else /* read PLAYBACK_SIZE */
  730. ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
  731. ptr = (ptr + 1) << 2;
  732. ptr = bytes_to_frames(substream->runtime, ptr);
  733. if (!ptr)
  734. ;
  735. else if (ptr <= substream->runtime->buffer_size)
  736. ptr = substream->runtime->buffer_size - ptr;
  737. else {
  738. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  739. (int)ptr, (int)substream->runtime->buffer_size);
  740. ptr = 0;
  741. }
  742. #endif
  743. return ptr;
  744. }
  745. static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
  746. {
  747. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  748. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  749. spin_lock_irq(&ice->reg_lock);
  750. outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
  751. outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
  752. ice->profi_port + reg->size);
  753. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
  754. ice->profi_port + reg->count);
  755. spin_unlock_irq(&ice->reg_lock);
  756. return 0;
  757. }
  758. static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
  759. {
  760. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  761. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  762. size_t ptr;
  763. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
  764. return 0;
  765. #if 0 /* use ADDR register */
  766. ptr = inl(ice->profi_port + reg->addr);
  767. ptr -= substream->runtime->dma_addr;
  768. return bytes_to_frames(substream->runtime, ptr);
  769. #else /* use SIZE register */
  770. ptr = inw(ice->profi_port + reg->size);
  771. ptr = (ptr + 1) << 2;
  772. ptr = bytes_to_frames(substream->runtime, ptr);
  773. if (!ptr)
  774. ;
  775. else if (ptr <= substream->runtime->buffer_size)
  776. ptr = substream->runtime->buffer_size - ptr;
  777. else {
  778. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  779. (int)ptr, (int)substream->runtime->buffer_size);
  780. ptr = 0;
  781. }
  782. return ptr;
  783. #endif
  784. }
  785. static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
  786. .addr = VT1724_MT_PLAYBACK_ADDR,
  787. .size = VT1724_MT_PLAYBACK_SIZE,
  788. .count = VT1724_MT_PLAYBACK_COUNT,
  789. .start = VT1724_PDMA0_START,
  790. };
  791. static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
  792. .addr = VT1724_MT_PDMA4_ADDR,
  793. .size = VT1724_MT_PDMA4_SIZE,
  794. .count = VT1724_MT_PDMA4_COUNT,
  795. .start = VT1724_PDMA4_START,
  796. };
  797. static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
  798. .addr = VT1724_MT_CAPTURE_ADDR,
  799. .size = VT1724_MT_CAPTURE_SIZE,
  800. .count = VT1724_MT_CAPTURE_COUNT,
  801. .start = VT1724_RDMA0_START,
  802. };
  803. static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
  804. .addr = VT1724_MT_RDMA1_ADDR,
  805. .size = VT1724_MT_RDMA1_SIZE,
  806. .count = VT1724_MT_RDMA1_COUNT,
  807. .start = VT1724_RDMA1_START,
  808. };
  809. #define vt1724_playback_pro_reg vt1724_pdma0_reg
  810. #define vt1724_playback_spdif_reg vt1724_pdma4_reg
  811. #define vt1724_capture_pro_reg vt1724_rdma0_reg
  812. #define vt1724_capture_spdif_reg vt1724_rdma1_reg
  813. static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
  814. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  815. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  816. SNDRV_PCM_INFO_MMAP_VALID |
  817. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  818. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  819. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  820. .rate_min = 8000,
  821. .rate_max = 192000,
  822. .channels_min = 2,
  823. .channels_max = 8,
  824. .buffer_bytes_max = (1UL << 21), /* 19bits dword */
  825. .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
  826. .period_bytes_max = (1UL << 21),
  827. .periods_min = 2,
  828. .periods_max = 1024,
  829. };
  830. static const struct snd_pcm_hardware snd_vt1724_spdif = {
  831. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  832. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  833. SNDRV_PCM_INFO_MMAP_VALID |
  834. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  835. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  836. .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
  837. SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
  838. SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
  839. SNDRV_PCM_RATE_192000),
  840. .rate_min = 32000,
  841. .rate_max = 192000,
  842. .channels_min = 2,
  843. .channels_max = 2,
  844. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  845. .period_bytes_min = 2 * 4 * 2,
  846. .period_bytes_max = (1UL << 18),
  847. .periods_min = 2,
  848. .periods_max = 1024,
  849. };
  850. static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
  851. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  852. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  853. SNDRV_PCM_INFO_MMAP_VALID |
  854. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  855. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  856. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  857. .rate_min = 8000,
  858. .rate_max = 192000,
  859. .channels_min = 2,
  860. .channels_max = 2,
  861. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  862. .period_bytes_min = 2 * 4 * 2,
  863. .period_bytes_max = (1UL << 18),
  864. .periods_min = 2,
  865. .periods_max = 1024,
  866. };
  867. /*
  868. * set rate constraints
  869. */
  870. static void set_std_hw_rates(struct snd_ice1712 *ice)
  871. {
  872. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  873. /* I2S */
  874. /* VT1720 doesn't support more than 96kHz */
  875. if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
  876. ice->hw_rates = &hw_constraints_rates_192;
  877. else
  878. ice->hw_rates = &hw_constraints_rates_96;
  879. } else {
  880. /* ACLINK */
  881. ice->hw_rates = &hw_constraints_rates_48;
  882. }
  883. }
  884. static int set_rate_constraints(struct snd_ice1712 *ice,
  885. struct snd_pcm_substream *substream)
  886. {
  887. struct snd_pcm_runtime *runtime = substream->runtime;
  888. runtime->hw.rate_min = ice->hw_rates->list[0];
  889. runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
  890. runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
  891. return snd_pcm_hw_constraint_list(runtime, 0,
  892. SNDRV_PCM_HW_PARAM_RATE,
  893. ice->hw_rates);
  894. }
  895. /* if the card has the internal rate locked (is_pro_locked), limit runtime
  896. hw rates to the current internal rate only.
  897. */
  898. static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
  899. {
  900. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  901. struct snd_pcm_runtime *runtime = substream->runtime;
  902. unsigned int rate;
  903. if (is_pro_rate_locked(ice)) {
  904. rate = ice->get_rate(ice);
  905. if (rate >= runtime->hw.rate_min
  906. && rate <= runtime->hw.rate_max) {
  907. runtime->hw.rate_min = rate;
  908. runtime->hw.rate_max = rate;
  909. }
  910. }
  911. }
  912. /* multi-channel playback needs alignment 8x32bit regardless of the channels
  913. * actually used
  914. */
  915. #define VT1724_BUFFER_ALIGN 0x20
  916. static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
  917. {
  918. struct snd_pcm_runtime *runtime = substream->runtime;
  919. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  920. int chs, num_indeps;
  921. runtime->private_data = (void *)&vt1724_playback_pro_reg;
  922. ice->playback_pro_substream = substream;
  923. runtime->hw = snd_vt1724_playback_pro;
  924. snd_pcm_set_sync(substream);
  925. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  926. set_rate_constraints(ice, substream);
  927. mutex_lock(&ice->open_mutex);
  928. /* calculate the currently available channels */
  929. num_indeps = ice->num_total_dacs / 2 - 1;
  930. for (chs = 0; chs < num_indeps; chs++) {
  931. if (ice->pcm_reserved[chs])
  932. break;
  933. }
  934. chs = (chs + 1) * 2;
  935. runtime->hw.channels_max = chs;
  936. if (chs > 2) /* channels must be even */
  937. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  938. mutex_unlock(&ice->open_mutex);
  939. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  940. VT1724_BUFFER_ALIGN);
  941. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  942. VT1724_BUFFER_ALIGN);
  943. constrain_rate_if_locked(substream);
  944. if (ice->pro_open)
  945. ice->pro_open(ice, substream);
  946. return 0;
  947. }
  948. static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
  949. {
  950. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  951. struct snd_pcm_runtime *runtime = substream->runtime;
  952. runtime->private_data = (void *)&vt1724_capture_pro_reg;
  953. ice->capture_pro_substream = substream;
  954. runtime->hw = snd_vt1724_2ch_stereo;
  955. snd_pcm_set_sync(substream);
  956. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  957. set_rate_constraints(ice, substream);
  958. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  959. VT1724_BUFFER_ALIGN);
  960. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  961. VT1724_BUFFER_ALIGN);
  962. constrain_rate_if_locked(substream);
  963. if (ice->pro_open)
  964. ice->pro_open(ice, substream);
  965. return 0;
  966. }
  967. static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
  968. {
  969. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  970. if (PRO_RATE_RESET)
  971. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  972. ice->playback_pro_substream = NULL;
  973. return 0;
  974. }
  975. static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
  976. {
  977. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  978. if (PRO_RATE_RESET)
  979. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  980. ice->capture_pro_substream = NULL;
  981. return 0;
  982. }
  983. static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
  984. .open = snd_vt1724_playback_pro_open,
  985. .close = snd_vt1724_playback_pro_close,
  986. .ioctl = snd_pcm_lib_ioctl,
  987. .hw_params = snd_vt1724_pcm_hw_params,
  988. .hw_free = snd_vt1724_pcm_hw_free,
  989. .prepare = snd_vt1724_playback_pro_prepare,
  990. .trigger = snd_vt1724_pcm_trigger,
  991. .pointer = snd_vt1724_playback_pro_pointer,
  992. };
  993. static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
  994. .open = snd_vt1724_capture_pro_open,
  995. .close = snd_vt1724_capture_pro_close,
  996. .ioctl = snd_pcm_lib_ioctl,
  997. .hw_params = snd_vt1724_pcm_hw_params,
  998. .hw_free = snd_vt1724_pcm_hw_free,
  999. .prepare = snd_vt1724_pcm_prepare,
  1000. .trigger = snd_vt1724_pcm_trigger,
  1001. .pointer = snd_vt1724_pcm_pointer,
  1002. };
  1003. static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
  1004. {
  1005. struct snd_pcm *pcm;
  1006. int capt, err;
  1007. if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
  1008. VT1724_CFG_ADC_NONE)
  1009. capt = 0;
  1010. else
  1011. capt = 1;
  1012. err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
  1013. if (err < 0)
  1014. return err;
  1015. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
  1016. if (capt)
  1017. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1018. &snd_vt1724_capture_pro_ops);
  1019. pcm->private_data = ice;
  1020. pcm->info_flags = 0;
  1021. strcpy(pcm->name, "ICE1724");
  1022. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1023. snd_dma_pci_data(ice->pci),
  1024. 256*1024, 256*1024);
  1025. ice->pcm_pro = pcm;
  1026. return 0;
  1027. }
  1028. /*
  1029. * SPDIF PCM
  1030. */
  1031. /* update spdif control bits; call with reg_lock */
  1032. static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
  1033. {
  1034. unsigned char cbit, disabled;
  1035. cbit = inb(ICEREG1724(ice, SPDIF_CFG));
  1036. disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
  1037. if (cbit != disabled)
  1038. outb(disabled, ICEREG1724(ice, SPDIF_CFG));
  1039. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1040. if (cbit != disabled)
  1041. outb(cbit, ICEREG1724(ice, SPDIF_CFG));
  1042. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1043. }
  1044. /* update SPDIF control bits according to the given rate */
  1045. static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
  1046. {
  1047. unsigned int val, nval;
  1048. unsigned long flags;
  1049. spin_lock_irqsave(&ice->reg_lock, flags);
  1050. nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1051. nval &= ~(7 << 12);
  1052. switch (rate) {
  1053. case 44100: break;
  1054. case 48000: nval |= 2 << 12; break;
  1055. case 32000: nval |= 3 << 12; break;
  1056. case 88200: nval |= 4 << 12; break;
  1057. case 96000: nval |= 5 << 12; break;
  1058. case 192000: nval |= 6 << 12; break;
  1059. case 176400: nval |= 7 << 12; break;
  1060. }
  1061. if (val != nval)
  1062. update_spdif_bits(ice, nval);
  1063. spin_unlock_irqrestore(&ice->reg_lock, flags);
  1064. }
  1065. static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
  1066. {
  1067. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1068. if (!ice->force_pdma4)
  1069. update_spdif_rate(ice, substream->runtime->rate);
  1070. return snd_vt1724_pcm_prepare(substream);
  1071. }
  1072. static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
  1073. {
  1074. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1075. struct snd_pcm_runtime *runtime = substream->runtime;
  1076. runtime->private_data = (void *)&vt1724_playback_spdif_reg;
  1077. ice->playback_con_substream = substream;
  1078. if (ice->force_pdma4) {
  1079. runtime->hw = snd_vt1724_2ch_stereo;
  1080. set_rate_constraints(ice, substream);
  1081. } else
  1082. runtime->hw = snd_vt1724_spdif;
  1083. snd_pcm_set_sync(substream);
  1084. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1085. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1086. VT1724_BUFFER_ALIGN);
  1087. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1088. VT1724_BUFFER_ALIGN);
  1089. constrain_rate_if_locked(substream);
  1090. if (ice->spdif.ops.open)
  1091. ice->spdif.ops.open(ice, substream);
  1092. return 0;
  1093. }
  1094. static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
  1095. {
  1096. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1097. if (PRO_RATE_RESET)
  1098. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1099. ice->playback_con_substream = NULL;
  1100. if (ice->spdif.ops.close)
  1101. ice->spdif.ops.close(ice, substream);
  1102. return 0;
  1103. }
  1104. static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
  1105. {
  1106. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1107. struct snd_pcm_runtime *runtime = substream->runtime;
  1108. runtime->private_data = (void *)&vt1724_capture_spdif_reg;
  1109. ice->capture_con_substream = substream;
  1110. if (ice->force_rdma1) {
  1111. runtime->hw = snd_vt1724_2ch_stereo;
  1112. set_rate_constraints(ice, substream);
  1113. } else
  1114. runtime->hw = snd_vt1724_spdif;
  1115. snd_pcm_set_sync(substream);
  1116. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1117. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1118. VT1724_BUFFER_ALIGN);
  1119. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1120. VT1724_BUFFER_ALIGN);
  1121. constrain_rate_if_locked(substream);
  1122. if (ice->spdif.ops.open)
  1123. ice->spdif.ops.open(ice, substream);
  1124. return 0;
  1125. }
  1126. static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
  1127. {
  1128. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1129. if (PRO_RATE_RESET)
  1130. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1131. ice->capture_con_substream = NULL;
  1132. if (ice->spdif.ops.close)
  1133. ice->spdif.ops.close(ice, substream);
  1134. return 0;
  1135. }
  1136. static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
  1137. .open = snd_vt1724_playback_spdif_open,
  1138. .close = snd_vt1724_playback_spdif_close,
  1139. .ioctl = snd_pcm_lib_ioctl,
  1140. .hw_params = snd_vt1724_pcm_hw_params,
  1141. .hw_free = snd_vt1724_pcm_hw_free,
  1142. .prepare = snd_vt1724_playback_spdif_prepare,
  1143. .trigger = snd_vt1724_pcm_trigger,
  1144. .pointer = snd_vt1724_pcm_pointer,
  1145. };
  1146. static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
  1147. .open = snd_vt1724_capture_spdif_open,
  1148. .close = snd_vt1724_capture_spdif_close,
  1149. .ioctl = snd_pcm_lib_ioctl,
  1150. .hw_params = snd_vt1724_pcm_hw_params,
  1151. .hw_free = snd_vt1724_pcm_hw_free,
  1152. .prepare = snd_vt1724_pcm_prepare,
  1153. .trigger = snd_vt1724_pcm_trigger,
  1154. .pointer = snd_vt1724_pcm_pointer,
  1155. };
  1156. static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
  1157. {
  1158. char *name;
  1159. struct snd_pcm *pcm;
  1160. int play, capt;
  1161. int err;
  1162. if (ice->force_pdma4 ||
  1163. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
  1164. play = 1;
  1165. ice->has_spdif = 1;
  1166. } else
  1167. play = 0;
  1168. if (ice->force_rdma1 ||
  1169. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
  1170. capt = 1;
  1171. ice->has_spdif = 1;
  1172. } else
  1173. capt = 0;
  1174. if (!play && !capt)
  1175. return 0; /* no spdif device */
  1176. if (ice->force_pdma4 || ice->force_rdma1)
  1177. name = "ICE1724 Secondary";
  1178. else
  1179. name = "ICE1724 IEC958";
  1180. err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
  1181. if (err < 0)
  1182. return err;
  1183. if (play)
  1184. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1185. &snd_vt1724_playback_spdif_ops);
  1186. if (capt)
  1187. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1188. &snd_vt1724_capture_spdif_ops);
  1189. pcm->private_data = ice;
  1190. pcm->info_flags = 0;
  1191. strcpy(pcm->name, name);
  1192. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1193. snd_dma_pci_data(ice->pci),
  1194. 256*1024, 256*1024);
  1195. ice->pcm = pcm;
  1196. return 0;
  1197. }
  1198. /*
  1199. * independent surround PCMs
  1200. */
  1201. static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
  1202. {
  1203. .addr = VT1724_MT_PDMA1_ADDR,
  1204. .size = VT1724_MT_PDMA1_SIZE,
  1205. .count = VT1724_MT_PDMA1_COUNT,
  1206. .start = VT1724_PDMA1_START,
  1207. },
  1208. {
  1209. .addr = VT1724_MT_PDMA2_ADDR,
  1210. .size = VT1724_MT_PDMA2_SIZE,
  1211. .count = VT1724_MT_PDMA2_COUNT,
  1212. .start = VT1724_PDMA2_START,
  1213. },
  1214. {
  1215. .addr = VT1724_MT_PDMA3_ADDR,
  1216. .size = VT1724_MT_PDMA3_SIZE,
  1217. .count = VT1724_MT_PDMA3_COUNT,
  1218. .start = VT1724_PDMA3_START,
  1219. },
  1220. };
  1221. static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
  1222. {
  1223. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1224. unsigned char val;
  1225. spin_lock_irq(&ice->reg_lock);
  1226. val = 3 - substream->number;
  1227. if (inb(ICEMT1724(ice, BURST)) < val)
  1228. outb(val, ICEMT1724(ice, BURST));
  1229. spin_unlock_irq(&ice->reg_lock);
  1230. return snd_vt1724_pcm_prepare(substream);
  1231. }
  1232. static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
  1233. {
  1234. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1235. struct snd_pcm_runtime *runtime = substream->runtime;
  1236. mutex_lock(&ice->open_mutex);
  1237. /* already used by PDMA0? */
  1238. if (ice->pcm_reserved[substream->number]) {
  1239. mutex_unlock(&ice->open_mutex);
  1240. return -EBUSY; /* FIXME: should handle blocking mode properly */
  1241. }
  1242. mutex_unlock(&ice->open_mutex);
  1243. runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
  1244. ice->playback_con_substream_ds[substream->number] = substream;
  1245. runtime->hw = snd_vt1724_2ch_stereo;
  1246. snd_pcm_set_sync(substream);
  1247. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1248. set_rate_constraints(ice, substream);
  1249. return 0;
  1250. }
  1251. static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
  1252. {
  1253. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1254. if (PRO_RATE_RESET)
  1255. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1256. ice->playback_con_substream_ds[substream->number] = NULL;
  1257. ice->pcm_reserved[substream->number] = NULL;
  1258. return 0;
  1259. }
  1260. static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
  1261. .open = snd_vt1724_playback_indep_open,
  1262. .close = snd_vt1724_playback_indep_close,
  1263. .ioctl = snd_pcm_lib_ioctl,
  1264. .hw_params = snd_vt1724_pcm_hw_params,
  1265. .hw_free = snd_vt1724_pcm_hw_free,
  1266. .prepare = snd_vt1724_playback_indep_prepare,
  1267. .trigger = snd_vt1724_pcm_trigger,
  1268. .pointer = snd_vt1724_pcm_pointer,
  1269. };
  1270. static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
  1271. {
  1272. struct snd_pcm *pcm;
  1273. int play;
  1274. int err;
  1275. play = ice->num_total_dacs / 2 - 1;
  1276. if (play <= 0)
  1277. return 0;
  1278. err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
  1279. if (err < 0)
  1280. return err;
  1281. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1282. &snd_vt1724_playback_indep_ops);
  1283. pcm->private_data = ice;
  1284. pcm->info_flags = 0;
  1285. strcpy(pcm->name, "ICE1724 Surround PCM");
  1286. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1287. snd_dma_pci_data(ice->pci),
  1288. 256*1024, 256*1024);
  1289. ice->pcm_ds = pcm;
  1290. return 0;
  1291. }
  1292. /*
  1293. * Mixer section
  1294. */
  1295. static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
  1296. {
  1297. int err;
  1298. if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
  1299. struct snd_ac97_bus *pbus;
  1300. struct snd_ac97_template ac97;
  1301. static struct snd_ac97_bus_ops ops = {
  1302. .write = snd_vt1724_ac97_write,
  1303. .read = snd_vt1724_ac97_read,
  1304. };
  1305. /* cold reset */
  1306. outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
  1307. mdelay(5); /* FIXME */
  1308. outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
  1309. err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
  1310. if (err < 0)
  1311. return err;
  1312. memset(&ac97, 0, sizeof(ac97));
  1313. ac97.private_data = ice;
  1314. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1315. if (err < 0)
  1316. dev_warn(ice->card->dev,
  1317. "cannot initialize pro ac97, skipped\n");
  1318. else
  1319. return 0;
  1320. }
  1321. /* I2S mixer only */
  1322. strcat(ice->card->mixername, "ICE1724 - multitrack");
  1323. return 0;
  1324. }
  1325. /*
  1326. *
  1327. */
  1328. static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
  1329. {
  1330. return (unsigned int)ice->eeprom.data[idx] | \
  1331. ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
  1332. ((unsigned int)ice->eeprom.data[idx + 2] << 16);
  1333. }
  1334. static void snd_vt1724_proc_read(struct snd_info_entry *entry,
  1335. struct snd_info_buffer *buffer)
  1336. {
  1337. struct snd_ice1712 *ice = entry->private_data;
  1338. unsigned int idx;
  1339. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1340. snd_iprintf(buffer, "EEPROM:\n");
  1341. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1342. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1343. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1344. snd_iprintf(buffer, " System Config : 0x%x\n",
  1345. ice->eeprom.data[ICE_EEP2_SYSCONF]);
  1346. snd_iprintf(buffer, " ACLink : 0x%x\n",
  1347. ice->eeprom.data[ICE_EEP2_ACLINK]);
  1348. snd_iprintf(buffer, " I2S : 0x%x\n",
  1349. ice->eeprom.data[ICE_EEP2_I2S]);
  1350. snd_iprintf(buffer, " S/PDIF : 0x%x\n",
  1351. ice->eeprom.data[ICE_EEP2_SPDIF]);
  1352. snd_iprintf(buffer, " GPIO direction : 0x%x\n",
  1353. ice->eeprom.gpiodir);
  1354. snd_iprintf(buffer, " GPIO mask : 0x%x\n",
  1355. ice->eeprom.gpiomask);
  1356. snd_iprintf(buffer, " GPIO state : 0x%x\n",
  1357. ice->eeprom.gpiostate);
  1358. for (idx = 0x12; idx < ice->eeprom.size; idx++)
  1359. snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
  1360. idx, ice->eeprom.data[idx]);
  1361. snd_iprintf(buffer, "\nRegisters:\n");
  1362. snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
  1363. (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
  1364. for (idx = 0x0; idx < 0x20 ; idx++)
  1365. snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
  1366. idx, inb(ice->port+idx));
  1367. for (idx = 0x0; idx < 0x30 ; idx++)
  1368. snd_iprintf(buffer, " MT%02x : 0x%02x\n",
  1369. idx, inb(ice->profi_port+idx));
  1370. }
  1371. static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
  1372. {
  1373. struct snd_info_entry *entry;
  1374. if (!snd_card_proc_new(ice->card, "ice1724", &entry))
  1375. snd_info_set_text_ops(entry, ice, snd_vt1724_proc_read);
  1376. }
  1377. /*
  1378. *
  1379. */
  1380. static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
  1381. struct snd_ctl_elem_info *uinfo)
  1382. {
  1383. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1384. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1385. return 0;
  1386. }
  1387. static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
  1388. struct snd_ctl_elem_value *ucontrol)
  1389. {
  1390. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1391. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1392. return 0;
  1393. }
  1394. static struct snd_kcontrol_new snd_vt1724_eeprom = {
  1395. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1396. .name = "ICE1724 EEPROM",
  1397. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1398. .info = snd_vt1724_eeprom_info,
  1399. .get = snd_vt1724_eeprom_get
  1400. };
  1401. /*
  1402. */
  1403. static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
  1404. struct snd_ctl_elem_info *uinfo)
  1405. {
  1406. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1407. uinfo->count = 1;
  1408. return 0;
  1409. }
  1410. static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
  1411. {
  1412. unsigned int val, rbits;
  1413. val = diga->status[0] & 0x03; /* professional, non-audio */
  1414. if (val & 0x01) {
  1415. /* professional */
  1416. if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
  1417. IEC958_AES0_PRO_EMPHASIS_5015)
  1418. val |= 1U << 3;
  1419. rbits = (diga->status[4] >> 3) & 0x0f;
  1420. if (rbits) {
  1421. switch (rbits) {
  1422. case 2: val |= 5 << 12; break; /* 96k */
  1423. case 3: val |= 6 << 12; break; /* 192k */
  1424. case 10: val |= 4 << 12; break; /* 88.2k */
  1425. case 11: val |= 7 << 12; break; /* 176.4k */
  1426. }
  1427. } else {
  1428. switch (diga->status[0] & IEC958_AES0_PRO_FS) {
  1429. case IEC958_AES0_PRO_FS_44100:
  1430. break;
  1431. case IEC958_AES0_PRO_FS_32000:
  1432. val |= 3U << 12;
  1433. break;
  1434. default:
  1435. val |= 2U << 12;
  1436. break;
  1437. }
  1438. }
  1439. } else {
  1440. /* consumer */
  1441. val |= diga->status[1] & 0x04; /* copyright */
  1442. if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
  1443. IEC958_AES0_CON_EMPHASIS_5015)
  1444. val |= 1U << 3;
  1445. val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
  1446. val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
  1447. }
  1448. return val;
  1449. }
  1450. static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
  1451. {
  1452. memset(diga->status, 0, sizeof(diga->status));
  1453. diga->status[0] = val & 0x03; /* professional, non-audio */
  1454. if (val & 0x01) {
  1455. /* professional */
  1456. if (val & (1U << 3))
  1457. diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
  1458. switch ((val >> 12) & 0x7) {
  1459. case 0:
  1460. break;
  1461. case 2:
  1462. diga->status[0] |= IEC958_AES0_PRO_FS_32000;
  1463. break;
  1464. default:
  1465. diga->status[0] |= IEC958_AES0_PRO_FS_48000;
  1466. break;
  1467. }
  1468. } else {
  1469. /* consumer */
  1470. diga->status[0] |= val & (1U << 2); /* copyright */
  1471. if (val & (1U << 3))
  1472. diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
  1473. diga->status[1] |= (val >> 4) & 0x3f; /* category */
  1474. diga->status[3] |= (val >> 12) & 0x07; /* fs */
  1475. }
  1476. }
  1477. static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
  1478. struct snd_ctl_elem_value *ucontrol)
  1479. {
  1480. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1481. unsigned int val;
  1482. val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1483. decode_spdif_bits(&ucontrol->value.iec958, val);
  1484. return 0;
  1485. }
  1486. static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
  1487. struct snd_ctl_elem_value *ucontrol)
  1488. {
  1489. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1490. unsigned int val, old;
  1491. val = encode_spdif_bits(&ucontrol->value.iec958);
  1492. spin_lock_irq(&ice->reg_lock);
  1493. old = inw(ICEMT1724(ice, SPDIF_CTRL));
  1494. if (val != old)
  1495. update_spdif_bits(ice, val);
  1496. spin_unlock_irq(&ice->reg_lock);
  1497. return val != old;
  1498. }
  1499. static struct snd_kcontrol_new snd_vt1724_spdif_default =
  1500. {
  1501. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1502. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1503. .info = snd_vt1724_spdif_info,
  1504. .get = snd_vt1724_spdif_default_get,
  1505. .put = snd_vt1724_spdif_default_put
  1506. };
  1507. static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1508. struct snd_ctl_elem_value *ucontrol)
  1509. {
  1510. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1511. IEC958_AES0_PROFESSIONAL |
  1512. IEC958_AES0_CON_NOT_COPYRIGHT |
  1513. IEC958_AES0_CON_EMPHASIS;
  1514. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1515. IEC958_AES1_CON_CATEGORY;
  1516. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1517. return 0;
  1518. }
  1519. static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1523. IEC958_AES0_PROFESSIONAL |
  1524. IEC958_AES0_PRO_FS |
  1525. IEC958_AES0_PRO_EMPHASIS;
  1526. return 0;
  1527. }
  1528. static struct snd_kcontrol_new snd_vt1724_spdif_maskc =
  1529. {
  1530. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1531. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1532. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1533. .info = snd_vt1724_spdif_info,
  1534. .get = snd_vt1724_spdif_maskc_get,
  1535. };
  1536. static struct snd_kcontrol_new snd_vt1724_spdif_maskp =
  1537. {
  1538. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1539. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1540. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1541. .info = snd_vt1724_spdif_info,
  1542. .get = snd_vt1724_spdif_maskp_get,
  1543. };
  1544. #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
  1545. static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
  1546. struct snd_ctl_elem_value *ucontrol)
  1547. {
  1548. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1549. ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
  1550. VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
  1551. return 0;
  1552. }
  1553. static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
  1554. struct snd_ctl_elem_value *ucontrol)
  1555. {
  1556. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1557. unsigned char old, val;
  1558. spin_lock_irq(&ice->reg_lock);
  1559. old = val = inb(ICEREG1724(ice, SPDIF_CFG));
  1560. val &= ~VT1724_CFG_SPDIF_OUT_EN;
  1561. if (ucontrol->value.integer.value[0])
  1562. val |= VT1724_CFG_SPDIF_OUT_EN;
  1563. if (old != val)
  1564. outb(val, ICEREG1724(ice, SPDIF_CFG));
  1565. spin_unlock_irq(&ice->reg_lock);
  1566. return old != val;
  1567. }
  1568. static struct snd_kcontrol_new snd_vt1724_spdif_switch =
  1569. {
  1570. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1571. /* FIXME: the following conflict with IEC958 Playback Route */
  1572. /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
  1573. .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
  1574. .info = snd_vt1724_spdif_sw_info,
  1575. .get = snd_vt1724_spdif_sw_get,
  1576. .put = snd_vt1724_spdif_sw_put
  1577. };
  1578. #if 0 /* NOT USED YET */
  1579. /*
  1580. * GPIO access from extern
  1581. */
  1582. #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
  1583. int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
  1584. struct snd_ctl_elem_value *ucontrol)
  1585. {
  1586. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1587. int shift = kcontrol->private_value & 0xff;
  1588. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1589. snd_ice1712_save_gpio_status(ice);
  1590. ucontrol->value.integer.value[0] =
  1591. (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
  1592. snd_ice1712_restore_gpio_status(ice);
  1593. return 0;
  1594. }
  1595. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_value *ucontrol)
  1597. {
  1598. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1599. int shift = kcontrol->private_value & 0xff;
  1600. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1601. unsigned int val, nval;
  1602. if (kcontrol->private_value & (1 << 31))
  1603. return -EPERM;
  1604. nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
  1605. snd_ice1712_save_gpio_status(ice);
  1606. val = snd_ice1712_gpio_read(ice);
  1607. nval |= val & ~(1 << shift);
  1608. if (val != nval)
  1609. snd_ice1712_gpio_write(ice, nval);
  1610. snd_ice1712_restore_gpio_status(ice);
  1611. return val != nval;
  1612. }
  1613. #endif /* NOT USED YET */
  1614. /*
  1615. * rate
  1616. */
  1617. static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1618. struct snd_ctl_elem_info *uinfo)
  1619. {
  1620. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1621. int hw_rates_count = ice->hw_rates->count;
  1622. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1623. uinfo->count = 1;
  1624. /* internal clocks */
  1625. uinfo->value.enumerated.items = hw_rates_count;
  1626. /* external clocks */
  1627. if (ice->force_rdma1 ||
  1628. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
  1629. uinfo->value.enumerated.items += ice->ext_clock_count;
  1630. /* upper limit - keep at top */
  1631. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1632. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1633. if (uinfo->value.enumerated.item >= hw_rates_count)
  1634. /* ext_clock items */
  1635. strcpy(uinfo->value.enumerated.name,
  1636. ice->ext_clock_names[
  1637. uinfo->value.enumerated.item - hw_rates_count]);
  1638. else
  1639. /* int clock items */
  1640. sprintf(uinfo->value.enumerated.name, "%d",
  1641. ice->hw_rates->list[uinfo->value.enumerated.item]);
  1642. return 0;
  1643. }
  1644. static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1645. struct snd_ctl_elem_value *ucontrol)
  1646. {
  1647. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1648. unsigned int i, rate;
  1649. spin_lock_irq(&ice->reg_lock);
  1650. if (ice->is_spdif_master(ice)) {
  1651. ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
  1652. ice->get_spdif_master_type(ice);
  1653. } else {
  1654. rate = ice->get_rate(ice);
  1655. ucontrol->value.enumerated.item[0] = 0;
  1656. for (i = 0; i < ice->hw_rates->count; i++) {
  1657. if (ice->hw_rates->list[i] == rate) {
  1658. ucontrol->value.enumerated.item[0] = i;
  1659. break;
  1660. }
  1661. }
  1662. }
  1663. spin_unlock_irq(&ice->reg_lock);
  1664. return 0;
  1665. }
  1666. static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
  1667. {
  1668. /* standard external clock - only single type - SPDIF IN */
  1669. return 0;
  1670. }
  1671. /* setting clock to external - SPDIF */
  1672. static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
  1673. {
  1674. unsigned char oval;
  1675. unsigned char i2s_oval;
  1676. oval = inb(ICEMT1724(ice, RATE));
  1677. outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
  1678. /* setting 256fs */
  1679. i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
  1680. outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
  1681. return 0;
  1682. }
  1683. static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1684. struct snd_ctl_elem_value *ucontrol)
  1685. {
  1686. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1687. unsigned int old_rate, new_rate;
  1688. unsigned int item = ucontrol->value.enumerated.item[0];
  1689. unsigned int first_ext_clock = ice->hw_rates->count;
  1690. if (item > first_ext_clock + ice->ext_clock_count - 1)
  1691. return -EINVAL;
  1692. /* if rate = 0 => external clock */
  1693. spin_lock_irq(&ice->reg_lock);
  1694. if (ice->is_spdif_master(ice))
  1695. old_rate = 0;
  1696. else
  1697. old_rate = ice->get_rate(ice);
  1698. if (item >= first_ext_clock) {
  1699. /* switching to external clock */
  1700. ice->set_spdif_clock(ice, item - first_ext_clock);
  1701. new_rate = 0;
  1702. } else {
  1703. /* internal on-card clock */
  1704. new_rate = ice->hw_rates->list[item];
  1705. ice->pro_rate_default = new_rate;
  1706. spin_unlock_irq(&ice->reg_lock);
  1707. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
  1708. spin_lock_irq(&ice->reg_lock);
  1709. }
  1710. spin_unlock_irq(&ice->reg_lock);
  1711. /* the first switch to the ext. clock mode? */
  1712. if (old_rate != new_rate && !new_rate) {
  1713. /* notify akm chips as well */
  1714. unsigned int i;
  1715. if (ice->gpio.set_pro_rate)
  1716. ice->gpio.set_pro_rate(ice, 0);
  1717. for (i = 0; i < ice->akm_codecs; i++) {
  1718. if (ice->akm[i].ops.set_rate_val)
  1719. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  1720. }
  1721. }
  1722. return old_rate != new_rate;
  1723. }
  1724. static struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
  1725. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1726. .name = "Multi Track Internal Clock",
  1727. .info = snd_vt1724_pro_internal_clock_info,
  1728. .get = snd_vt1724_pro_internal_clock_get,
  1729. .put = snd_vt1724_pro_internal_clock_put
  1730. };
  1731. #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
  1732. static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1733. struct snd_ctl_elem_value *ucontrol)
  1734. {
  1735. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1736. return 0;
  1737. }
  1738. static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1739. struct snd_ctl_elem_value *ucontrol)
  1740. {
  1741. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1742. int change = 0, nval;
  1743. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1744. spin_lock_irq(&ice->reg_lock);
  1745. change = PRO_RATE_LOCKED != nval;
  1746. PRO_RATE_LOCKED = nval;
  1747. spin_unlock_irq(&ice->reg_lock);
  1748. return change;
  1749. }
  1750. static struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
  1751. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1752. .name = "Multi Track Rate Locking",
  1753. .info = snd_vt1724_pro_rate_locking_info,
  1754. .get = snd_vt1724_pro_rate_locking_get,
  1755. .put = snd_vt1724_pro_rate_locking_put
  1756. };
  1757. #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
  1758. static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1759. struct snd_ctl_elem_value *ucontrol)
  1760. {
  1761. ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
  1762. return 0;
  1763. }
  1764. static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1765. struct snd_ctl_elem_value *ucontrol)
  1766. {
  1767. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1768. int change = 0, nval;
  1769. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1770. spin_lock_irq(&ice->reg_lock);
  1771. change = PRO_RATE_RESET != nval;
  1772. PRO_RATE_RESET = nval;
  1773. spin_unlock_irq(&ice->reg_lock);
  1774. return change;
  1775. }
  1776. static struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
  1777. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1778. .name = "Multi Track Rate Reset",
  1779. .info = snd_vt1724_pro_rate_reset_info,
  1780. .get = snd_vt1724_pro_rate_reset_get,
  1781. .put = snd_vt1724_pro_rate_reset_put
  1782. };
  1783. /*
  1784. * routing
  1785. */
  1786. static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
  1787. struct snd_ctl_elem_info *uinfo)
  1788. {
  1789. static const char * const texts[] = {
  1790. "PCM Out", /* 0 */
  1791. "H/W In 0", "H/W In 1", /* 1-2 */
  1792. "IEC958 In L", "IEC958 In R", /* 3-4 */
  1793. };
  1794. return snd_ctl_enum_info(uinfo, 1, 5, texts);
  1795. }
  1796. static inline int analog_route_shift(int idx)
  1797. {
  1798. return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
  1799. }
  1800. static inline int digital_route_shift(int idx)
  1801. {
  1802. return idx * 3;
  1803. }
  1804. int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
  1805. {
  1806. unsigned long val;
  1807. unsigned char eitem;
  1808. static const unsigned char xlate[8] = {
  1809. 0, 255, 1, 2, 255, 255, 3, 4,
  1810. };
  1811. val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1812. val >>= shift;
  1813. val &= 7; /* we now have 3 bits per output */
  1814. eitem = xlate[val];
  1815. if (eitem == 255) {
  1816. snd_BUG();
  1817. return 0;
  1818. }
  1819. return eitem;
  1820. }
  1821. int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
  1822. int shift)
  1823. {
  1824. unsigned int old_val, nval;
  1825. int change;
  1826. static const unsigned char xroute[8] = {
  1827. 0, /* PCM */
  1828. 2, /* PSDIN0 Left */
  1829. 3, /* PSDIN0 Right */
  1830. 6, /* SPDIN Left */
  1831. 7, /* SPDIN Right */
  1832. };
  1833. nval = xroute[val % 5];
  1834. val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1835. val &= ~(0x07 << shift);
  1836. val |= nval << shift;
  1837. change = val != old_val;
  1838. if (change)
  1839. outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
  1840. return change;
  1841. }
  1842. static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1843. struct snd_ctl_elem_value *ucontrol)
  1844. {
  1845. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1846. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1847. ucontrol->value.enumerated.item[0] =
  1848. snd_ice1724_get_route_val(ice, analog_route_shift(idx));
  1849. return 0;
  1850. }
  1851. static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1852. struct snd_ctl_elem_value *ucontrol)
  1853. {
  1854. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1855. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1856. return snd_ice1724_put_route_val(ice,
  1857. ucontrol->value.enumerated.item[0],
  1858. analog_route_shift(idx));
  1859. }
  1860. static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1861. struct snd_ctl_elem_value *ucontrol)
  1862. {
  1863. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1864. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1865. ucontrol->value.enumerated.item[0] =
  1866. snd_ice1724_get_route_val(ice, digital_route_shift(idx));
  1867. return 0;
  1868. }
  1869. static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1870. struct snd_ctl_elem_value *ucontrol)
  1871. {
  1872. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1873. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1874. return snd_ice1724_put_route_val(ice,
  1875. ucontrol->value.enumerated.item[0],
  1876. digital_route_shift(idx));
  1877. }
  1878. static struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
  1879. {
  1880. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1881. .name = "H/W Playback Route",
  1882. .info = snd_vt1724_pro_route_info,
  1883. .get = snd_vt1724_pro_route_analog_get,
  1884. .put = snd_vt1724_pro_route_analog_put,
  1885. };
  1886. static struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
  1887. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1888. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1889. .info = snd_vt1724_pro_route_info,
  1890. .get = snd_vt1724_pro_route_spdif_get,
  1891. .put = snd_vt1724_pro_route_spdif_put,
  1892. .count = 2,
  1893. };
  1894. static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
  1895. struct snd_ctl_elem_info *uinfo)
  1896. {
  1897. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1898. uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
  1899. uinfo->value.integer.min = 0;
  1900. uinfo->value.integer.max = 255;
  1901. return 0;
  1902. }
  1903. static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
  1904. struct snd_ctl_elem_value *ucontrol)
  1905. {
  1906. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1907. int idx;
  1908. spin_lock_irq(&ice->reg_lock);
  1909. for (idx = 0; idx < 22; idx++) {
  1910. outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
  1911. ucontrol->value.integer.value[idx] =
  1912. inb(ICEMT1724(ice, MONITOR_PEAKDATA));
  1913. }
  1914. spin_unlock_irq(&ice->reg_lock);
  1915. return 0;
  1916. }
  1917. static struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
  1918. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1919. .name = "Multi Track Peak",
  1920. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1921. .info = snd_vt1724_pro_peak_info,
  1922. .get = snd_vt1724_pro_peak_get
  1923. };
  1924. /*
  1925. *
  1926. */
  1927. static struct snd_ice1712_card_info no_matched;
  1928. /*
  1929. ooAoo cards with no controls
  1930. */
  1931. static unsigned char ooaoo_sq210_eeprom[] = {
  1932. [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
  1933. 1xDACs */
  1934. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  1935. [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
  1936. [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
  1937. [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
  1938. [ICE_EEP2_GPIO_DIR1] = 0x00,
  1939. [ICE_EEP2_GPIO_DIR2] = 0x00,
  1940. [ICE_EEP2_GPIO_MASK] = 0xff,
  1941. [ICE_EEP2_GPIO_MASK1] = 0xff,
  1942. [ICE_EEP2_GPIO_MASK2] = 0xff,
  1943. [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
  1944. [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
  1945. and GPIO15 always zero */
  1946. [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
  1947. };
  1948. static struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
  1949. {
  1950. .name = "ooAoo SQ210a",
  1951. .model = "sq210a",
  1952. .eeprom_size = sizeof(ooaoo_sq210_eeprom),
  1953. .eeprom_data = ooaoo_sq210_eeprom,
  1954. },
  1955. { } /* terminator */
  1956. };
  1957. static struct snd_ice1712_card_info *card_tables[] = {
  1958. snd_vt1724_revo_cards,
  1959. snd_vt1724_amp_cards,
  1960. snd_vt1724_aureon_cards,
  1961. snd_vt1720_mobo_cards,
  1962. snd_vt1720_pontis_cards,
  1963. snd_vt1724_prodigy_hifi_cards,
  1964. snd_vt1724_prodigy192_cards,
  1965. snd_vt1724_juli_cards,
  1966. snd_vt1724_maya44_cards,
  1967. snd_vt1724_phase_cards,
  1968. snd_vt1724_wtm_cards,
  1969. snd_vt1724_se_cards,
  1970. snd_vt1724_qtet_cards,
  1971. snd_vt1724_ooaoo_cards,
  1972. snd_vt1724_psc724_cards,
  1973. NULL,
  1974. };
  1975. /*
  1976. */
  1977. static void wait_i2c_busy(struct snd_ice1712 *ice)
  1978. {
  1979. int t = 0x10000;
  1980. while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
  1981. ;
  1982. if (t == -1)
  1983. dev_err(ice->card->dev, "i2c busy timeout\n");
  1984. }
  1985. unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
  1986. unsigned char dev, unsigned char addr)
  1987. {
  1988. unsigned char val;
  1989. mutex_lock(&ice->i2c_mutex);
  1990. wait_i2c_busy(ice);
  1991. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  1992. outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  1993. wait_i2c_busy(ice);
  1994. val = inb(ICEREG1724(ice, I2C_DATA));
  1995. mutex_unlock(&ice->i2c_mutex);
  1996. /*
  1997. dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
  1998. */
  1999. return val;
  2000. }
  2001. void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
  2002. unsigned char dev, unsigned char addr, unsigned char data)
  2003. {
  2004. mutex_lock(&ice->i2c_mutex);
  2005. wait_i2c_busy(ice);
  2006. /*
  2007. dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
  2008. */
  2009. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  2010. outb(data, ICEREG1724(ice, I2C_DATA));
  2011. outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  2012. wait_i2c_busy(ice);
  2013. mutex_unlock(&ice->i2c_mutex);
  2014. }
  2015. static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
  2016. const char *modelname)
  2017. {
  2018. const int dev = 0xa0; /* EEPROM device address */
  2019. unsigned int i, size;
  2020. struct snd_ice1712_card_info * const *tbl, *c;
  2021. if (!modelname || !*modelname) {
  2022. ice->eeprom.subvendor = 0;
  2023. if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
  2024. ice->eeprom.subvendor =
  2025. (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
  2026. (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
  2027. (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
  2028. (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
  2029. if (ice->eeprom.subvendor == 0 ||
  2030. ice->eeprom.subvendor == (unsigned int)-1) {
  2031. /* invalid subvendor from EEPROM, try the PCI
  2032. * subststem ID instead
  2033. */
  2034. u16 vendor, device;
  2035. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
  2036. &vendor);
  2037. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2038. ice->eeprom.subvendor =
  2039. ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2040. if (ice->eeprom.subvendor == 0 ||
  2041. ice->eeprom.subvendor == (unsigned int)-1) {
  2042. dev_err(ice->card->dev,
  2043. "No valid ID is found\n");
  2044. return -ENXIO;
  2045. }
  2046. }
  2047. }
  2048. for (tbl = card_tables; *tbl; tbl++) {
  2049. for (c = *tbl; c->name; c++) {
  2050. if (modelname && c->model &&
  2051. !strcmp(modelname, c->model)) {
  2052. dev_info(ice->card->dev,
  2053. "Using board model %s\n",
  2054. c->name);
  2055. ice->eeprom.subvendor = c->subvendor;
  2056. } else if (c->subvendor != ice->eeprom.subvendor)
  2057. continue;
  2058. ice->card_info = c;
  2059. if (!c->eeprom_size || !c->eeprom_data)
  2060. goto found;
  2061. /* if the EEPROM is given by the driver, use it */
  2062. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2063. ice->eeprom.version = 2;
  2064. ice->eeprom.size = c->eeprom_size + 6;
  2065. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2066. goto read_skipped;
  2067. }
  2068. }
  2069. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2070. ice->eeprom.subvendor);
  2071. #ifdef CONFIG_PM_SLEEP
  2072. /* assume AC97-only card which can suspend without additional code */
  2073. ice->pm_suspend_enabled = 1;
  2074. #endif
  2075. found:
  2076. ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
  2077. if (ice->eeprom.size < 6)
  2078. ice->eeprom.size = 32;
  2079. else if (ice->eeprom.size > 32) {
  2080. dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
  2081. ice->eeprom.size);
  2082. return -EIO;
  2083. }
  2084. ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
  2085. if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
  2086. dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
  2087. ice->eeprom.version);
  2088. size = ice->eeprom.size - 6;
  2089. for (i = 0; i < size; i++)
  2090. ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
  2091. read_skipped:
  2092. ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
  2093. ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
  2094. ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
  2095. return 0;
  2096. }
  2097. static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
  2098. {
  2099. outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
  2100. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2101. msleep(10);
  2102. outb(0, ICEREG1724(ice, CONTROL));
  2103. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2104. msleep(10);
  2105. }
  2106. static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
  2107. {
  2108. outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
  2109. outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
  2110. outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
  2111. outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
  2112. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2113. ice->gpio.direction = ice->eeprom.gpiodir;
  2114. snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
  2115. snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
  2116. snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
  2117. outb(0, ICEREG1724(ice, POWERDOWN));
  2118. /* MPU_RX and TX irq masks are cleared later dynamically */
  2119. outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
  2120. /* don't handle FIFO overrun/underruns (just yet),
  2121. * since they cause machine lockups
  2122. */
  2123. outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
  2124. return 0;
  2125. }
  2126. static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
  2127. {
  2128. int err;
  2129. struct snd_kcontrol *kctl;
  2130. if (snd_BUG_ON(!ice->pcm))
  2131. return -EIO;
  2132. if (!ice->own_routing) {
  2133. err = snd_ctl_add(ice->card,
  2134. snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
  2135. if (err < 0)
  2136. return err;
  2137. }
  2138. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
  2139. if (err < 0)
  2140. return err;
  2141. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
  2142. if (err < 0)
  2143. return err;
  2144. kctl->id.device = ice->pcm->device;
  2145. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
  2146. if (err < 0)
  2147. return err;
  2148. kctl->id.device = ice->pcm->device;
  2149. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
  2150. if (err < 0)
  2151. return err;
  2152. kctl->id.device = ice->pcm->device;
  2153. #if 0 /* use default only */
  2154. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
  2155. if (err < 0)
  2156. return err;
  2157. kctl->id.device = ice->pcm->device;
  2158. ice->spdif.stream_ctl = kctl;
  2159. #endif
  2160. return 0;
  2161. }
  2162. static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
  2163. {
  2164. int err;
  2165. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
  2166. if (err < 0)
  2167. return err;
  2168. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
  2169. if (err < 0)
  2170. return err;
  2171. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
  2172. if (err < 0)
  2173. return err;
  2174. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
  2175. if (err < 0)
  2176. return err;
  2177. if (!ice->own_routing && ice->num_total_dacs > 0) {
  2178. struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
  2179. tmp.count = ice->num_total_dacs;
  2180. if (ice->vt1720 && tmp.count > 2)
  2181. tmp.count = 2;
  2182. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2183. if (err < 0)
  2184. return err;
  2185. }
  2186. return snd_ctl_add(ice->card,
  2187. snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
  2188. }
  2189. static int snd_vt1724_free(struct snd_ice1712 *ice)
  2190. {
  2191. if (!ice->port)
  2192. goto __hw_end;
  2193. /* mask all interrupts */
  2194. outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
  2195. outb(0xff, ICEREG1724(ice, IRQMASK));
  2196. /* --- */
  2197. __hw_end:
  2198. if (ice->irq >= 0)
  2199. free_irq(ice->irq, ice);
  2200. pci_release_regions(ice->pci);
  2201. snd_ice1712_akm4xxx_free(ice);
  2202. pci_disable_device(ice->pci);
  2203. kfree(ice->spec);
  2204. kfree(ice);
  2205. return 0;
  2206. }
  2207. static int snd_vt1724_dev_free(struct snd_device *device)
  2208. {
  2209. struct snd_ice1712 *ice = device->device_data;
  2210. return snd_vt1724_free(ice);
  2211. }
  2212. static int snd_vt1724_create(struct snd_card *card,
  2213. struct pci_dev *pci,
  2214. const char *modelname,
  2215. struct snd_ice1712 **r_ice1712)
  2216. {
  2217. struct snd_ice1712 *ice;
  2218. int err;
  2219. static struct snd_device_ops ops = {
  2220. .dev_free = snd_vt1724_dev_free,
  2221. };
  2222. *r_ice1712 = NULL;
  2223. /* enable PCI device */
  2224. err = pci_enable_device(pci);
  2225. if (err < 0)
  2226. return err;
  2227. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2228. if (ice == NULL) {
  2229. pci_disable_device(pci);
  2230. return -ENOMEM;
  2231. }
  2232. ice->vt1724 = 1;
  2233. spin_lock_init(&ice->reg_lock);
  2234. mutex_init(&ice->gpio_mutex);
  2235. mutex_init(&ice->open_mutex);
  2236. mutex_init(&ice->i2c_mutex);
  2237. ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
  2238. ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
  2239. ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
  2240. ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
  2241. ice->gpio.set_data = snd_vt1724_set_gpio_data;
  2242. ice->gpio.get_data = snd_vt1724_get_gpio_data;
  2243. ice->card = card;
  2244. ice->pci = pci;
  2245. ice->irq = -1;
  2246. pci_set_master(pci);
  2247. snd_vt1724_proc_init(ice);
  2248. synchronize_irq(pci->irq);
  2249. card->private_data = ice;
  2250. err = pci_request_regions(pci, "ICE1724");
  2251. if (err < 0) {
  2252. kfree(ice);
  2253. pci_disable_device(pci);
  2254. return err;
  2255. }
  2256. ice->port = pci_resource_start(pci, 0);
  2257. ice->profi_port = pci_resource_start(pci, 1);
  2258. if (request_irq(pci->irq, snd_vt1724_interrupt,
  2259. IRQF_SHARED, KBUILD_MODNAME, ice)) {
  2260. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2261. snd_vt1724_free(ice);
  2262. return -EIO;
  2263. }
  2264. ice->irq = pci->irq;
  2265. snd_vt1724_chip_reset(ice);
  2266. if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
  2267. snd_vt1724_free(ice);
  2268. return -EIO;
  2269. }
  2270. if (snd_vt1724_chip_init(ice) < 0) {
  2271. snd_vt1724_free(ice);
  2272. return -EIO;
  2273. }
  2274. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2275. if (err < 0) {
  2276. snd_vt1724_free(ice);
  2277. return err;
  2278. }
  2279. *r_ice1712 = ice;
  2280. return 0;
  2281. }
  2282. /*
  2283. *
  2284. * Registration
  2285. *
  2286. */
  2287. static int snd_vt1724_probe(struct pci_dev *pci,
  2288. const struct pci_device_id *pci_id)
  2289. {
  2290. static int dev;
  2291. struct snd_card *card;
  2292. struct snd_ice1712 *ice;
  2293. int pcm_dev = 0, err;
  2294. struct snd_ice1712_card_info * const *tbl, *c;
  2295. if (dev >= SNDRV_CARDS)
  2296. return -ENODEV;
  2297. if (!enable[dev]) {
  2298. dev++;
  2299. return -ENOENT;
  2300. }
  2301. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2302. 0, &card);
  2303. if (err < 0)
  2304. return err;
  2305. strcpy(card->driver, "ICE1724");
  2306. strcpy(card->shortname, "ICEnsemble ICE1724");
  2307. err = snd_vt1724_create(card, pci, model[dev], &ice);
  2308. if (err < 0) {
  2309. snd_card_free(card);
  2310. return err;
  2311. }
  2312. /* field init before calling chip_init */
  2313. ice->ext_clock_count = 0;
  2314. for (tbl = card_tables; *tbl; tbl++) {
  2315. for (c = *tbl; c->name; c++) {
  2316. if ((model[dev] && c->model &&
  2317. !strcmp(model[dev], c->model)) ||
  2318. (c->subvendor == ice->eeprom.subvendor)) {
  2319. strcpy(card->shortname, c->name);
  2320. if (c->driver) /* specific driver? */
  2321. strcpy(card->driver, c->driver);
  2322. if (c->chip_init) {
  2323. err = c->chip_init(ice);
  2324. if (err < 0) {
  2325. snd_card_free(card);
  2326. return err;
  2327. }
  2328. }
  2329. goto __found;
  2330. }
  2331. }
  2332. }
  2333. c = &no_matched;
  2334. __found:
  2335. /*
  2336. * VT1724 has separate DMAs for the analog and the SPDIF streams while
  2337. * ICE1712 has only one for both (mixed up).
  2338. *
  2339. * Confusingly the analog PCM is named "professional" here because it
  2340. * was called so in ice1712 driver, and vt1724 driver is derived from
  2341. * ice1712 driver.
  2342. */
  2343. ice->pro_rate_default = PRO_RATE_DEFAULT;
  2344. if (!ice->is_spdif_master)
  2345. ice->is_spdif_master = stdclock_is_spdif_master;
  2346. if (!ice->get_rate)
  2347. ice->get_rate = stdclock_get_rate;
  2348. if (!ice->set_rate)
  2349. ice->set_rate = stdclock_set_rate;
  2350. if (!ice->set_mclk)
  2351. ice->set_mclk = stdclock_set_mclk;
  2352. if (!ice->set_spdif_clock)
  2353. ice->set_spdif_clock = stdclock_set_spdif_clock;
  2354. if (!ice->get_spdif_master_type)
  2355. ice->get_spdif_master_type = stdclock_get_spdif_master_type;
  2356. if (!ice->ext_clock_names)
  2357. ice->ext_clock_names = ext_clock_names;
  2358. if (!ice->ext_clock_count)
  2359. ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
  2360. if (!ice->hw_rates)
  2361. set_std_hw_rates(ice);
  2362. err = snd_vt1724_pcm_profi(ice, pcm_dev++);
  2363. if (err < 0) {
  2364. snd_card_free(card);
  2365. return err;
  2366. }
  2367. err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
  2368. if (err < 0) {
  2369. snd_card_free(card);
  2370. return err;
  2371. }
  2372. err = snd_vt1724_pcm_indep(ice, pcm_dev++);
  2373. if (err < 0) {
  2374. snd_card_free(card);
  2375. return err;
  2376. }
  2377. err = snd_vt1724_ac97_mixer(ice);
  2378. if (err < 0) {
  2379. snd_card_free(card);
  2380. return err;
  2381. }
  2382. err = snd_vt1724_build_controls(ice);
  2383. if (err < 0) {
  2384. snd_card_free(card);
  2385. return err;
  2386. }
  2387. if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
  2388. err = snd_vt1724_spdif_build_controls(ice);
  2389. if (err < 0) {
  2390. snd_card_free(card);
  2391. return err;
  2392. }
  2393. }
  2394. if (c->build_controls) {
  2395. err = c->build_controls(ice);
  2396. if (err < 0) {
  2397. snd_card_free(card);
  2398. return err;
  2399. }
  2400. }
  2401. if (!c->no_mpu401) {
  2402. if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
  2403. struct snd_rawmidi *rmidi;
  2404. err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
  2405. if (err < 0) {
  2406. snd_card_free(card);
  2407. return err;
  2408. }
  2409. ice->rmidi[0] = rmidi;
  2410. rmidi->private_data = ice;
  2411. strcpy(rmidi->name, "ICE1724 MIDI");
  2412. rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
  2413. SNDRV_RAWMIDI_INFO_INPUT |
  2414. SNDRV_RAWMIDI_INFO_DUPLEX;
  2415. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
  2416. &vt1724_midi_output_ops);
  2417. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
  2418. &vt1724_midi_input_ops);
  2419. /* set watermarks */
  2420. outb(VT1724_MPU_RX_FIFO | 0x1,
  2421. ICEREG1724(ice, MPU_FIFO_WM));
  2422. outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
  2423. /* set UART mode */
  2424. outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
  2425. }
  2426. }
  2427. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2428. card->shortname, ice->port, ice->irq);
  2429. err = snd_card_register(card);
  2430. if (err < 0) {
  2431. snd_card_free(card);
  2432. return err;
  2433. }
  2434. pci_set_drvdata(pci, card);
  2435. dev++;
  2436. return 0;
  2437. }
  2438. static void snd_vt1724_remove(struct pci_dev *pci)
  2439. {
  2440. struct snd_card *card = pci_get_drvdata(pci);
  2441. struct snd_ice1712 *ice = card->private_data;
  2442. if (ice->card_info && ice->card_info->chip_exit)
  2443. ice->card_info->chip_exit(ice);
  2444. snd_card_free(card);
  2445. }
  2446. #ifdef CONFIG_PM_SLEEP
  2447. static int snd_vt1724_suspend(struct device *dev)
  2448. {
  2449. struct snd_card *card = dev_get_drvdata(dev);
  2450. struct snd_ice1712 *ice = card->private_data;
  2451. if (!ice->pm_suspend_enabled)
  2452. return 0;
  2453. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2454. snd_pcm_suspend_all(ice->pcm);
  2455. snd_pcm_suspend_all(ice->pcm_pro);
  2456. snd_pcm_suspend_all(ice->pcm_ds);
  2457. snd_ac97_suspend(ice->ac97);
  2458. spin_lock_irq(&ice->reg_lock);
  2459. ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
  2460. ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
  2461. ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
  2462. ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  2463. spin_unlock_irq(&ice->reg_lock);
  2464. if (ice->pm_suspend)
  2465. ice->pm_suspend(ice);
  2466. return 0;
  2467. }
  2468. static int snd_vt1724_resume(struct device *dev)
  2469. {
  2470. struct snd_card *card = dev_get_drvdata(dev);
  2471. struct snd_ice1712 *ice = card->private_data;
  2472. if (!ice->pm_suspend_enabled)
  2473. return 0;
  2474. snd_vt1724_chip_reset(ice);
  2475. if (snd_vt1724_chip_init(ice) < 0) {
  2476. snd_card_disconnect(card);
  2477. return -EIO;
  2478. }
  2479. if (ice->pm_resume)
  2480. ice->pm_resume(ice);
  2481. if (ice->pm_saved_is_spdif_master) {
  2482. /* switching to external clock via SPDIF */
  2483. ice->set_spdif_clock(ice, 0);
  2484. } else {
  2485. /* internal on-card clock */
  2486. int rate;
  2487. if (ice->cur_rate)
  2488. rate = ice->cur_rate;
  2489. else
  2490. rate = ice->pro_rate_default;
  2491. snd_vt1724_set_pro_rate(ice, rate, 1);
  2492. }
  2493. update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
  2494. outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
  2495. outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
  2496. snd_ac97_resume(ice->ac97);
  2497. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2498. return 0;
  2499. }
  2500. static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
  2501. #define SND_VT1724_PM_OPS &snd_vt1724_pm
  2502. #else
  2503. #define SND_VT1724_PM_OPS NULL
  2504. #endif /* CONFIG_PM_SLEEP */
  2505. static struct pci_driver vt1724_driver = {
  2506. .name = KBUILD_MODNAME,
  2507. .id_table = snd_vt1724_ids,
  2508. .probe = snd_vt1724_probe,
  2509. .remove = snd_vt1724_remove,
  2510. .driver = {
  2511. .pm = SND_VT1724_PM_OPS,
  2512. },
  2513. };
  2514. module_pci_driver(vt1724_driver);