msi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436
  1. /*
  2. * linux/kernel/irq/msi.c
  3. *
  4. * Copyright (C) 2014 Intel Corp.
  5. * Author: Jiang Liu <jiang.liu@linux.intel.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This file contains common code to support Message Signalled Interrupt for
  10. * PCI compatible and non PCI compatible devices.
  11. */
  12. #include <linux/types.h>
  13. #include <linux/device.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/msi.h>
  17. /* Temparory solution for building, will be removed later */
  18. #include <linux/pci.h>
  19. /**
  20. * alloc_msi_entry - Allocate an initialize msi_entry
  21. * @dev: Pointer to the device for which this is allocated
  22. * @nvec: The number of vectors used in this entry
  23. * @affinity: Optional pointer to an affinity mask array size of @nvec
  24. *
  25. * If @affinity is not NULL then a an affinity array[@nvec] is allocated
  26. * and the affinity masks from @affinity are copied.
  27. */
  28. struct msi_desc *
  29. alloc_msi_entry(struct device *dev, int nvec, const struct cpumask *affinity)
  30. {
  31. struct msi_desc *desc;
  32. desc = kzalloc(sizeof(*desc), GFP_KERNEL);
  33. if (!desc)
  34. return NULL;
  35. INIT_LIST_HEAD(&desc->list);
  36. desc->dev = dev;
  37. desc->nvec_used = nvec;
  38. if (affinity) {
  39. desc->affinity = kmemdup(affinity,
  40. nvec * sizeof(*desc->affinity), GFP_KERNEL);
  41. if (!desc->affinity) {
  42. kfree(desc);
  43. return NULL;
  44. }
  45. }
  46. return desc;
  47. }
  48. void free_msi_entry(struct msi_desc *entry)
  49. {
  50. kfree(entry->affinity);
  51. kfree(entry);
  52. }
  53. void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
  54. {
  55. *msg = entry->msg;
  56. }
  57. void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
  58. {
  59. struct msi_desc *entry = irq_get_msi_desc(irq);
  60. __get_cached_msi_msg(entry, msg);
  61. }
  62. EXPORT_SYMBOL_GPL(get_cached_msi_msg);
  63. #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
  64. static inline void irq_chip_write_msi_msg(struct irq_data *data,
  65. struct msi_msg *msg)
  66. {
  67. data->chip->irq_write_msi_msg(data, msg);
  68. }
  69. /**
  70. * msi_domain_set_affinity - Generic affinity setter function for MSI domains
  71. * @irq_data: The irq data associated to the interrupt
  72. * @mask: The affinity mask to set
  73. * @force: Flag to enforce setting (disable online checks)
  74. *
  75. * Intended to be used by MSI interrupt controllers which are
  76. * implemented with hierarchical domains.
  77. */
  78. int msi_domain_set_affinity(struct irq_data *irq_data,
  79. const struct cpumask *mask, bool force)
  80. {
  81. struct irq_data *parent = irq_data->parent_data;
  82. struct msi_msg msg;
  83. int ret;
  84. ret = parent->chip->irq_set_affinity(parent, mask, force);
  85. if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
  86. BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
  87. irq_chip_write_msi_msg(irq_data, &msg);
  88. }
  89. return ret;
  90. }
  91. static void msi_domain_activate(struct irq_domain *domain,
  92. struct irq_data *irq_data)
  93. {
  94. struct msi_msg msg;
  95. BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg));
  96. irq_chip_write_msi_msg(irq_data, &msg);
  97. }
  98. static void msi_domain_deactivate(struct irq_domain *domain,
  99. struct irq_data *irq_data)
  100. {
  101. struct msi_msg msg;
  102. memset(&msg, 0, sizeof(msg));
  103. irq_chip_write_msi_msg(irq_data, &msg);
  104. }
  105. static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
  106. unsigned int nr_irqs, void *arg)
  107. {
  108. struct msi_domain_info *info = domain->host_data;
  109. struct msi_domain_ops *ops = info->ops;
  110. irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
  111. int i, ret;
  112. if (irq_find_mapping(domain, hwirq) > 0)
  113. return -EEXIST;
  114. if (domain->parent) {
  115. ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
  116. if (ret < 0)
  117. return ret;
  118. }
  119. for (i = 0; i < nr_irqs; i++) {
  120. ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
  121. if (ret < 0) {
  122. if (ops->msi_free) {
  123. for (i--; i > 0; i--)
  124. ops->msi_free(domain, info, virq + i);
  125. }
  126. irq_domain_free_irqs_top(domain, virq, nr_irqs);
  127. return ret;
  128. }
  129. }
  130. return 0;
  131. }
  132. static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
  133. unsigned int nr_irqs)
  134. {
  135. struct msi_domain_info *info = domain->host_data;
  136. int i;
  137. if (info->ops->msi_free) {
  138. for (i = 0; i < nr_irqs; i++)
  139. info->ops->msi_free(domain, info, virq + i);
  140. }
  141. irq_domain_free_irqs_top(domain, virq, nr_irqs);
  142. }
  143. static const struct irq_domain_ops msi_domain_ops = {
  144. .alloc = msi_domain_alloc,
  145. .free = msi_domain_free,
  146. .activate = msi_domain_activate,
  147. .deactivate = msi_domain_deactivate,
  148. };
  149. #ifdef GENERIC_MSI_DOMAIN_OPS
  150. static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
  151. msi_alloc_info_t *arg)
  152. {
  153. return arg->hwirq;
  154. }
  155. static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
  156. int nvec, msi_alloc_info_t *arg)
  157. {
  158. memset(arg, 0, sizeof(*arg));
  159. return 0;
  160. }
  161. static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
  162. struct msi_desc *desc)
  163. {
  164. arg->desc = desc;
  165. }
  166. #else
  167. #define msi_domain_ops_get_hwirq NULL
  168. #define msi_domain_ops_prepare NULL
  169. #define msi_domain_ops_set_desc NULL
  170. #endif /* !GENERIC_MSI_DOMAIN_OPS */
  171. static int msi_domain_ops_init(struct irq_domain *domain,
  172. struct msi_domain_info *info,
  173. unsigned int virq, irq_hw_number_t hwirq,
  174. msi_alloc_info_t *arg)
  175. {
  176. irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
  177. info->chip_data);
  178. if (info->handler && info->handler_name) {
  179. __irq_set_handler(virq, info->handler, 0, info->handler_name);
  180. if (info->handler_data)
  181. irq_set_handler_data(virq, info->handler_data);
  182. }
  183. return 0;
  184. }
  185. static int msi_domain_ops_check(struct irq_domain *domain,
  186. struct msi_domain_info *info,
  187. struct device *dev)
  188. {
  189. return 0;
  190. }
  191. static struct msi_domain_ops msi_domain_ops_default = {
  192. .get_hwirq = msi_domain_ops_get_hwirq,
  193. .msi_init = msi_domain_ops_init,
  194. .msi_check = msi_domain_ops_check,
  195. .msi_prepare = msi_domain_ops_prepare,
  196. .set_desc = msi_domain_ops_set_desc,
  197. };
  198. static void msi_domain_update_dom_ops(struct msi_domain_info *info)
  199. {
  200. struct msi_domain_ops *ops = info->ops;
  201. if (ops == NULL) {
  202. info->ops = &msi_domain_ops_default;
  203. return;
  204. }
  205. if (ops->get_hwirq == NULL)
  206. ops->get_hwirq = msi_domain_ops_default.get_hwirq;
  207. if (ops->msi_init == NULL)
  208. ops->msi_init = msi_domain_ops_default.msi_init;
  209. if (ops->msi_check == NULL)
  210. ops->msi_check = msi_domain_ops_default.msi_check;
  211. if (ops->msi_prepare == NULL)
  212. ops->msi_prepare = msi_domain_ops_default.msi_prepare;
  213. if (ops->set_desc == NULL)
  214. ops->set_desc = msi_domain_ops_default.set_desc;
  215. }
  216. static void msi_domain_update_chip_ops(struct msi_domain_info *info)
  217. {
  218. struct irq_chip *chip = info->chip;
  219. BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
  220. if (!chip->irq_set_affinity)
  221. chip->irq_set_affinity = msi_domain_set_affinity;
  222. }
  223. /**
  224. * msi_create_irq_domain - Create a MSI interrupt domain
  225. * @fwnode: Optional fwnode of the interrupt controller
  226. * @info: MSI domain info
  227. * @parent: Parent irq domain
  228. */
  229. struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
  230. struct msi_domain_info *info,
  231. struct irq_domain *parent)
  232. {
  233. if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
  234. msi_domain_update_dom_ops(info);
  235. if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
  236. msi_domain_update_chip_ops(info);
  237. return irq_domain_create_hierarchy(parent, 0, 0, fwnode,
  238. &msi_domain_ops, info);
  239. }
  240. int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
  241. int nvec, msi_alloc_info_t *arg)
  242. {
  243. struct msi_domain_info *info = domain->host_data;
  244. struct msi_domain_ops *ops = info->ops;
  245. int ret;
  246. ret = ops->msi_check(domain, info, dev);
  247. if (ret == 0)
  248. ret = ops->msi_prepare(domain, dev, nvec, arg);
  249. return ret;
  250. }
  251. int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
  252. int virq, int nvec, msi_alloc_info_t *arg)
  253. {
  254. struct msi_domain_info *info = domain->host_data;
  255. struct msi_domain_ops *ops = info->ops;
  256. struct msi_desc *desc;
  257. int ret = 0;
  258. for_each_msi_entry(desc, dev) {
  259. /* Don't even try the multi-MSI brain damage. */
  260. if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
  261. ret = -EINVAL;
  262. break;
  263. }
  264. if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
  265. continue;
  266. ops->set_desc(arg, desc);
  267. /* Assumes the domain mutex is held! */
  268. ret = irq_domain_alloc_irqs_recursive(domain, virq, 1, arg);
  269. if (ret)
  270. break;
  271. irq_set_msi_desc_off(virq, 0, desc);
  272. }
  273. if (ret) {
  274. /* Mop up the damage */
  275. for_each_msi_entry(desc, dev) {
  276. if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
  277. continue;
  278. irq_domain_free_irqs_common(domain, desc->irq, 1);
  279. }
  280. }
  281. return ret;
  282. }
  283. /**
  284. * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
  285. * @domain: The domain to allocate from
  286. * @dev: Pointer to device struct of the device for which the interrupts
  287. * are allocated
  288. * @nvec: The number of interrupts to allocate
  289. *
  290. * Returns 0 on success or an error code.
  291. */
  292. int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
  293. int nvec)
  294. {
  295. struct msi_domain_info *info = domain->host_data;
  296. struct msi_domain_ops *ops = info->ops;
  297. msi_alloc_info_t arg;
  298. struct msi_desc *desc;
  299. int i, ret, virq;
  300. ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
  301. if (ret)
  302. return ret;
  303. for_each_msi_entry(desc, dev) {
  304. ops->set_desc(&arg, desc);
  305. virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
  306. dev_to_node(dev), &arg, false,
  307. desc->affinity);
  308. if (virq < 0) {
  309. ret = -ENOSPC;
  310. if (ops->handle_error)
  311. ret = ops->handle_error(domain, desc, ret);
  312. if (ops->msi_finish)
  313. ops->msi_finish(&arg, ret);
  314. return ret;
  315. }
  316. for (i = 0; i < desc->nvec_used; i++)
  317. irq_set_msi_desc_off(virq, i, desc);
  318. }
  319. if (ops->msi_finish)
  320. ops->msi_finish(&arg, 0);
  321. for_each_msi_entry(desc, dev) {
  322. virq = desc->irq;
  323. if (desc->nvec_used == 1)
  324. dev_dbg(dev, "irq %d for MSI\n", virq);
  325. else
  326. dev_dbg(dev, "irq [%d-%d] for MSI\n",
  327. virq, virq + desc->nvec_used - 1);
  328. /*
  329. * This flag is set by the PCI layer as we need to activate
  330. * the MSI entries before the PCI layer enables MSI in the
  331. * card. Otherwise the card latches a random msi message.
  332. */
  333. if (info->flags & MSI_FLAG_ACTIVATE_EARLY) {
  334. struct irq_data *irq_data;
  335. irq_data = irq_domain_get_irq_data(domain, desc->irq);
  336. irq_domain_activate_irq(irq_data);
  337. }
  338. }
  339. return 0;
  340. }
  341. /**
  342. * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
  343. * @domain: The domain to managing the interrupts
  344. * @dev: Pointer to device struct of the device for which the interrupts
  345. * are free
  346. */
  347. void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
  348. {
  349. struct msi_desc *desc;
  350. for_each_msi_entry(desc, dev) {
  351. /*
  352. * We might have failed to allocate an MSI early
  353. * enough that there is no IRQ associated to this
  354. * entry. If that's the case, don't do anything.
  355. */
  356. if (desc->irq) {
  357. irq_domain_free_irqs(desc->irq, desc->nvec_used);
  358. desc->irq = 0;
  359. }
  360. }
  361. }
  362. /**
  363. * msi_get_domain_info - Get the MSI interrupt domain info for @domain
  364. * @domain: The interrupt domain to retrieve data from
  365. *
  366. * Returns the pointer to the msi_domain_info stored in
  367. * @domain->host_data.
  368. */
  369. struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
  370. {
  371. return (struct msi_domain_info *)domain->host_data;
  372. }
  373. #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */