chip.c 30 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209
  1. /*
  2. * linux/kernel/irq/chip.c
  3. *
  4. * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  5. * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
  6. *
  7. * This file contains the core interrupt handling code, for irq-chip
  8. * based architectures.
  9. *
  10. * Detailed information is available in Documentation/DocBook/genericirq
  11. */
  12. #include <linux/irq.h>
  13. #include <linux/msi.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel_stat.h>
  17. #include <linux/irqdomain.h>
  18. #include <trace/events/irq.h>
  19. #include "internals.h"
  20. static irqreturn_t bad_chained_irq(int irq, void *dev_id)
  21. {
  22. WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
  23. return IRQ_NONE;
  24. }
  25. /*
  26. * Chained handlers should never call action on their IRQ. This default
  27. * action will emit warning if such thing happens.
  28. */
  29. struct irqaction chained_action = {
  30. .handler = bad_chained_irq,
  31. };
  32. /**
  33. * irq_set_chip - set the irq chip for an irq
  34. * @irq: irq number
  35. * @chip: pointer to irq chip description structure
  36. */
  37. int irq_set_chip(unsigned int irq, struct irq_chip *chip)
  38. {
  39. unsigned long flags;
  40. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  41. if (!desc)
  42. return -EINVAL;
  43. if (!chip)
  44. chip = &no_irq_chip;
  45. desc->irq_data.chip = chip;
  46. irq_put_desc_unlock(desc, flags);
  47. /*
  48. * For !CONFIG_SPARSE_IRQ make the irq show up in
  49. * allocated_irqs.
  50. */
  51. irq_mark_irq(irq);
  52. return 0;
  53. }
  54. EXPORT_SYMBOL(irq_set_chip);
  55. /**
  56. * irq_set_type - set the irq trigger type for an irq
  57. * @irq: irq number
  58. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  59. */
  60. int irq_set_irq_type(unsigned int irq, unsigned int type)
  61. {
  62. unsigned long flags;
  63. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  64. int ret = 0;
  65. if (!desc)
  66. return -EINVAL;
  67. ret = __irq_set_trigger(desc, type);
  68. irq_put_desc_busunlock(desc, flags);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL(irq_set_irq_type);
  72. /**
  73. * irq_set_handler_data - set irq handler data for an irq
  74. * @irq: Interrupt number
  75. * @data: Pointer to interrupt specific data
  76. *
  77. * Set the hardware irq controller data for an irq
  78. */
  79. int irq_set_handler_data(unsigned int irq, void *data)
  80. {
  81. unsigned long flags;
  82. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  83. if (!desc)
  84. return -EINVAL;
  85. desc->irq_common_data.handler_data = data;
  86. irq_put_desc_unlock(desc, flags);
  87. return 0;
  88. }
  89. EXPORT_SYMBOL(irq_set_handler_data);
  90. /**
  91. * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
  92. * @irq_base: Interrupt number base
  93. * @irq_offset: Interrupt number offset
  94. * @entry: Pointer to MSI descriptor data
  95. *
  96. * Set the MSI descriptor entry for an irq at offset
  97. */
  98. int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
  99. struct msi_desc *entry)
  100. {
  101. unsigned long flags;
  102. struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  103. if (!desc)
  104. return -EINVAL;
  105. desc->irq_common_data.msi_desc = entry;
  106. if (entry && !irq_offset)
  107. entry->irq = irq_base;
  108. irq_put_desc_unlock(desc, flags);
  109. return 0;
  110. }
  111. /**
  112. * irq_set_msi_desc - set MSI descriptor data for an irq
  113. * @irq: Interrupt number
  114. * @entry: Pointer to MSI descriptor data
  115. *
  116. * Set the MSI descriptor entry for an irq
  117. */
  118. int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
  119. {
  120. return irq_set_msi_desc_off(irq, 0, entry);
  121. }
  122. /**
  123. * irq_set_chip_data - set irq chip data for an irq
  124. * @irq: Interrupt number
  125. * @data: Pointer to chip specific data
  126. *
  127. * Set the hardware irq chip data for an irq
  128. */
  129. int irq_set_chip_data(unsigned int irq, void *data)
  130. {
  131. unsigned long flags;
  132. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  133. if (!desc)
  134. return -EINVAL;
  135. desc->irq_data.chip_data = data;
  136. irq_put_desc_unlock(desc, flags);
  137. return 0;
  138. }
  139. EXPORT_SYMBOL(irq_set_chip_data);
  140. struct irq_data *irq_get_irq_data(unsigned int irq)
  141. {
  142. struct irq_desc *desc = irq_to_desc(irq);
  143. return desc ? &desc->irq_data : NULL;
  144. }
  145. EXPORT_SYMBOL_GPL(irq_get_irq_data);
  146. static void irq_state_clr_disabled(struct irq_desc *desc)
  147. {
  148. irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
  149. }
  150. static void irq_state_set_disabled(struct irq_desc *desc)
  151. {
  152. irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
  153. }
  154. static void irq_state_clr_masked(struct irq_desc *desc)
  155. {
  156. irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
  157. }
  158. static void irq_state_set_masked(struct irq_desc *desc)
  159. {
  160. irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
  161. }
  162. int irq_startup(struct irq_desc *desc, bool resend)
  163. {
  164. int ret = 0;
  165. irq_state_clr_disabled(desc);
  166. desc->depth = 0;
  167. irq_domain_activate_irq(&desc->irq_data);
  168. if (desc->irq_data.chip->irq_startup) {
  169. ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
  170. irq_state_clr_masked(desc);
  171. } else {
  172. irq_enable(desc);
  173. }
  174. if (resend)
  175. check_irq_resend(desc);
  176. return ret;
  177. }
  178. void irq_shutdown(struct irq_desc *desc)
  179. {
  180. irq_state_set_disabled(desc);
  181. desc->depth = 1;
  182. if (desc->irq_data.chip->irq_shutdown)
  183. desc->irq_data.chip->irq_shutdown(&desc->irq_data);
  184. else if (desc->irq_data.chip->irq_disable)
  185. desc->irq_data.chip->irq_disable(&desc->irq_data);
  186. else
  187. desc->irq_data.chip->irq_mask(&desc->irq_data);
  188. irq_domain_deactivate_irq(&desc->irq_data);
  189. irq_state_set_masked(desc);
  190. }
  191. void irq_enable(struct irq_desc *desc)
  192. {
  193. irq_state_clr_disabled(desc);
  194. if (desc->irq_data.chip->irq_enable)
  195. desc->irq_data.chip->irq_enable(&desc->irq_data);
  196. else
  197. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  198. irq_state_clr_masked(desc);
  199. }
  200. /**
  201. * irq_disable - Mark interrupt disabled
  202. * @desc: irq descriptor which should be disabled
  203. *
  204. * If the chip does not implement the irq_disable callback, we
  205. * use a lazy disable approach. That means we mark the interrupt
  206. * disabled, but leave the hardware unmasked. That's an
  207. * optimization because we avoid the hardware access for the
  208. * common case where no interrupt happens after we marked it
  209. * disabled. If an interrupt happens, then the interrupt flow
  210. * handler masks the line at the hardware level and marks it
  211. * pending.
  212. *
  213. * If the interrupt chip does not implement the irq_disable callback,
  214. * a driver can disable the lazy approach for a particular irq line by
  215. * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
  216. * be used for devices which cannot disable the interrupt at the
  217. * device level under certain circumstances and have to use
  218. * disable_irq[_nosync] instead.
  219. */
  220. void irq_disable(struct irq_desc *desc)
  221. {
  222. irq_state_set_disabled(desc);
  223. if (desc->irq_data.chip->irq_disable) {
  224. desc->irq_data.chip->irq_disable(&desc->irq_data);
  225. irq_state_set_masked(desc);
  226. } else if (irq_settings_disable_unlazy(desc)) {
  227. mask_irq(desc);
  228. }
  229. }
  230. void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
  231. {
  232. if (desc->irq_data.chip->irq_enable)
  233. desc->irq_data.chip->irq_enable(&desc->irq_data);
  234. else
  235. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  236. cpumask_set_cpu(cpu, desc->percpu_enabled);
  237. }
  238. void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
  239. {
  240. if (desc->irq_data.chip->irq_disable)
  241. desc->irq_data.chip->irq_disable(&desc->irq_data);
  242. else
  243. desc->irq_data.chip->irq_mask(&desc->irq_data);
  244. cpumask_clear_cpu(cpu, desc->percpu_enabled);
  245. }
  246. static inline void mask_ack_irq(struct irq_desc *desc)
  247. {
  248. if (desc->irq_data.chip->irq_mask_ack)
  249. desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
  250. else {
  251. desc->irq_data.chip->irq_mask(&desc->irq_data);
  252. if (desc->irq_data.chip->irq_ack)
  253. desc->irq_data.chip->irq_ack(&desc->irq_data);
  254. }
  255. irq_state_set_masked(desc);
  256. }
  257. void mask_irq(struct irq_desc *desc)
  258. {
  259. if (desc->irq_data.chip->irq_mask) {
  260. desc->irq_data.chip->irq_mask(&desc->irq_data);
  261. irq_state_set_masked(desc);
  262. }
  263. }
  264. void unmask_irq(struct irq_desc *desc)
  265. {
  266. if (desc->irq_data.chip->irq_unmask) {
  267. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  268. irq_state_clr_masked(desc);
  269. }
  270. }
  271. void unmask_threaded_irq(struct irq_desc *desc)
  272. {
  273. struct irq_chip *chip = desc->irq_data.chip;
  274. if (chip->flags & IRQCHIP_EOI_THREADED)
  275. chip->irq_eoi(&desc->irq_data);
  276. if (chip->irq_unmask) {
  277. chip->irq_unmask(&desc->irq_data);
  278. irq_state_clr_masked(desc);
  279. }
  280. }
  281. /*
  282. * handle_nested_irq - Handle a nested irq from a irq thread
  283. * @irq: the interrupt number
  284. *
  285. * Handle interrupts which are nested into a threaded interrupt
  286. * handler. The handler function is called inside the calling
  287. * threads context.
  288. */
  289. void handle_nested_irq(unsigned int irq)
  290. {
  291. struct irq_desc *desc = irq_to_desc(irq);
  292. struct irqaction *action;
  293. irqreturn_t action_ret;
  294. might_sleep();
  295. raw_spin_lock_irq(&desc->lock);
  296. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  297. action = desc->action;
  298. if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
  299. desc->istate |= IRQS_PENDING;
  300. goto out_unlock;
  301. }
  302. kstat_incr_irqs_this_cpu(desc);
  303. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  304. raw_spin_unlock_irq(&desc->lock);
  305. action_ret = action->thread_fn(action->irq, action->dev_id);
  306. if (!noirqdebug)
  307. note_interrupt(desc, action_ret);
  308. raw_spin_lock_irq(&desc->lock);
  309. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  310. out_unlock:
  311. raw_spin_unlock_irq(&desc->lock);
  312. }
  313. EXPORT_SYMBOL_GPL(handle_nested_irq);
  314. static bool irq_check_poll(struct irq_desc *desc)
  315. {
  316. if (!(desc->istate & IRQS_POLL_INPROGRESS))
  317. return false;
  318. return irq_wait_for_poll(desc);
  319. }
  320. static bool irq_may_run(struct irq_desc *desc)
  321. {
  322. unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
  323. /*
  324. * If the interrupt is not in progress and is not an armed
  325. * wakeup interrupt, proceed.
  326. */
  327. if (!irqd_has_set(&desc->irq_data, mask))
  328. return true;
  329. /*
  330. * If the interrupt is an armed wakeup source, mark it pending
  331. * and suspended, disable it and notify the pm core about the
  332. * event.
  333. */
  334. if (irq_pm_check_wakeup(desc))
  335. return false;
  336. /*
  337. * Handle a potential concurrent poll on a different core.
  338. */
  339. return irq_check_poll(desc);
  340. }
  341. /**
  342. * handle_simple_irq - Simple and software-decoded IRQs.
  343. * @desc: the interrupt description structure for this irq
  344. *
  345. * Simple interrupts are either sent from a demultiplexing interrupt
  346. * handler or come from hardware, where no interrupt hardware control
  347. * is necessary.
  348. *
  349. * Note: The caller is expected to handle the ack, clear, mask and
  350. * unmask issues if necessary.
  351. */
  352. void handle_simple_irq(struct irq_desc *desc)
  353. {
  354. raw_spin_lock(&desc->lock);
  355. if (!irq_may_run(desc))
  356. goto out_unlock;
  357. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  358. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  359. desc->istate |= IRQS_PENDING;
  360. goto out_unlock;
  361. }
  362. kstat_incr_irqs_this_cpu(desc);
  363. handle_irq_event(desc);
  364. out_unlock:
  365. raw_spin_unlock(&desc->lock);
  366. }
  367. EXPORT_SYMBOL_GPL(handle_simple_irq);
  368. /**
  369. * handle_untracked_irq - Simple and software-decoded IRQs.
  370. * @desc: the interrupt description structure for this irq
  371. *
  372. * Untracked interrupts are sent from a demultiplexing interrupt
  373. * handler when the demultiplexer does not know which device it its
  374. * multiplexed irq domain generated the interrupt. IRQ's handled
  375. * through here are not subjected to stats tracking, randomness, or
  376. * spurious interrupt detection.
  377. *
  378. * Note: Like handle_simple_irq, the caller is expected to handle
  379. * the ack, clear, mask and unmask issues if necessary.
  380. */
  381. void handle_untracked_irq(struct irq_desc *desc)
  382. {
  383. unsigned int flags = 0;
  384. raw_spin_lock(&desc->lock);
  385. if (!irq_may_run(desc))
  386. goto out_unlock;
  387. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  388. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  389. desc->istate |= IRQS_PENDING;
  390. goto out_unlock;
  391. }
  392. desc->istate &= ~IRQS_PENDING;
  393. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  394. raw_spin_unlock(&desc->lock);
  395. __handle_irq_event_percpu(desc, &flags);
  396. raw_spin_lock(&desc->lock);
  397. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  398. out_unlock:
  399. raw_spin_unlock(&desc->lock);
  400. }
  401. EXPORT_SYMBOL_GPL(handle_untracked_irq);
  402. /*
  403. * Called unconditionally from handle_level_irq() and only for oneshot
  404. * interrupts from handle_fasteoi_irq()
  405. */
  406. static void cond_unmask_irq(struct irq_desc *desc)
  407. {
  408. /*
  409. * We need to unmask in the following cases:
  410. * - Standard level irq (IRQF_ONESHOT is not set)
  411. * - Oneshot irq which did not wake the thread (caused by a
  412. * spurious interrupt or a primary handler handling it
  413. * completely).
  414. */
  415. if (!irqd_irq_disabled(&desc->irq_data) &&
  416. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
  417. unmask_irq(desc);
  418. }
  419. /**
  420. * handle_level_irq - Level type irq handler
  421. * @desc: the interrupt description structure for this irq
  422. *
  423. * Level type interrupts are active as long as the hardware line has
  424. * the active level. This may require to mask the interrupt and unmask
  425. * it after the associated handler has acknowledged the device, so the
  426. * interrupt line is back to inactive.
  427. */
  428. void handle_level_irq(struct irq_desc *desc)
  429. {
  430. raw_spin_lock(&desc->lock);
  431. mask_ack_irq(desc);
  432. if (!irq_may_run(desc))
  433. goto out_unlock;
  434. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  435. /*
  436. * If its disabled or no action available
  437. * keep it masked and get out of here
  438. */
  439. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  440. desc->istate |= IRQS_PENDING;
  441. goto out_unlock;
  442. }
  443. kstat_incr_irqs_this_cpu(desc);
  444. handle_irq_event(desc);
  445. cond_unmask_irq(desc);
  446. out_unlock:
  447. raw_spin_unlock(&desc->lock);
  448. }
  449. EXPORT_SYMBOL_GPL(handle_level_irq);
  450. #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
  451. static inline void preflow_handler(struct irq_desc *desc)
  452. {
  453. if (desc->preflow_handler)
  454. desc->preflow_handler(&desc->irq_data);
  455. }
  456. #else
  457. static inline void preflow_handler(struct irq_desc *desc) { }
  458. #endif
  459. static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
  460. {
  461. if (!(desc->istate & IRQS_ONESHOT)) {
  462. chip->irq_eoi(&desc->irq_data);
  463. return;
  464. }
  465. /*
  466. * We need to unmask in the following cases:
  467. * - Oneshot irq which did not wake the thread (caused by a
  468. * spurious interrupt or a primary handler handling it
  469. * completely).
  470. */
  471. if (!irqd_irq_disabled(&desc->irq_data) &&
  472. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
  473. chip->irq_eoi(&desc->irq_data);
  474. unmask_irq(desc);
  475. } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
  476. chip->irq_eoi(&desc->irq_data);
  477. }
  478. }
  479. /**
  480. * handle_fasteoi_irq - irq handler for transparent controllers
  481. * @desc: the interrupt description structure for this irq
  482. *
  483. * Only a single callback will be issued to the chip: an ->eoi()
  484. * call when the interrupt has been serviced. This enables support
  485. * for modern forms of interrupt handlers, which handle the flow
  486. * details in hardware, transparently.
  487. */
  488. void handle_fasteoi_irq(struct irq_desc *desc)
  489. {
  490. struct irq_chip *chip = desc->irq_data.chip;
  491. raw_spin_lock(&desc->lock);
  492. if (!irq_may_run(desc))
  493. goto out;
  494. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  495. /*
  496. * If its disabled or no action available
  497. * then mask it and get out of here:
  498. */
  499. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  500. desc->istate |= IRQS_PENDING;
  501. mask_irq(desc);
  502. goto out;
  503. }
  504. kstat_incr_irqs_this_cpu(desc);
  505. if (desc->istate & IRQS_ONESHOT)
  506. mask_irq(desc);
  507. preflow_handler(desc);
  508. handle_irq_event(desc);
  509. cond_unmask_eoi_irq(desc, chip);
  510. raw_spin_unlock(&desc->lock);
  511. return;
  512. out:
  513. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  514. chip->irq_eoi(&desc->irq_data);
  515. raw_spin_unlock(&desc->lock);
  516. }
  517. EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
  518. /**
  519. * handle_edge_irq - edge type IRQ handler
  520. * @desc: the interrupt description structure for this irq
  521. *
  522. * Interrupt occures on the falling and/or rising edge of a hardware
  523. * signal. The occurrence is latched into the irq controller hardware
  524. * and must be acked in order to be reenabled. After the ack another
  525. * interrupt can happen on the same source even before the first one
  526. * is handled by the associated event handler. If this happens it
  527. * might be necessary to disable (mask) the interrupt depending on the
  528. * controller hardware. This requires to reenable the interrupt inside
  529. * of the loop which handles the interrupts which have arrived while
  530. * the handler was running. If all pending interrupts are handled, the
  531. * loop is left.
  532. */
  533. void handle_edge_irq(struct irq_desc *desc)
  534. {
  535. raw_spin_lock(&desc->lock);
  536. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  537. if (!irq_may_run(desc)) {
  538. desc->istate |= IRQS_PENDING;
  539. mask_ack_irq(desc);
  540. goto out_unlock;
  541. }
  542. /*
  543. * If its disabled or no action available then mask it and get
  544. * out of here.
  545. */
  546. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  547. desc->istate |= IRQS_PENDING;
  548. mask_ack_irq(desc);
  549. goto out_unlock;
  550. }
  551. kstat_incr_irqs_this_cpu(desc);
  552. /* Start handling the irq */
  553. desc->irq_data.chip->irq_ack(&desc->irq_data);
  554. do {
  555. if (unlikely(!desc->action)) {
  556. mask_irq(desc);
  557. goto out_unlock;
  558. }
  559. /*
  560. * When another irq arrived while we were handling
  561. * one, we could have masked the irq.
  562. * Renable it, if it was not disabled in meantime.
  563. */
  564. if (unlikely(desc->istate & IRQS_PENDING)) {
  565. if (!irqd_irq_disabled(&desc->irq_data) &&
  566. irqd_irq_masked(&desc->irq_data))
  567. unmask_irq(desc);
  568. }
  569. handle_irq_event(desc);
  570. } while ((desc->istate & IRQS_PENDING) &&
  571. !irqd_irq_disabled(&desc->irq_data));
  572. out_unlock:
  573. raw_spin_unlock(&desc->lock);
  574. }
  575. EXPORT_SYMBOL(handle_edge_irq);
  576. #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
  577. /**
  578. * handle_edge_eoi_irq - edge eoi type IRQ handler
  579. * @desc: the interrupt description structure for this irq
  580. *
  581. * Similar as the above handle_edge_irq, but using eoi and w/o the
  582. * mask/unmask logic.
  583. */
  584. void handle_edge_eoi_irq(struct irq_desc *desc)
  585. {
  586. struct irq_chip *chip = irq_desc_get_chip(desc);
  587. raw_spin_lock(&desc->lock);
  588. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  589. if (!irq_may_run(desc)) {
  590. desc->istate |= IRQS_PENDING;
  591. goto out_eoi;
  592. }
  593. /*
  594. * If its disabled or no action available then mask it and get
  595. * out of here.
  596. */
  597. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  598. desc->istate |= IRQS_PENDING;
  599. goto out_eoi;
  600. }
  601. kstat_incr_irqs_this_cpu(desc);
  602. do {
  603. if (unlikely(!desc->action))
  604. goto out_eoi;
  605. handle_irq_event(desc);
  606. } while ((desc->istate & IRQS_PENDING) &&
  607. !irqd_irq_disabled(&desc->irq_data));
  608. out_eoi:
  609. chip->irq_eoi(&desc->irq_data);
  610. raw_spin_unlock(&desc->lock);
  611. }
  612. #endif
  613. /**
  614. * handle_percpu_irq - Per CPU local irq handler
  615. * @desc: the interrupt description structure for this irq
  616. *
  617. * Per CPU interrupts on SMP machines without locking requirements
  618. */
  619. void handle_percpu_irq(struct irq_desc *desc)
  620. {
  621. struct irq_chip *chip = irq_desc_get_chip(desc);
  622. kstat_incr_irqs_this_cpu(desc);
  623. if (chip->irq_ack)
  624. chip->irq_ack(&desc->irq_data);
  625. handle_irq_event_percpu(desc);
  626. if (chip->irq_eoi)
  627. chip->irq_eoi(&desc->irq_data);
  628. }
  629. /**
  630. * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
  631. * @desc: the interrupt description structure for this irq
  632. *
  633. * Per CPU interrupts on SMP machines without locking requirements. Same as
  634. * handle_percpu_irq() above but with the following extras:
  635. *
  636. * action->percpu_dev_id is a pointer to percpu variables which
  637. * contain the real device id for the cpu on which this handler is
  638. * called
  639. */
  640. void handle_percpu_devid_irq(struct irq_desc *desc)
  641. {
  642. struct irq_chip *chip = irq_desc_get_chip(desc);
  643. struct irqaction *action = desc->action;
  644. unsigned int irq = irq_desc_get_irq(desc);
  645. irqreturn_t res;
  646. kstat_incr_irqs_this_cpu(desc);
  647. if (chip->irq_ack)
  648. chip->irq_ack(&desc->irq_data);
  649. if (likely(action)) {
  650. trace_irq_handler_entry(irq, action);
  651. res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
  652. trace_irq_handler_exit(irq, action, res);
  653. } else {
  654. unsigned int cpu = smp_processor_id();
  655. bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
  656. if (enabled)
  657. irq_percpu_disable(desc, cpu);
  658. pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
  659. enabled ? " and unmasked" : "", irq, cpu);
  660. }
  661. if (chip->irq_eoi)
  662. chip->irq_eoi(&desc->irq_data);
  663. }
  664. static void
  665. __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
  666. int is_chained, const char *name)
  667. {
  668. if (!handle) {
  669. handle = handle_bad_irq;
  670. } else {
  671. struct irq_data *irq_data = &desc->irq_data;
  672. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  673. /*
  674. * With hierarchical domains we might run into a
  675. * situation where the outermost chip is not yet set
  676. * up, but the inner chips are there. Instead of
  677. * bailing we install the handler, but obviously we
  678. * cannot enable/startup the interrupt at this point.
  679. */
  680. while (irq_data) {
  681. if (irq_data->chip != &no_irq_chip)
  682. break;
  683. /*
  684. * Bail out if the outer chip is not set up
  685. * and the interrrupt supposed to be started
  686. * right away.
  687. */
  688. if (WARN_ON(is_chained))
  689. return;
  690. /* Try the parent */
  691. irq_data = irq_data->parent_data;
  692. }
  693. #endif
  694. if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
  695. return;
  696. }
  697. /* Uninstall? */
  698. if (handle == handle_bad_irq) {
  699. if (desc->irq_data.chip != &no_irq_chip)
  700. mask_ack_irq(desc);
  701. irq_state_set_disabled(desc);
  702. if (is_chained)
  703. desc->action = NULL;
  704. desc->depth = 1;
  705. }
  706. desc->handle_irq = handle;
  707. desc->name = name;
  708. if (handle != handle_bad_irq && is_chained) {
  709. unsigned int type = irqd_get_trigger_type(&desc->irq_data);
  710. /*
  711. * We're about to start this interrupt immediately,
  712. * hence the need to set the trigger configuration.
  713. * But the .set_type callback may have overridden the
  714. * flow handler, ignoring that we're dealing with a
  715. * chained interrupt. Reset it immediately because we
  716. * do know better.
  717. */
  718. if (type != IRQ_TYPE_NONE) {
  719. __irq_set_trigger(desc, type);
  720. desc->handle_irq = handle;
  721. }
  722. irq_settings_set_noprobe(desc);
  723. irq_settings_set_norequest(desc);
  724. irq_settings_set_nothread(desc);
  725. desc->action = &chained_action;
  726. irq_startup(desc, true);
  727. }
  728. }
  729. void
  730. __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
  731. const char *name)
  732. {
  733. unsigned long flags;
  734. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  735. if (!desc)
  736. return;
  737. __irq_do_set_handler(desc, handle, is_chained, name);
  738. irq_put_desc_busunlock(desc, flags);
  739. }
  740. EXPORT_SYMBOL_GPL(__irq_set_handler);
  741. void
  742. irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
  743. void *data)
  744. {
  745. unsigned long flags;
  746. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  747. if (!desc)
  748. return;
  749. desc->irq_common_data.handler_data = data;
  750. __irq_do_set_handler(desc, handle, 1, NULL);
  751. irq_put_desc_busunlock(desc, flags);
  752. }
  753. EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
  754. void
  755. irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
  756. irq_flow_handler_t handle, const char *name)
  757. {
  758. irq_set_chip(irq, chip);
  759. __irq_set_handler(irq, handle, 0, name);
  760. }
  761. EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
  762. void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
  763. {
  764. unsigned long flags, trigger, tmp;
  765. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  766. if (!desc)
  767. return;
  768. irq_settings_clr_and_set(desc, clr, set);
  769. trigger = irqd_get_trigger_type(&desc->irq_data);
  770. irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
  771. IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
  772. if (irq_settings_has_no_balance_set(desc))
  773. irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
  774. if (irq_settings_is_per_cpu(desc))
  775. irqd_set(&desc->irq_data, IRQD_PER_CPU);
  776. if (irq_settings_can_move_pcntxt(desc))
  777. irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
  778. if (irq_settings_is_level(desc))
  779. irqd_set(&desc->irq_data, IRQD_LEVEL);
  780. tmp = irq_settings_get_trigger_mask(desc);
  781. if (tmp != IRQ_TYPE_NONE)
  782. trigger = tmp;
  783. irqd_set(&desc->irq_data, trigger);
  784. irq_put_desc_unlock(desc, flags);
  785. }
  786. EXPORT_SYMBOL_GPL(irq_modify_status);
  787. /**
  788. * irq_cpu_online - Invoke all irq_cpu_online functions.
  789. *
  790. * Iterate through all irqs and invoke the chip.irq_cpu_online()
  791. * for each.
  792. */
  793. void irq_cpu_online(void)
  794. {
  795. struct irq_desc *desc;
  796. struct irq_chip *chip;
  797. unsigned long flags;
  798. unsigned int irq;
  799. for_each_active_irq(irq) {
  800. desc = irq_to_desc(irq);
  801. if (!desc)
  802. continue;
  803. raw_spin_lock_irqsave(&desc->lock, flags);
  804. chip = irq_data_get_irq_chip(&desc->irq_data);
  805. if (chip && chip->irq_cpu_online &&
  806. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  807. !irqd_irq_disabled(&desc->irq_data)))
  808. chip->irq_cpu_online(&desc->irq_data);
  809. raw_spin_unlock_irqrestore(&desc->lock, flags);
  810. }
  811. }
  812. /**
  813. * irq_cpu_offline - Invoke all irq_cpu_offline functions.
  814. *
  815. * Iterate through all irqs and invoke the chip.irq_cpu_offline()
  816. * for each.
  817. */
  818. void irq_cpu_offline(void)
  819. {
  820. struct irq_desc *desc;
  821. struct irq_chip *chip;
  822. unsigned long flags;
  823. unsigned int irq;
  824. for_each_active_irq(irq) {
  825. desc = irq_to_desc(irq);
  826. if (!desc)
  827. continue;
  828. raw_spin_lock_irqsave(&desc->lock, flags);
  829. chip = irq_data_get_irq_chip(&desc->irq_data);
  830. if (chip && chip->irq_cpu_offline &&
  831. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  832. !irqd_irq_disabled(&desc->irq_data)))
  833. chip->irq_cpu_offline(&desc->irq_data);
  834. raw_spin_unlock_irqrestore(&desc->lock, flags);
  835. }
  836. }
  837. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  838. /**
  839. * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
  840. * NULL)
  841. * @data: Pointer to interrupt specific data
  842. */
  843. void irq_chip_enable_parent(struct irq_data *data)
  844. {
  845. data = data->parent_data;
  846. if (data->chip->irq_enable)
  847. data->chip->irq_enable(data);
  848. else
  849. data->chip->irq_unmask(data);
  850. }
  851. /**
  852. * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
  853. * NULL)
  854. * @data: Pointer to interrupt specific data
  855. */
  856. void irq_chip_disable_parent(struct irq_data *data)
  857. {
  858. data = data->parent_data;
  859. if (data->chip->irq_disable)
  860. data->chip->irq_disable(data);
  861. else
  862. data->chip->irq_mask(data);
  863. }
  864. /**
  865. * irq_chip_ack_parent - Acknowledge the parent interrupt
  866. * @data: Pointer to interrupt specific data
  867. */
  868. void irq_chip_ack_parent(struct irq_data *data)
  869. {
  870. data = data->parent_data;
  871. data->chip->irq_ack(data);
  872. }
  873. EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
  874. /**
  875. * irq_chip_mask_parent - Mask the parent interrupt
  876. * @data: Pointer to interrupt specific data
  877. */
  878. void irq_chip_mask_parent(struct irq_data *data)
  879. {
  880. data = data->parent_data;
  881. data->chip->irq_mask(data);
  882. }
  883. EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
  884. /**
  885. * irq_chip_unmask_parent - Unmask the parent interrupt
  886. * @data: Pointer to interrupt specific data
  887. */
  888. void irq_chip_unmask_parent(struct irq_data *data)
  889. {
  890. data = data->parent_data;
  891. data->chip->irq_unmask(data);
  892. }
  893. EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
  894. /**
  895. * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
  896. * @data: Pointer to interrupt specific data
  897. */
  898. void irq_chip_eoi_parent(struct irq_data *data)
  899. {
  900. data = data->parent_data;
  901. data->chip->irq_eoi(data);
  902. }
  903. EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
  904. /**
  905. * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
  906. * @data: Pointer to interrupt specific data
  907. * @dest: The affinity mask to set
  908. * @force: Flag to enforce setting (disable online checks)
  909. *
  910. * Conditinal, as the underlying parent chip might not implement it.
  911. */
  912. int irq_chip_set_affinity_parent(struct irq_data *data,
  913. const struct cpumask *dest, bool force)
  914. {
  915. data = data->parent_data;
  916. if (data->chip->irq_set_affinity)
  917. return data->chip->irq_set_affinity(data, dest, force);
  918. return -ENOSYS;
  919. }
  920. /**
  921. * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
  922. * @data: Pointer to interrupt specific data
  923. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  924. *
  925. * Conditional, as the underlying parent chip might not implement it.
  926. */
  927. int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
  928. {
  929. data = data->parent_data;
  930. if (data->chip->irq_set_type)
  931. return data->chip->irq_set_type(data, type);
  932. return -ENOSYS;
  933. }
  934. EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
  935. /**
  936. * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
  937. * @data: Pointer to interrupt specific data
  938. *
  939. * Iterate through the domain hierarchy of the interrupt and check
  940. * whether a hw retrigger function exists. If yes, invoke it.
  941. */
  942. int irq_chip_retrigger_hierarchy(struct irq_data *data)
  943. {
  944. for (data = data->parent_data; data; data = data->parent_data)
  945. if (data->chip && data->chip->irq_retrigger)
  946. return data->chip->irq_retrigger(data);
  947. return 0;
  948. }
  949. /**
  950. * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
  951. * @data: Pointer to interrupt specific data
  952. * @vcpu_info: The vcpu affinity information
  953. */
  954. int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
  955. {
  956. data = data->parent_data;
  957. if (data->chip->irq_set_vcpu_affinity)
  958. return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
  959. return -ENOSYS;
  960. }
  961. /**
  962. * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
  963. * @data: Pointer to interrupt specific data
  964. * @on: Whether to set or reset the wake-up capability of this irq
  965. *
  966. * Conditional, as the underlying parent chip might not implement it.
  967. */
  968. int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
  969. {
  970. data = data->parent_data;
  971. if (data->chip->irq_set_wake)
  972. return data->chip->irq_set_wake(data, on);
  973. return -ENOSYS;
  974. }
  975. #endif
  976. /**
  977. * irq_chip_compose_msi_msg - Componse msi message for a irq chip
  978. * @data: Pointer to interrupt specific data
  979. * @msg: Pointer to the MSI message
  980. *
  981. * For hierarchical domains we find the first chip in the hierarchy
  982. * which implements the irq_compose_msi_msg callback. For non
  983. * hierarchical we use the top level chip.
  984. */
  985. int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  986. {
  987. struct irq_data *pos = NULL;
  988. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  989. for (; data; data = data->parent_data)
  990. #endif
  991. if (data->chip && data->chip->irq_compose_msi_msg)
  992. pos = data;
  993. if (!pos)
  994. return -ENOSYS;
  995. pos->chip->irq_compose_msi_msg(pos, msg);
  996. return 0;
  997. }
  998. /**
  999. * irq_chip_pm_get - Enable power for an IRQ chip
  1000. * @data: Pointer to interrupt specific data
  1001. *
  1002. * Enable the power to the IRQ chip referenced by the interrupt data
  1003. * structure.
  1004. */
  1005. int irq_chip_pm_get(struct irq_data *data)
  1006. {
  1007. int retval;
  1008. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
  1009. retval = pm_runtime_get_sync(data->chip->parent_device);
  1010. if (retval < 0) {
  1011. pm_runtime_put_noidle(data->chip->parent_device);
  1012. return retval;
  1013. }
  1014. }
  1015. return 0;
  1016. }
  1017. /**
  1018. * irq_chip_pm_put - Disable power for an IRQ chip
  1019. * @data: Pointer to interrupt specific data
  1020. *
  1021. * Disable the power to the IRQ chip referenced by the interrupt data
  1022. * structure, belongs. Note that power will only be disabled, once this
  1023. * function has been called for all IRQs that have called irq_chip_pm_get().
  1024. */
  1025. int irq_chip_pm_put(struct irq_data *data)
  1026. {
  1027. int retval = 0;
  1028. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
  1029. retval = pm_runtime_put(data->chip->parent_device);
  1030. return (retval < 0) ? retval : 0;
  1031. }