opa_port_info.h 15 KB

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  1. /*
  2. * Copyright (c) 2014 Intel Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #if !defined(OPA_PORT_INFO_H)
  33. #define OPA_PORT_INFO_H
  34. #define OPA_PORT_LINK_MODE_NOP 0 /* No change */
  35. #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
  36. #define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */
  37. #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */
  38. #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
  39. #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
  40. #define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */
  41. #define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */
  42. #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
  43. #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
  44. #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
  45. #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
  46. /* Link Down / Neighbor Link Down Reason; indicated as follows: */
  47. #define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */
  48. #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1
  49. #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
  50. #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3
  51. #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
  52. #define OPA_LINKDOWN_REASON_BAD_SLID 5
  53. #define OPA_LINKDOWN_REASON_BAD_DLID 6
  54. #define OPA_LINKDOWN_REASON_BAD_L2 7
  55. #define OPA_LINKDOWN_REASON_BAD_SC 8
  56. #define OPA_LINKDOWN_REASON_RCV_ERROR_8 9
  57. #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
  58. #define OPA_LINKDOWN_REASON_RCV_ERROR_10 11
  59. #define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12
  60. #define OPA_LINKDOWN_REASON_PREEMPT_VL15 13
  61. #define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14
  62. #define OPA_LINKDOWN_REASON_RCV_ERROR_14 15
  63. #define OPA_LINKDOWN_REASON_RCV_ERROR_15 16
  64. #define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17
  65. #define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18
  66. #define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19
  67. #define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20
  68. #define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21
  69. #define OPA_LINKDOWN_REASON_BAD_PREEMPT 22
  70. #define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23
  71. #define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24
  72. #define OPA_LINKDOWN_REASON_RCV_ERROR_24 25
  73. #define OPA_LINKDOWN_REASON_RCV_ERROR_25 26
  74. #define OPA_LINKDOWN_REASON_RCV_ERROR_26 27
  75. #define OPA_LINKDOWN_REASON_RCV_ERROR_27 28
  76. #define OPA_LINKDOWN_REASON_RCV_ERROR_28 29
  77. #define OPA_LINKDOWN_REASON_RCV_ERROR_29 30
  78. #define OPA_LINKDOWN_REASON_RCV_ERROR_30 31
  79. #define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32
  80. #define OPA_LINKDOWN_REASON_UNKNOWN 33
  81. /* 34 -reserved */
  82. #define OPA_LINKDOWN_REASON_REBOOT 35
  83. #define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36
  84. /* 37-38 reserved */
  85. #define OPA_LINKDOWN_REASON_FM_BOUNCE 39
  86. #define OPA_LINKDOWN_REASON_SPEED_POLICY 40
  87. #define OPA_LINKDOWN_REASON_WIDTH_POLICY 41
  88. /* 42-48 reserved */
  89. #define OPA_LINKDOWN_REASON_DISCONNECTED 49
  90. #define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50
  91. #define OPA_LINKDOWN_REASON_NOT_INSTALLED 51
  92. #define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52
  93. /* 53 reserved */
  94. #define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54
  95. /* 55 reserved */
  96. #define OPA_LINKDOWN_REASON_POWER_POLICY 56
  97. #define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57
  98. #define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58
  99. /* 59 reserved */
  100. #define OPA_LINKDOWN_REASON_SWITCH_MGMT 60
  101. #define OPA_LINKDOWN_REASON_SMA_DISABLED 61
  102. /* 62 reserved */
  103. #define OPA_LINKDOWN_REASON_TRANSIENT 63
  104. /* 64-255 reserved */
  105. /* OPA Link Init reason; indicated as follows: */
  106. /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
  107. #define OPA_LINKINIT_REASON_NOP 0
  108. #define OPA_LINKINIT_REASON_LINKUP (1 << 4)
  109. #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
  110. #define OPA_LINKINIT_REASON_CLEAR (8 << 4)
  111. #define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4)
  112. #define OPA_LINKINIT_QUARANTINED (9 << 4)
  113. #define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4)
  114. #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
  115. #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
  116. #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
  117. #define OPA_LINK_WIDTH_1X 0x0001
  118. #define OPA_LINK_WIDTH_2X 0x0002
  119. #define OPA_LINK_WIDTH_3X 0x0004
  120. #define OPA_LINK_WIDTH_4X 0x0008
  121. #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7)
  122. #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6)
  123. #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
  124. #define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4)
  125. #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3)
  126. /* reserved (1 << 2) */
  127. #define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1)
  128. #define OPA_CAP_MASK3_IsVLrSupported (1 << 0)
  129. /**
  130. * new MTU values
  131. */
  132. enum {
  133. OPA_MTU_8192 = 6,
  134. OPA_MTU_10240 = 7,
  135. };
  136. enum {
  137. OPA_PORT_PHYS_CONF_DISCONNECTED = 0,
  138. OPA_PORT_PHYS_CONF_STANDARD = 1,
  139. OPA_PORT_PHYS_CONF_FIXED = 2,
  140. OPA_PORT_PHYS_CONF_VARIABLE = 3,
  141. OPA_PORT_PHYS_CONF_SI_PHOTO = 4
  142. };
  143. enum port_info_field_masks {
  144. /* vl.cap */
  145. OPA_PI_MASK_VL_CAP = 0x1F,
  146. /* port_states.ledenable_offlinereason */
  147. OPA_PI_MASK_OFFLINE_REASON = 0x0F,
  148. OPA_PI_MASK_LED_ENABLE = 0x40,
  149. /* port_states.unsleepstate_downdefstate */
  150. OPA_PI_MASK_UNSLEEP_STATE = 0xF0,
  151. OPA_PI_MASK_DOWNDEF_STATE = 0x0F,
  152. /* port_states.portphysstate_portstate */
  153. OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0,
  154. OPA_PI_MASK_PORT_STATE = 0x0F,
  155. /* port_phys_conf */
  156. OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F,
  157. /* collectivemask_multicastmask */
  158. OPA_PI_MASK_COLLECT_MASK = 0x38,
  159. OPA_PI_MASK_MULTICAST_MASK = 0x07,
  160. /* mkeyprotect_lmc */
  161. OPA_PI_MASK_MKEY_PROT_BIT = 0xC0,
  162. OPA_PI_MASK_LMC = 0x0F,
  163. /* smsl */
  164. OPA_PI_MASK_SMSL = 0x1F,
  165. /* partenforce_filterraw */
  166. /* Filter Raw In/Out bits 1 and 2 were removed */
  167. OPA_PI_MASK_LINKINIT_REASON = 0xF0,
  168. OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08,
  169. OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04,
  170. /* operational_vls */
  171. OPA_PI_MASK_OPERATIONAL_VL = 0x1F,
  172. /* sa_qp */
  173. OPA_PI_MASK_SA_QP = 0x00FFFFFF,
  174. /* sm_trap_qp */
  175. OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF,
  176. /* localphy_overrun_errors */
  177. OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0,
  178. OPA_PI_MASK_OVERRUN_ERRORS = 0x0F,
  179. /* clientrereg_subnettimeout */
  180. OPA_PI_MASK_CLIENT_REREGISTER = 0x80,
  181. OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F,
  182. /* port_link_mode */
  183. OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10),
  184. OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
  185. OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0),
  186. /* port_link_crc_mode */
  187. OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00,
  188. OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0,
  189. OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F,
  190. /* port_mode */
  191. OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001,
  192. OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002,
  193. OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004,
  194. OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008,
  195. OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010,
  196. OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020,
  197. OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040,
  198. /* flit_control.interleave */
  199. OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12),
  200. OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10),
  201. OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
  202. OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0),
  203. /* port_error_action */
  204. OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000,
  205. /* 7 bits reserved */
  206. OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000,
  207. OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000,
  208. OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000,
  209. OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000,
  210. OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000,
  211. OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000,
  212. OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000,
  213. OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000,
  214. /* 2 bits reserved */
  215. OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000,
  216. OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000,
  217. OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800,
  218. /* 1 bit reserved */
  219. OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200,
  220. /* 1 bit reserved */
  221. OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080,
  222. OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040,
  223. OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020,
  224. OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010,
  225. OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008,
  226. OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004,
  227. OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002,
  228. OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001,
  229. /* pass_through.res_drctl */
  230. OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01,
  231. /* buffer_units */
  232. OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11),
  233. OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6),
  234. OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3),
  235. OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0),
  236. /* neigh_mtu.pvlx_to_mtu */
  237. OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0,
  238. OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F,
  239. /* neigh_mtu.vlstall_hoq_life */
  240. OPA_PI_MASK_VL_STALL = (0x03 << 5),
  241. OPA_PI_MASK_HOQ_LIFE = (0x1F << 0),
  242. /* port_neigh_mode */
  243. OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3),
  244. OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2),
  245. OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0),
  246. /* resptime_value */
  247. OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F,
  248. /* mtucap */
  249. OPA_PI_MASK_MTU_CAP = 0x0F,
  250. };
  251. struct opa_port_states {
  252. u8 reserved;
  253. u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
  254. u8 reserved2;
  255. u8 portphysstate_portstate; /* 4 bits, 4 bits */
  256. };
  257. struct opa_port_state_info {
  258. struct opa_port_states port_states;
  259. __be16 link_width_downgrade_tx_active;
  260. __be16 link_width_downgrade_rx_active;
  261. };
  262. struct opa_port_info {
  263. __be32 lid;
  264. __be32 flow_control_mask;
  265. struct {
  266. u8 res; /* was inittype */
  267. u8 cap; /* 3 res, 5 bits */
  268. __be16 high_limit;
  269. __be16 preempt_limit;
  270. u8 arb_high_cap;
  271. u8 arb_low_cap;
  272. } vl;
  273. struct opa_port_states port_states;
  274. u8 port_phys_conf; /* 4 res, 4 bits */
  275. u8 collectivemask_multicastmask; /* 2 res, 3, 3 */
  276. u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */
  277. u8 smsl; /* 3 res, 5 bits */
  278. u8 partenforce_filterraw; /* bit fields */
  279. u8 operational_vls; /* 3 res, 5 bits */
  280. __be16 pkey_8b;
  281. __be16 pkey_10b;
  282. __be16 mkey_violations;
  283. __be16 pkey_violations;
  284. __be16 qkey_violations;
  285. __be32 sm_trap_qp; /* 8 bits, 24 bits */
  286. __be32 sa_qp; /* 8 bits, 24 bits */
  287. u8 neigh_port_num;
  288. u8 link_down_reason;
  289. u8 neigh_link_down_reason;
  290. u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */
  291. struct {
  292. __be16 supported;
  293. __be16 enabled;
  294. __be16 active;
  295. } link_speed;
  296. struct {
  297. __be16 supported;
  298. __be16 enabled;
  299. __be16 active;
  300. } link_width;
  301. struct {
  302. __be16 supported;
  303. __be16 enabled;
  304. __be16 tx_active;
  305. __be16 rx_active;
  306. } link_width_downgrade;
  307. __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */
  308. __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */
  309. __be16 port_mode; /* 9 res, bit fields */
  310. struct {
  311. __be16 supported;
  312. __be16 enabled;
  313. } port_packet_format;
  314. struct {
  315. __be16 interleave; /* 2 res, 2,2,5,5 */
  316. struct {
  317. __be16 min_initial;
  318. __be16 min_tail;
  319. u8 large_pkt_limit;
  320. u8 small_pkt_limit;
  321. u8 max_small_pkt_limit;
  322. u8 preemption_limit;
  323. } preemption;
  324. } flit_control;
  325. __be32 reserved4;
  326. __be32 port_error_action; /* bit field */
  327. struct {
  328. u8 egress_port;
  329. u8 res_drctl; /* 7 res, 1 */
  330. } pass_through;
  331. __be16 mkey_lease_period;
  332. __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */
  333. __be32 reserved5;
  334. __be32 sm_lid;
  335. __be64 mkey;
  336. __be64 subnet_prefix;
  337. struct {
  338. u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
  339. } neigh_mtu;
  340. struct {
  341. u8 vlstall_hoqlife; /* 3 bits, 5 bits */
  342. } xmit_q[OPA_MAX_VLS];
  343. struct {
  344. u8 addr[16];
  345. } ipaddr_ipv6;
  346. struct {
  347. u8 addr[4];
  348. } ipaddr_ipv4;
  349. u32 reserved6;
  350. u32 reserved7;
  351. u32 reserved8;
  352. __be64 neigh_node_guid;
  353. __be32 ib_cap_mask;
  354. __be16 reserved9; /* was ib_cap_mask2 */
  355. __be16 opa_cap_mask;
  356. __be32 reserved10; /* was link_roundtrip_latency */
  357. __be16 overall_buffer_space;
  358. __be16 reserved11; /* was max_credit_hint */
  359. __be16 diag_code;
  360. struct {
  361. u8 buffer;
  362. u8 wire;
  363. } replay_depth;
  364. u8 port_neigh_mode;
  365. u8 mtucap; /* 4 res, 4 bits */
  366. u8 resptimevalue; /* 3 res, 5 bits */
  367. u8 local_port_num;
  368. u8 reserved12;
  369. u8 reserved13; /* was guid_cap */
  370. } __attribute__ ((packed));
  371. #endif /* OPA_PORT_INFO_H */