sxgbe_platform.h 1.3 KB

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  1. /*
  2. * 10G controller driver for Samsung EXYNOS SoCs
  3. *
  4. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #ifndef __SXGBE_PLATFORM_H__
  14. #define __SXGBE_PLATFORM_H__
  15. /* MDC Clock Selection define*/
  16. #define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */
  17. #define SXGBE_CSR_150_250M 0x1 /* MDC = clk_scr_i/102 */
  18. #define SXGBE_CSR_250_300M 0x2 /* MDC = clk_scr_i/122 */
  19. #define SXGBE_CSR_300_350M 0x3 /* MDC = clk_scr_i/142 */
  20. #define SXGBE_CSR_350_400M 0x4 /* MDC = clk_scr_i/162 */
  21. #define SXGBE_CSR_400_500M 0x5 /* MDC = clk_scr_i/202 */
  22. /* Platfrom data for platform device structure's
  23. * platform_data field
  24. */
  25. struct sxgbe_mdio_bus_data {
  26. unsigned int phy_mask;
  27. int *irqs;
  28. int probed_phy_irq;
  29. };
  30. struct sxgbe_dma_cfg {
  31. int pbl;
  32. int fixed_burst;
  33. int burst_map;
  34. int adv_addr_mode;
  35. };
  36. struct sxgbe_plat_data {
  37. char *phy_bus_name;
  38. int bus_id;
  39. int phy_addr;
  40. int interface;
  41. struct sxgbe_mdio_bus_data *mdio_bus_data;
  42. struct sxgbe_dma_cfg *dma_cfg;
  43. int clk_csr;
  44. int pmt;
  45. int force_sf_dma_mode;
  46. int force_thresh_dma_mode;
  47. int riwt_off;
  48. };
  49. #endif /* __SXGBE_PLATFORM_H__ */