fsmc.h 4.0 KB

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  1. /*
  2. * incude/mtd/fsmc.h
  3. *
  4. * ST Microelectronics
  5. * Flexible Static Memory Controller (FSMC)
  6. * platform data interface and header file
  7. *
  8. * Copyright © 2010 ST Microelectronics
  9. * Vipin Kumar <vipin.kumar@st.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #ifndef __MTD_FSMC_H
  16. #define __MTD_FSMC_H
  17. #include <linux/io.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/mtd/physmap.h>
  20. #include <linux/types.h>
  21. #include <linux/mtd/partitions.h>
  22. #include <asm/param.h>
  23. #define FSMC_NAND_BW8 1
  24. #define FSMC_NAND_BW16 2
  25. #define FSMC_MAX_NOR_BANKS 4
  26. #define FSMC_MAX_NAND_BANKS 4
  27. #define FSMC_FLASH_WIDTH8 1
  28. #define FSMC_FLASH_WIDTH16 2
  29. /* fsmc controller registers for NOR flash */
  30. #define CTRL 0x0
  31. /* ctrl register definitions */
  32. #define BANK_ENABLE (1 << 0)
  33. #define MUXED (1 << 1)
  34. #define NOR_DEV (2 << 2)
  35. #define WIDTH_8 (0 << 4)
  36. #define WIDTH_16 (1 << 4)
  37. #define RSTPWRDWN (1 << 6)
  38. #define WPROT (1 << 7)
  39. #define WRT_ENABLE (1 << 12)
  40. #define WAIT_ENB (1 << 13)
  41. #define CTRL_TIM 0x4
  42. /* ctrl_tim register definitions */
  43. #define FSMC_NOR_BANK_SZ 0x8
  44. #define FSMC_NOR_REG_SIZE 0x40
  45. #define FSMC_NOR_REG(base, bank, reg) (base + \
  46. FSMC_NOR_BANK_SZ * (bank) + \
  47. reg)
  48. /* fsmc controller registers for NAND flash */
  49. #define PC 0x00
  50. /* pc register definitions */
  51. #define FSMC_RESET (1 << 0)
  52. #define FSMC_WAITON (1 << 1)
  53. #define FSMC_ENABLE (1 << 2)
  54. #define FSMC_DEVTYPE_NAND (1 << 3)
  55. #define FSMC_DEVWID_8 (0 << 4)
  56. #define FSMC_DEVWID_16 (1 << 4)
  57. #define FSMC_ECCEN (1 << 6)
  58. #define FSMC_ECCPLEN_512 (0 << 7)
  59. #define FSMC_ECCPLEN_256 (1 << 7)
  60. #define FSMC_TCLR_1 (1)
  61. #define FSMC_TCLR_SHIFT (9)
  62. #define FSMC_TCLR_MASK (0xF)
  63. #define FSMC_TAR_1 (1)
  64. #define FSMC_TAR_SHIFT (13)
  65. #define FSMC_TAR_MASK (0xF)
  66. #define STS 0x04
  67. /* sts register definitions */
  68. #define FSMC_CODE_RDY (1 << 15)
  69. #define COMM 0x08
  70. /* comm register definitions */
  71. #define FSMC_TSET_0 0
  72. #define FSMC_TSET_SHIFT 0
  73. #define FSMC_TSET_MASK 0xFF
  74. #define FSMC_TWAIT_6 6
  75. #define FSMC_TWAIT_SHIFT 8
  76. #define FSMC_TWAIT_MASK 0xFF
  77. #define FSMC_THOLD_4 4
  78. #define FSMC_THOLD_SHIFT 16
  79. #define FSMC_THOLD_MASK 0xFF
  80. #define FSMC_THIZ_1 1
  81. #define FSMC_THIZ_SHIFT 24
  82. #define FSMC_THIZ_MASK 0xFF
  83. #define ATTRIB 0x0C
  84. #define IOATA 0x10
  85. #define ECC1 0x14
  86. #define ECC2 0x18
  87. #define ECC3 0x1C
  88. #define FSMC_NAND_BANK_SZ 0x20
  89. #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
  90. (FSMC_NAND_BANK_SZ * (bank)) + \
  91. reg)
  92. #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
  93. struct fsmc_nand_timings {
  94. uint8_t tclr;
  95. uint8_t tar;
  96. uint8_t thiz;
  97. uint8_t thold;
  98. uint8_t twait;
  99. uint8_t tset;
  100. };
  101. enum access_mode {
  102. USE_DMA_ACCESS = 1,
  103. USE_WORD_ACCESS,
  104. };
  105. /**
  106. * fsmc_nand_platform_data - platform specific NAND controller config
  107. * @nand_timings: timing setup for the physical NAND interface
  108. * @partitions: partition table for the platform, use a default fallback
  109. * if this is NULL
  110. * @nr_partitions: the number of partitions in the previous entry
  111. * @options: different options for the driver
  112. * @width: bus width
  113. * @bank: default bank
  114. * @select_bank: callback to select a certain bank, this is
  115. * platform-specific. If the controller only supports one bank
  116. * this may be set to NULL
  117. */
  118. struct fsmc_nand_platform_data {
  119. struct fsmc_nand_timings *nand_timings;
  120. struct mtd_partition *partitions;
  121. unsigned int nr_partitions;
  122. unsigned int options;
  123. unsigned int width;
  124. unsigned int bank;
  125. enum access_mode mode;
  126. void (*select_bank)(uint32_t bank, uint32_t busw);
  127. /* priv structures for dma accesses */
  128. void *read_dma_priv;
  129. void *write_dma_priv;
  130. };
  131. extern int __init fsmc_nor_init(struct platform_device *pdev,
  132. unsigned long base, uint32_t bank, uint32_t width);
  133. extern void __init fsmc_init_board_info(struct platform_device *pdev,
  134. struct mtd_partition *partitions, unsigned int nr_partitions,
  135. unsigned int width);
  136. #endif /* __MTD_FSMC_H */